EP0257345A2 - Miroir de courant compensé - Google Patents

Miroir de courant compensé Download PDF

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Publication number
EP0257345A2
EP0257345A2 EP87111109A EP87111109A EP0257345A2 EP 0257345 A2 EP0257345 A2 EP 0257345A2 EP 87111109 A EP87111109 A EP 87111109A EP 87111109 A EP87111109 A EP 87111109A EP 0257345 A2 EP0257345 A2 EP 0257345A2
Authority
EP
European Patent Office
Prior art keywords
transistor
transistors
current
collector
current mirror
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP87111109A
Other languages
German (de)
English (en)
Other versions
EP0257345A3 (fr
Inventor
Stewart S. Taylor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Inc
Original Assignee
Tektronix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Publication of EP0257345A2 publication Critical patent/EP0257345A2/fr
Publication of EP0257345A3 publication Critical patent/EP0257345A3/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/265—Current mirrors using bipolar transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers

Definitions

  • the present invention relates in general to current mirrors and in particular to a current mirror utilizing a small capacitance for stability compensation.
  • Current mirrors are widely used in integrated circuits implementing operational amplifiers, digi­tal-to-analog converters, and the like to produce an output current which is substantially equal in magnitude to an input current.
  • One well known current mirror employs first and second matching bipolar transistors having interconnected bases and having emitters respectively coupled through matching first and second resistors to a common potential source. A collector voltage of the first transistor is fed back to the transistor bases through a unity gain amplifier to form a feedback loop. When an input current source is connected to the collector of the first transistor, the feedback loop adjusts the base voltage so that the collector of the first transistor carries the input current. Since the bases of the first and second transistors are interconnected, and since the first and second resistors as well as the transistors are matched, the second transistor produces an output collector current substantially equal in magnitude to the input current.
  • the feedback loop is altered by connecting a compensating capacitor between the collector of the first transistor and the common potential source, the capacitor being sized to adjust the frequency, at which the absolute value of the open loop gain of the feedback loop is unity, to less than the short-circuit current gain-bandwidth product (f T ) of the first transistor.
  • the parameter f T is an inherent characteristic and is defined as the frequency at which the short-circuit common-emitter current gain of the transistor attains unity magnitude.
  • the size of the compensating capacitor needed to insure circuit stability may exceed the maximum capacitance which can be realized on an integrated circuit or may require much more chip area than can be economically justified, particularly when there is no thin oxide dielectric layer on the chip for allowing higher capacitances to be realized.
  • the requirement for a large capacitance is aggra­vated as the collector currents of the transistors become large, increasing the transconductance of the transistors.
  • the compensating capa­citor must be implemented in the form of a more complex and expensive discrete component connected to external terminals of the chip, consuming package pins and increasing packaging cost. What is needed is a stable, compensated current mirror which may be implemented with transistors having a low current gain-bandwidth product, without requiring a large, discrete compensating capacitance.
  • a current mirror includes first and second transistors having bases connected together and having emitters respectively coupled through first and second load resistors to a common potential source.
  • a voltage on the collector of the first transistor is fed back to the transistor bases through a unity gain amplifier with a series con­nected output resistor to form a feedback loop for controlling the voltage at the bases of the transistors.
  • the feedback loop adjusts the base voltage of the first transistor so that its collector carries substantially all of the input current provided by the current source. Since the bases of the first and second transistors are interconnected, and since the first and second resistors and transis­tors are matched, the second transistor produces an output collector current substantially equal to the input current in the collector of the first transistor.
  • a feedback capacitor is coupled between the base and collector of the first transistor.
  • the feedback capacitor and the series output resistor of the unity gain amplifier are sized to reduce the frequency, at which the absolute value of the open loop gain of the feedback loop is unity, to less than or equal to the short-circuit current gain-bandwidth product of the first transistor.
  • the transistors have low short-circuit current gain-bandwidth pro­ducts, as in the case when the transistors are implemented as lateral pnp junction transistors or are operated at high collector current, placing the feedback capacitor between the collector and the base of the first transistor, rather than between the first transistor collector and the common poten­tial source, and choosing an appropriate value of feedback loop resistor, reduces the size of feedback capacitor required to ensure stability.
  • the feed­back capacitor is small enough to be implemented on the same integrated circuit as the transistors, thereby eliminating the need for a discrete external capacitor component and its associated cost and complexity.
  • the present invention relates to an improvement over the current mirror circuit of the prior art and therefore it is instructive to describe the prior art current mirror first.
  • the current mirror 10 of the prior art is adapted to produce an output current I2 substantially equal in magnitude to an input current I1 from a current source 11 (which may or may not be an ideal current source).
  • Current mirror 10 includes a pair of matching pnp transistors Q1 and Q2 having interconnected bases and having emitters coupled through similar resistors R1 and R2 to a common potential source V cc .
  • the collector of transistor Q1 is coupled to the base of another pnp transistor Q3 and the emitter of transistor Q3 is connected to the bases of transistors Q1 and Q2.
  • transistor Q3 The collector of transistor Q3 is grounded while the collector of transistor Q2 is coupled to ground through load resistor RL.
  • transistor Q3 acts as a unity gain buffering ampli­fier to control the base voltage on transistor Q1 such that the collector of transistor Q1 carries the input current I1. Since the bases of transistors Q1 and Q2 are tied together, since transistors Q1 and Q2 have matching characteristics, and since resistors R1 and R2 have similar resistance, transistor Q2 produces an output collector current I2 which is substantially equal in magnitude to current I1 carried by the collector of transistor Q1.
  • a compensating capacitor C1 is suitably connected between the collector of transistor Q1 and potential source V cc , capacitor C1 being sized so as to limit f u to less than f T .
  • FIG. 2 is a combination schematic and block diagram illustrating an equivalent circuit of the feedback loop formed by transistors Q1 and Q3 as well as resistor R1 and capacitor C1 when the loop is opened at a point 12 between the base of transistor Q3 and the collector of transistor Q1.
  • Transistor Q3 of FIG. 1 is represented by a unity gain amplifier 14, an approximation of the small signal behavior of Q3.
  • Tran­sistor Q1 of FIG. 1 acts as a common-emitter amplifier with emitter degeneration provided by resistor R1 and is represented in FIG.
  • an inverting transconductance amplifier 16 producing an output current (at the col­lector current of Q1) which is proportional to an input voltage (the base voltage of Q1), the ratio of propor­tionality being the transconductance G m of the ampli­fier.
  • amplifier transconductance G m is ap­proximately g m /(1+g m R1) where g m is the transconduc­tance of transistor Q1, the ratio of collector cur­rent to the thermal voltage V T of the base-emitter junction and R1 is the emitter degeneration resis­ tance.
  • the thermal voltage V T is equal to Boltzman's constant K times the absolute temperature of the junction divided by the charge on an electron.
  • the output of amplifier 16 is coupled to ground through the parallel combination of capacitor C1 and a resistance Rc representing the total resistance to ground from the collector of transistor Q1 of FIG. 1, including the high internal resistance of current source 11, and the high resistances to ground through tran­sistor Q3 and through resistor R1 via transistor Q1.
  • a small signal input voltage v i applied to the input of amplifier 14 results in a proportional small signal cur­rent output in amplifier 16 applied to the parallel com­bination of Rc and C1.
  • the frequency ⁇ u ( 2 ⁇ f u ) at which the magnitude of the open loop gain
  • is equal to 1 is approximately equal to 1/R1C1.
  • f u not exceed f T in order to insure that the feedback loop formed by transistors Q1 and Q3 remain stable.
  • the f T of the transistors is relatively low, approxi­mately 5-40 MHz. Assuming for example, that f T is 10 MHz and R1 is 500 Ohms, a compensating capaci­tor C1 having a value of at least 31.8 pF would be required.
  • FIG. 3 there is depicted in com­bination block and circuit diagram form a current mirror 20 according to the present invention adapted to produce an output current I4 through a load resistor RL ⁇ , wherein the magnitude of I4 is equal to the magnitude of an input current I3 from a current source 21.
  • Current mirror 20 includes a matching pair of pnp transistors Q4 and Q5 having interconnected bases and having their emitters coupled through matching first and second load resistors R3 and R4 to a common potential source V cc .
  • the collector of transistor Q4 is connected to the input of a unity gain amplifier 22, while the output of amplifier 22 is coupled to the bases of transistors Q4 and Q5 through a series resistor R5.
  • the collector of transistor Q5 is coupled to ground through the load resistor RL ⁇ .
  • the collector of transistor Q4 is coupled to its base through a capacitor C2.
  • Amplifier 22 provides feedback to the base of transistor Q4 through R5, which feedback allows Q4 to carry current I3 when current source 21 is connected to the collector of Q4.
  • Capacitor C2 is provided to stabilize the feedback loop in the circuit according to the present invention.
  • FIG. 4 is a combination schematic and block diagram representation of an equivalent circuit of the feedback loop when the loop is opened at point 24 between the input of unity gain amplifier 22 and the collector of transistor Q4.
  • Transistor Q4 of FIG. 3 (like transistor Q1 of FIG. 1) acts as a common-emitter amplifier with emitter degeneration provided by resistor R3 and is represented in FIG. 4 by an inverting transconductance amplifier 26 having a transconductance G m of approximately g m /(1+g m R3) where g m is the transconductance of transistor Q4.
  • the output of amplifier 26 is coupled to ground through a resistance Rc ⁇ repre­senting the relatively high resistance between the collector of transistor Q4 of FIG. 1 and ground.
  • the output v o of amplifier 26 (corresponding to the collector voltage of transistor Q4 of FIG. 3) is fed back to its input (i.e. to the base of transistor Q4) through capacitor C2. Due to feedback from capacitor C2 and the voltage gain provided by ampli­fier 26 acting through the high impedance Rc ⁇ , the input of amplifier 26 is at virtual ground.
  • a small signal input voltage v i is applied to the input of amplifier 22 and the output of ampli­fier 22 is coupled through resistor R5 to the input of amplifier 26.
  • Amplifier 22 and resistor R5 form another transconductance amplifier 28 having a transconductance G m1 of 1/R5 which pro­duces an output current of magnitude v i /R5. Since the input impedance of amplifier 26 is relatively high, substantially all of the output current of transconductance amplifier 28 passes through capa­citor C2 and the potential developed across C2 is approximately equal to v i /j ⁇ R5C2. Since the input of amplifier 26 is at virtual ground, the output voltage v o is also approximately equal to v i /j ⁇ R5C2. Therefore the absolute value of the open loop gain
  • the frequency ⁇ u ( 2 ⁇ f u ) at which
  • is equal to 1 is approximately equal to 1/R5C2.
  • the value of the transfer function is indepen­dent of the transconductance G m of amplifier 26 and therefore is independent of the value of R3.
  • Resistor R5 may be relatively large (for example, 10K Ohms) without disrupting circuit operation by dropping an excessively large voltage.
  • the current mirror circuit 20 of FIG. 3 does not require the use of an off-chip capacitor or integrated capacitor requiring a large chip area, for feedback loop stabilization when the transistors Q4 and Q5 have low f T and/or when the transconductance of Q4 is very large.
  • capa­citor C2 in the circuit of FIG. 3 introduces a right half plane zero at a frequency f z of approxi­mately 1/2 ⁇ R3C2 which can cause ringing if f z occurs too close to f u . Since f z /f u is approxi­mately equal to R5/R3, R5 is selected to be at least several times larger than R3.
  • the current mirror 20 of FIG. 3 is depicted in schematic diagram form including a more detailed embodiment of amplifier 22 of FIG. 3.
  • the current mirror 20 of FIG. 5 includes pnp transistors Q4 and Q5 having interconnected bases and having emitters respec­tively coupled through matching first and second load resistors R3 and R4 to the common potential source V cc .
  • the collector of transistor Q5 is coupled to ground through resistor RL ⁇ and the collector of transistor Q4 is applied to the base of an npn transistor Q6.
  • the potential source V cc is supplied to the collector of transistor Q6 while a current source 23 is connected to the emitter of transistor Q6.
  • the emitter of transistor Q6 is further coupled to the base of pnp transistor Q7 through resistor R5 and the collector of transistor Q4 is coupled to the base of transistor Q7 through capacitor C2.
  • the emitter of transistor Q7 is attached to the bases of transistors Q4 and Q5 with the collector of transistor Q7 being grounded.
  • Transistor Q6 acts as an emitter follower to fulfill the function of unity gain amplifier 22 of FIG. 3 by producing an output signal at its emitter which varies with the input signal at its base. Since the emitter voltage of Q6 is one pn junction drop below the collector voltage on transistor Q4, transistor Q7 is employed to level shift upward, by one pn junction drop, the feedback voltage produced by transistor Q6 and resistor R5 before the feed­back voltage is applied to the bases of transistors Q4 and Q5. The current gain of Q7 also keeps the DC current through R5 small, enabling R5 to be relatively large in magnitude if required.
  • Capaci­tor C2 may be connected to the base of transistor Q7 as shown in FIG. 5 or, in an alternative embodi­ment, may be connected directly to the bases of transistors Q4 and Q5.
  • a capacitor C3 connected between V cc and the collector of tran­sistor Q4 of FIG. 5 may be additionally useful to reduce ringing.
  • magni­tude of such additional capacitor C3 can be quite small, on the order of a few pF, so it may also be implemented in integrated circuit form.
  • the current mirror 20 of the present invention is adapted to produce an output current substan­tially equal in magnitude to an input current, uti­lizing transistors having a low short-circuit cur­rent gain-bandwidth product and/or large transcon­ductances, without requiring a large compensating capacitor to ensure stability. While the preferred embodiment of the present invention employs bipolar pnp junction transistors, the present invention may be implemented utilizing various types of tran­sistors including npn junction transistors, MOSFETS, MESFETS or the like wherein a voltage applied to a control terminal (such as a transistor base or gate) can control a current through two load terminals (such as an emitter and a collector, or a drain and a source).
  • a control terminal such as a transistor base or gate
  • the present invention may also be used in current mirrors in which the output current is scaled to, rather than equal to, the input current by scaling the emitter areas of Q4 and Q5 and the ratio of R3 and R4.
  • the invention is suitable for compensating current mirrors (sources or sinks) providing a multiplicity of output cur­rents proportional to the input current through a multiplicity of transistors Q5 having bases con­nected to the base of transistor Q4 and having emitters coupled to V cc through separate emitter resistors.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
EP87111109A 1986-08-21 1987-07-31 Miroir de courant compensé Withdrawn EP0257345A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/898,661 US4769619A (en) 1986-08-21 1986-08-21 Compensated current mirror
US898661 1986-08-21

Publications (2)

Publication Number Publication Date
EP0257345A2 true EP0257345A2 (fr) 1988-03-02
EP0257345A3 EP0257345A3 (fr) 1989-04-26

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EP87111109A Withdrawn EP0257345A3 (fr) 1986-08-21 1987-07-31 Miroir de courant compensé

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US (1) US4769619A (fr)
EP (1) EP0257345A3 (fr)
JP (1) JPS6354006A (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0488315A2 (fr) * 1990-11-29 1992-06-03 Brooktree Corporation Un miroir de courant en cascode symétrique
EP0526423A1 (fr) * 1991-07-29 1993-02-03 STMicroelectronics S.r.l. Amplificateur intégré de mesure à entrée différentiel et une source d'alimentation à capacité de compensation de fréquence intégrée
EP0531163A1 (fr) * 1991-09-05 1993-03-10 Sony Corporation Amplificateur audio
CN1061187C (zh) * 1993-07-12 2001-01-24 哈里斯公司 具有单偏置单元的低压射频放大器和混频器及其方法
EP1724885A1 (fr) * 2003-05-14 2006-11-22 ATMEL Germany GmbH Circuit de commande pour élément électronique

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4820968A (en) * 1988-07-27 1989-04-11 Harris Corporation Compensated current sensing circuit
US5032774B1 (en) * 1989-05-09 1996-04-23 United Technologies Automotive Circuit sensing circuit for use with a current controlling device in a power delivery circuit
US5210475B1 (en) * 1989-05-09 1996-04-23 United Technologies Automotive Circuit sensing circuit for use with a current controlling device in a power delivery circuit
DE69033248T2 (de) * 1989-05-09 2000-03-16 Ut Automotive Dearborn Inc Schaltung zur Leistungsabgabe mit Stromerfassung
US5495155A (en) * 1991-06-28 1996-02-27 United Technologies Corporation Device in a power delivery circuit
JPH05219443A (ja) * 1992-02-05 1993-08-27 Minolta Camera Co Ltd 固体撮像装置
US5373253A (en) * 1993-09-20 1994-12-13 International Business Machines Corporation Monolithic current mirror circuit employing voltage feedback for β-independent dynamic range
US5646520A (en) * 1994-06-28 1997-07-08 National Semiconductor Corporation Methods and apparatus for sensing currents
US6255897B1 (en) * 1998-09-28 2001-07-03 Ericsson Inc. Current biasing circuit
WO2000031604A1 (fr) * 1998-11-20 2000-06-02 Koninklijke Philips Electronics N.V. Circuit miroir de courant
EP1316005B1 (fr) * 2000-09-01 2005-11-09 Koninklijke Philips Electronics N.V. Circuit miroir de courant
US6545540B1 (en) * 2000-10-11 2003-04-08 Intersil Americas Inc. Current mirror-embedded low-pass filter for subscriber line interface circuit applications
US6657481B2 (en) * 2002-04-23 2003-12-02 Nokia Corporation Current mirror circuit
US7781985B2 (en) * 2007-09-27 2010-08-24 Osram Sylvania Inc. Constant current driver circuit with voltage compensated current sense mirror
US20110121888A1 (en) * 2009-11-23 2011-05-26 Dario Giotta Leakage current compensation
IT201900006715A1 (it) * 2019-05-10 2020-11-10 St Microelectronics Srl Circuito di compensazione in frequenza e dispositivo corrispondente

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0067447A2 (fr) * 1981-06-15 1982-12-22 Kabushiki Kaisha Toshiba Circuit miroir de courant
EP0209334A1 (fr) * 1985-07-17 1987-01-21 Kabushiki Kaisha Toshiba Circuit miroir de courant

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59229908A (ja) * 1983-05-27 1984-12-24 Rohm Co Ltd 電流反転回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0067447A2 (fr) * 1981-06-15 1982-12-22 Kabushiki Kaisha Toshiba Circuit miroir de courant
EP0209334A1 (fr) * 1985-07-17 1987-01-21 Kabushiki Kaisha Toshiba Circuit miroir de courant

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0488315A2 (fr) * 1990-11-29 1992-06-03 Brooktree Corporation Un miroir de courant en cascode symétrique
EP0488315A3 (en) * 1990-11-29 1993-03-31 Brooktree Corporation A balanced cascode current mirror
EP0526423A1 (fr) * 1991-07-29 1993-02-03 STMicroelectronics S.r.l. Amplificateur intégré de mesure à entrée différentiel et une source d'alimentation à capacité de compensation de fréquence intégrée
US5258723A (en) * 1991-07-29 1993-11-02 Sgs-Thomson Microelectronics, S.R.L. Integrated instrumentation amplifier with integrated frequency-compensating capacitance
EP0531163A1 (fr) * 1991-09-05 1993-03-10 Sony Corporation Amplificateur audio
CN1061187C (zh) * 1993-07-12 2001-01-24 哈里斯公司 具有单偏置单元的低压射频放大器和混频器及其方法
EP1724885A1 (fr) * 2003-05-14 2006-11-22 ATMEL Germany GmbH Circuit de commande pour élément électronique

Also Published As

Publication number Publication date
JPS6354006A (ja) 1988-03-08
EP0257345A3 (fr) 1989-04-26
US4769619A (en) 1988-09-06

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