EP0257162B1 - Gerät zur Zusammenstellung von Farbsignalkomponenten aus Helligkeits- und Chrominanzsignalen und diese Anwendung umfassendes Video-Anzeigegerät - Google Patents

Gerät zur Zusammenstellung von Farbsignalkomponenten aus Helligkeits- und Chrominanzsignalen und diese Anwendung umfassendes Video-Anzeigegerät Download PDF

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Publication number
EP0257162B1
EP0257162B1 EP19860401766 EP86401766A EP0257162B1 EP 0257162 B1 EP0257162 B1 EP 0257162B1 EP 19860401766 EP19860401766 EP 19860401766 EP 86401766 A EP86401766 A EP 86401766A EP 0257162 B1 EP0257162 B1 EP 0257162B1
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EP
European Patent Office
Prior art keywords
luminance
signals
chrominance
display
photographic
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
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EP19860401766
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English (en)
French (fr)
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EP0257162A1 (de
Inventor
Gerard Chauvel
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Texas Instruments France SAS
Texas Instruments Inc
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Texas Instruments France SAS
Texas Instruments Inc
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Priority to FR8511252A priority Critical patent/FR2585530B1/fr
Application filed by Texas Instruments France SAS, Texas Instruments Inc filed Critical Texas Instruments France SAS
Priority to EP19860401766 priority patent/EP0257162B1/de
Priority to DE8686401766T priority patent/DE3682067D1/de
Publication of EP0257162A1 publication Critical patent/EP0257162A1/de
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Publication of EP0257162B1 publication Critical patent/EP0257162B1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed

Definitions

  • the present invention relates to display devices for a television screen and more particularly relates to video image display devices on a line-by-line and dot-by-dot scanning screen of use in particular for displaying images in computer industry systems.
  • a display device in which the image is formed on the screen with the following elements : a page memory which contains the television description of the image to be displayed ; an address processor which computes the addresses of access to the page memory as a function of the signals it receives from a time base ; a display processor which contains all the elements for controlling the scanning and the red R, green G, blue B inputs of a television set or monitor ; the data of the page memory are transferred in the display processor so as to generate R.G.B. signals at the scanning rate issuing from the time base ; a central processing unit associated with an interface circuit which permits the loading of the contents of the page memory for subsequent display.
  • the address processor uses at the minimum two basic address BAZA and display zone PZA pointers in the registers of the address processor. During the signal of the beginning of the raster issuing from the time base, the signal of the beginning of the page memory to be displayed BAZA is transferred in PZA.
  • each Req. visu signal issuing from the time base is transmitted to a dynamic access control device DMA associated with the address register and which generates a visualization cycle for extracting the characteristics of the following dots in the page memory.
  • the DMA device produces four CAS signals which permit the extraction of four words from the page memory for each Req. visu demand.
  • the four words are transferred to four plane registers which await the loading thereof in shifter registers associated with the display monitor.
  • each word is composed of 16 bits.
  • Four words therefore permit the choice of a colour among sixteen for the following dots.
  • the shifter registers associated with the monitor select an address of a palette memory which contains the colour correspondence between the information contained in the planes of the page memory and the R.G.B. outputs through analog-digital converters interposed between the palette memory and the display monitor.
  • This display technique is well adapted to the graphic mode which requires a sudden change in the colour for each point of the screen.
  • the restoring will not require more than sixty-four colours.
  • the same image quality may be restored according to the photo type with 4, 5 or 6 bits.
  • the DPCM technique employs the following characteristics : In a photographic image, if the difference of level of each R.G.B. component of a dot of the image to the following dot is analyzed, it is found that 75 % of the spacings between dots are less than 1/256, assuming that there are 256 levels of luminance on each component.
  • 50 % of the spacings are less than 2/256.
  • 5 % of the spacings are less than 10/256.
  • the DPCM technique consists in loading in the page memory the spacings relating to a component.
  • the images of graphic type are generally coded in a graphic mode and most television sets accept items of information coded in R.G.B.
  • An object of the invention is to provide a device which permits the conversion of the luminance and chrominance coded pictures into R.G.B. levels so as to be in a position to display indifferently images in the graphic and photographic mode in the same image on a television set having R.G.B. inputs.
  • the invention therefore provides a device for the composition of color component signals from encoded luminance and chrominance signals, comprising means for computing the relationships relating said encoded luminance and chrominance signals with the color components derived therefrom, said computing means including decoding means for decoding said luminance and chrominance signals, and means for matrixing said decoded luminance and chrominance signals in accordance with relations established between said luminance and chrominance signals on one hand, and said color components on the other hand, characterised in that said luminance and chrominance signals are encoded as differential pulse code modulation DPCM signals, and in that said decoding means and said matrixing means consist only of digital logical means.
  • the invention also provides a device for the composition of the type defined hereinbefore, wherein said matrixing means comprise as many matrixing circuits as there are colour components to be obtained and are each constituted by at least one adder adapted to restore the corresponding colour component by effecting the relation relating said colour component with the luminance and chrominance values obtained at the output of the decoder.
  • said matrixing means comprise as many matrixing circuits as there are colour components to be obtained and are each constituted by at least one adder adapted to restore the corresponding colour component by effecting the relation relating said colour component with the luminance and chrominance values obtained at the output of the decoder.
  • FIG. 1 illustrates the procedure for converting items of information to which the invention is applied for the purpose of achieving the desired display.
  • This procedure comprises storing in memory at 1 the data relating to an RGB coded reference photographic image.
  • This reference image is for example encoded on eight bits by R, G and B components, namely on in all twenty four bits.
  • the R, G, B signals are encoded at 2 into luminance signals Y and chrominance signals DR and DB.
  • the reference image is RGB coded with eight resolution bits per R, G, B component, namely 256 levels.
  • the histogram of Fig. 6 represents a curve C1 showing the distribution of the differences of luminance between two neighbouring dots and a curve C2 showing the differences of chrominance which are preferably identical for DR and DB.
  • Each image has its own histogram.
  • quantization values are generally very close from one image to another.
  • quantization values may be selected :
  • the curve I is an example of a variation in luminance during the scanning of a line.
  • the planes Y of the page memory are loaded with the codes corresponding to these values.
  • the DPCM decoding is effected at 6 in the course of which the loading of the quantization values and the restoration of Y, DR and DB are achieved.
  • the matrixing device according to the invention is fully digital and can therefore be applied to the integrated LSI circuits.
  • the display shown in Fig. 2 comprises : a central processing unit 10,termed hereinafter CPU,which is adapted to manage all the operations of the system by means of a program contained in its own memory ; a video display processor 11,termed hereinafter VDP, communicating with the CPU 10, through a bus 12 and a control line 13, the circulation of the data on the bus 12 being ensured in time multiplexing for addresses and data in accordance with the procedure disclosed in particular in FR-A-2541805 filed on February 25, 1983 in the name of the Applicant ; a dynamic general memory 14, termed hereinafter DRAM, which can communicate with the other elements of the system through a time division bus 15, the latter being connected in particular to the CPU 10 through an interface 16 ; a display unit 17 which may be a conventional television set or an equally conventional monitor, this element being adapted to display visual information produced in the system ; an external unit 18 or Didon by means of which the system of Fig.
  • the external unit 18 may load the information into the memory 14 to permit, after processing in the system, their display on the screen of the display unit 17.
  • the video display processor 11 comprises an address processor 19, a point processor 20 adapted to effect the processing of the dots or"pixels" of the screen of the unit 17, for example for obtaining a change in shapes in the image and a display processor 21, these elements communicating with each other through the time division bus 15 and a bus 22 on which solely data may circulate.
  • the buses 15 and 22 are connected to the DRAM memory 14 through an interface 23 permitting the multiplexing of the data and addresses intended for the DRAM 14.
  • DMA dynamic access control device 24 of dynamic access to the DRAM memory 14.
  • This device hereinafter termed DMA, has been disclosed in detail in FR-A-2 406 250 and in the French patent application 83 03143 filed on February 24, 1983 both in the name of the Applicant.
  • a time base circuit 25 is associated with the display processor 21 and in particular communicates with the DMA circuit 24, the monitor 17 and the display processor 21 itself.
  • Fig. 3 essentially represents the elements of the device which are part of the display processor 21 of the device of Fig. 2.
  • the DRAM memory 14 is connected through the bus 22 to a group of plane registers 26 which may be loaded by the dot processor 20 (Fig. 2) or the DRAM memory 14.
  • the plane registers 26 are connected to shift registers 27 in the graphic mode whose outputs are connected to a RAM memory 28 or colour palette memory.
  • the clock inputs of the registers 27 are connected to the time base 25. Normally, the shifting frequency is equal to the frequency at which the dots are displayed on the screen.
  • the shifter registers 27 may be loaded by the group of plane registers 26 and by a register 29, termed "base colour register" which is part of an attribute storing unit 30.
  • the unit 30 may be loaded by the bus 15, for example from the memory 14 or the CPU 10.
  • the circuit of Fig. 3 further comprises, according to the invention, a series of shifter registers 31 in photographic mode whose inputs are connected to the plane registers 26 and whose outputs are connected to a first series of inputs of a circuit 32 producing quantization values.
  • a second series of inputs of the circuit 32 is connected to the address and data inputs of the colour palette memory 28.
  • the circuit 32 producing quantization values is connected to a photographic unit 33 with which is associated a matrixing device 34, the two latter circuits being part of the construction of the device converting the luminance and chrominance signals into R, G, B signals which will be described with reference to Fig. 4.
  • the outputs of the matrixing circuit are connected to a circuit 35 processing R, G, B signals of graphic and/or photographic origin which will be described in detail with reference to Fig. 5.
  • the circuit 35 is moreover connected by corresponding inputs GR, GG, GB to the outputs GR, GG, GB of the colour palette memory 28.
  • the outputs of the processing circuit 35 are connected to the corresponding inputs of digital-analog converters 38, which are connected to the R, G, B terminals of the monitor 17 (Fig. 2).
  • This device which includes the photographic unit 33, the matrixing circuit 34, the processing circuit 35 and the digital-analog converters 38, comprises : DPCM decoders 40, 41, 42 ; R, G, B matrixing devices 43, 44, 45, 46 ; the processing device 35 (Fig. 3) ; the digital-analog converters 38, and a control logic 47.
  • the corresponding DPCM decoder For each of the channels Y, DR, and DB, the corresponding DPCM decoder comprises an adder 48, 49, 50 whose outputs are connected to a register 51, 52, 53 which stores in memory at each clock signal CPR, CPB, the result of the operation between the value it contains before the clock signal with the quantization value QC or QY delivered by the quantization memory.
  • the register 51 is forced to zero by the gate 54.
  • DR is equal to zero.
  • the samples ⁇ DR are presented to the input of the adder before each clock signal CPR.
  • the DPCM decoder 42 of the channel Y uses the same principle, except that the operation is carried out for each clock cycle CP.
  • the R, G, B matrixing circuit is composed of four adders 43, 44, 45, 46.
  • the inverted ouputs S of the adder 44 give the complement at "1", S , of the result.
  • the adder 46 effects the following operation :
  • formula (b) which corresponds to the RGB matrixing technique, permits the calculation of the quantization values and the content of the planes ⁇ Y0, ⁇ Y1, ⁇ Y2 ⁇ DR0/ ⁇ DB0, ⁇ DR1/ ⁇ DB1 and ⁇ DR2/ ⁇ DB2 which will permit decompressing in real time the values of Y, DR and DB.
  • These values applied in the manner described to the matrixing system enables a correct image quality to be restored.
  • the conversion device described with reference to Fig. 4 comprises a gate 54 which has an input PCOUL. A signal applied to this input forces the registers 51 to 52 to zero when it is itself at zero level.
  • the adders 43, 46, 45 each have an input SO.
  • the signal SO applied to these adders permits a selection of the input B on the outputs of the adders.
  • the signal P/G applied to the logic 47 determines the duration of a window of photographic type during the scanning of a line.
  • the retarded P/G signal permits a selection either of the image of graphic type whose data issue directly from the registers 27 through the palette 28, or an image of photographic type.
  • This circuit essentially comprises a multiplexer 60 having inputs 61 of PR, PG, PB photographic signals connected to the output of the matrixing circuit 34 (Fig. 3) and inputs 62 of GR, GG, GB graphic signals, connected to the corresponding outputs of the colour palette memory 28.
  • An OR gate 63 for determining the graphic mode or photographic mode has its three inputs respectively connected to the GR, GG, GB inputs of the multiplexer 60, while its output is connected to a mode control input of said multiplexer.
  • the processing circuit 35 finally includes a logic 64 for controlling the multiplexer having a input G adapted to receive data relating to the number of graphic planes and an input P adapted to receive date relating to the number of photographic planes.
  • the outputs of the multiplexer are connected to the digital-analog converters 38.
  • the data are loaded into the plane registers 26 then transferred into the graphic shifter registers 27 whose ouputs select a colour in the palette memory 28 at the rate of the dot frequency.
  • the GR, GG and GB components applied to the processing circuit 35 are oriented directly by the latter to the digital-analog converters 38 so as to be than transmitted to the monitor 17.
  • the luminance and chrominance data are loaded into the plane registers 26 in the same way as in the graphic mode, and then transferred to the photographic shifter register 31 whose outputs select quantization values of luminance QY and chrominance QC.
  • quantization values form a correspondence table relating to the differences of luminance or chrominance between neighbouring dots loaded into the photographic shifter registers 31.
  • the quantization values QY and QC are transmitted to the photographic unit 33 which delivers, in association with the matrixing circuit 34, in the manner indicated in the description relation to Fig. 4, colour components PR, PG and PB which, when applied to the processing circuit 35, will appear on the converters 38 for the purpose of being displayed.
  • the processing circuit 35 performs a function of selecting between the graphic GR, GG, GB components, and the photographic PR, PG, PB components.
  • the shifter registers 27 and 31 are also used alternately.
  • the choice between an image processed in the photographic mode or in the graphic mode is made by the attributes register 29.
  • the content of the plane register 26 will be transferred suitably to the graphic and photographic shifter registers 27 and 31.
  • the two groups of registers will this time operate in parallel at the rate of the point frequency and will select, on one hand, graphic GR, GG, GB components issuing from the colour palette 28 and, on the other hand, quantization values which, when applied to the photographic unit 33, will permit the production of the PR, PG, PB colour components.
  • the processing circuit 35 shown in Fig. 5 performs different functions depending on the envisaged display mode.
  • the register 29 is modified in the course of the line scanning and raster scanning and alternatively, there may be had graphic zones which will select the multiplexer 60 on the GR, GG, GB channel or photographic zones which will select the multiplexer on the PR, PG, PB channel.
  • the OR gate 63 produces a level 1 which selects by the multiplexer 60 the PR, PG, PB photographic channel.
  • the multiplexer selects the graphic channel.
  • This for example permits superimposing text or curves on a photographic image dot by dot, the shape of the letters or of the curves appearing in the chosen colour on the photographic image.
  • the device for converting luminance and chrominance signals into RGB signals which has been described with reference to Fig. 4 has been considered to be applied to a graphic-photographic display device.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Color Television Systems (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Processing Of Color Television Signals (AREA)

Claims (8)

  1. Gerät zur Zusammenstellung von Farbsignalkomponenten aus codierten Luminanz- und Chrominanzsignalen mit Mitteln zum Berechnen der Beziehungen zwischen den codierten Luminanz- und Chrominanzsignalen und den daraus abgeleiteten Farbkomponenten, wobei die Berechnungsmittel Decodiervorrichtungen (40, 41, 42) zum Decodieren der Luminanz- und Chrominanzsignale sowie Vorrichtungen (43, 44, 45, 46) zum Matrizieren der decodierten Luminanz- und Chrominanzsignale entsprechend den zwischen den Luminanz- und Chrominanzsignalen einerseits und den Farbkomponenten andererseits festgestellten Beziehungen enthalten, dadurch gekennzeichnet, daß die Luminanz- und Chrominanzsignale durch differentielle Puls-Code-Modulation (DPCM) modulierte Signale sind und daß die Decodiervorrichtungen und die Matriziervorrichtungen ausschließlich aus digitalen Logikmitteln bestehen.
  2. Gerät nach Anspruch 1, dadurch gekennzeichnet, daß die Logikmittel zum Decodieren der Luminanz- und Chrominanzsignale pro zu erhaltender Farbkomponente einen DPCM-Decodierer enthalten, von denen jeder einen Addierer (48, 49, 50) von Luminanz- und Chrominanz-Quantisierungswerten umfaßt, die durch Selektion nach Vergleich der Luminanz- und Chrominanz-Werte zwischen benachbarten Punkten erhalten worden sind, und ferner ein Register (51, 52, 53) enthalten, das von einer Torschaltung (54) zum Übertragen der in dem entsprechenden Addierer enthaltenen Signale zu der zugehörigen digitalen Matrizierschaltung (43, 44, 45, 46) gesteuert wird.
  3. Gerät nach Anspruch 2, dadurch gekennzeichnet, daß die Torschaltung (54) einen Eingang (PCOUL) aufweist, der den Übergang von der Farbwiedergabe zu der Schwarz-Weiß-Wiedergabe steuert.
  4. Gerät nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß die digitalen Matrixiervorrichtungen ebensoviele digitale Matrixierschaltungen enthalten, wie zu erhaltende Farbkomponenten vorhanden sind und jeweils von wenigstens einem Addierer (43, 44, 46, 45) gebildet sind, der geeignet ist, die entsprechende Farbkomponente wiederherzustellen, indem die Beziehung bewirkt wird, mit der die Farbkomponente mit den Luminanz- und Chrominanz-Werten in Beziehung steht, die am Ausgang des entsprechenden Decodierers (40, 41, 42) erhalten werden.
  5. Gerät zur Wiedergabe von Videobildern auf einem Bildschirm (17) mit einem Gesamtspeicher, in dem die für jedes Teilbild wiederzugebenden Bilddaten gespeichert sind, wobei der Gesamtspeicher an einen den Bildschirm steuernden Videowiedergabeprozessor (21), eine zentrale Prozessoreinheit (10) und einen Adressenprozessor (19) angeschlossen ist, damit die Zusammensetzung des Bildes mittels des Speichers ermöglicht wird, wobei die Entnahme von sich auf wiederzugebende Punkte beziehenden Daten aus letzterem unter der Steuerung durch eine Zeitbasis (25) synchron mit dem Abtasten des Bildschirms sowie einer Vorrichtung (24) bewirkt wird, die den dynamischen Zugriff auf den Speicher steuert, wobei der Wiedergabeprozessor (21) einen Palettenspeicher (28) umfaßt, der mit dem Bildschirm (17) verbunden ist und auf letzterem wiederzugebende Farbcodes enthält, ferner eine erste Gruppe von Registern (27) vom Schiebetyp enthält, die von der Zeitbasis (25) gesteuert werden und in einer sich im Verlaufe der Wiedergabe einer Gruppe von wiederzugebenden Punkten entwickelnden Weise binäre Farbwerte enthalten, die eine Adresse für den Palettenspeicher (28) bilden, sowie eine zweite Gruppe von Registern (26) enthält, die die Farbdaten einer Gruppe von Punkten vorübergehend speichern können, die nach denen wiederzugeben sind, deren Daten sich in den Schieberegistern befinden, dadurch gekennzeichnet, daß es außerdem eine photographische Einheit (33) umfaßt, die ein Zusammenstellungsgerät nach einem der Ansprüche 1 bis 5 enthält, daß die Wiedergabe auf dem Bildschirm (11) in einem photographischen Modus gewährleisten kann, wobei die photographische Einheit (33) an den Palettenspeicher (28) angeschlossen ist und von Mitteln (29) zum Bestimmen des zu erzielenden Wiedergabemodus gesteuert wird.
  6. Gerät nach Anspruch 5, dadurch gekennzeichnet, daß an die photographische Einheit (33) auch eine Schaltung (35) zum Verarbeiten von Signalen entsprechend dem zu erzielenden Wiedergabemodus angeschlossen ist.
  7. Gerät nach Anspruch 5 oder 6, dadurch gekennzeichnet, daß die erste Gruppe von an den Palettenspeicher angeschlossenen Registern (27) eine Gruppe von Schieberegistern im Graphikmodus ist und daß eine zusätzliche Gruppe (31) von Schieberegistern im photographischen Modus vorgesehen ist, die an die zweite Gruppe von Registern (26) parallel zu der ersten Gruppe von Registern (27) angeschlossen ist, und ferner eine Schaltung (32) zum Erstellen von Quantisierungswerten der Luminanz und der Chrominanz (QY, QC) aus Werten, die in den Schieberegistern im photographischen Modus (31) enthalten sind, wobei die Schaltung (32) zum Erstellen von Quantisierungswerten an die photographische Einheit angeschlossen ist.
  8. Gerät nach Anspruch 6 oder 7, dadurch gekennzeichnet, daß die Bearbeitungsschaltung (35) einen Multiplexer (60) umfaßt, der direkt an den Farbpalettenspeicher (28) angeschlossene Eingänge im Graphikmodus (72) und Eingänge im photographischen Modus (61) aufweist, die an die entsprechenden Ausgänge der Vorrichtung zum Zusammensetzen von Farbsignalkomponenten aus Luminanz- und Chrominanzsignalen angeschlossen sind, wobei der Multiplexer von einer Logikschaltung (64) gesteuert wird, die an die Mittel (29) zum Bestimmen der Wiedergabe im Graphikmodus oder im photographischen Modus angeschlossen ist.
EP19860401766 1985-07-23 1986-08-06 Gerät zur Zusammenstellung von Farbsignalkomponenten aus Helligkeits- und Chrominanzsignalen und diese Anwendung umfassendes Video-Anzeigegerät Expired EP0257162B1 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR8511252A FR2585530B1 (fr) 1985-07-23 1985-07-23 Dispositif de composition de signaux de composantes de couleurs a partir de signaux de luminance et de chrominance et dispositif d'affichage video en comportant application
EP19860401766 EP0257162B1 (de) 1986-08-06 1986-08-06 Gerät zur Zusammenstellung von Farbsignalkomponenten aus Helligkeits- und Chrominanzsignalen und diese Anwendung umfassendes Video-Anzeigegerät
DE8686401766T DE3682067D1 (de) 1986-08-06 1986-08-06 Geraet zur zusammenstellung von farbsignalkomponenten aus helligkeits- und chrominanzsignalen und diese anwendung umfassendes video-anzeigegeraet.

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EP19860401766 EP0257162B1 (de) 1986-08-06 1986-08-06 Gerät zur Zusammenstellung von Farbsignalkomponenten aus Helligkeits- und Chrominanzsignalen und diese Anwendung umfassendes Video-Anzeigegerät

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EP0257162A1 EP0257162A1 (de) 1988-03-02
EP0257162B1 true EP0257162B1 (de) 1991-10-16

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GB1600170A (en) * 1977-04-06 1981-10-14 Texas Instruments Inc Digital control system
JPS5713484A (en) * 1980-04-11 1982-01-23 Ampex Video output processor
GB2083325B (en) * 1980-09-06 1984-03-07 Int Computers Ltd Display system

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DE3682067D1 (de) 1991-11-21
FR2585530B1 (fr) 1987-11-27
FR2585530A1 (fr) 1987-01-30

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