EP0253227B1 - Device for programming a non volatile memory of a time piece - Google Patents

Device for programming a non volatile memory of a time piece Download PDF

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Publication number
EP0253227B1
EP0253227B1 EP87109566A EP87109566A EP0253227B1 EP 0253227 B1 EP0253227 B1 EP 0253227B1 EP 87109566 A EP87109566 A EP 87109566A EP 87109566 A EP87109566 A EP 87109566A EP 0253227 B1 EP0253227 B1 EP 0253227B1
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EP
European Patent Office
Prior art keywords
frequency
timepiece
voltage
period
predetermined
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EP87109566A
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German (de)
French (fr)
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EP0253227A1 (en
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Arthur Descombes
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EM Microelectronic Marin SA
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EM Microelectronic Marin SA
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04D—APPARATUS OR TOOLS SPECIALLY DESIGNED FOR MAKING OR MAINTAINING CLOCKS OR WATCHES
    • G04D7/00—Measuring, counting, calibrating, testing or regulating apparatus
    • G04D7/002—Electrical measuring and testing apparatus
    • G04D7/003—Electrical measuring and testing apparatus for electric or electronic clocks
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G3/00—Producing timing pulses
    • G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency
    • G04G3/022—Circuits for deriving low frequency timing pulses from pulses of higher frequency the desired number of pulses per unit of time being obtained by adding to or substracting from a pulse train one or more pulses

Definitions

  • the present invention relates to a device for programming an electrically alterable non-volatile memory for timepieces, said part comprising an oscillator, a frequency divider with several stages, the rate of division of which is to be adjusted by alteration of a number k of pulses delivered by a stage of the divider, the number k being representative of the frequency difference existing between the frequency of the oscillator and a standard frequency and being in a binary form written in the memory not volatile to modify, at regular intervals, the content of certain determined stages of the divider, a stepping motor receiving driving pulses coming from the divider to display the time in analogical manner and a housing for receiving a supply battery.
  • the cited patent proposes, on the one hand, to eliminate certain operations for adjusting the frequency of the quartz and consequently to lower its cost price while improving its stability and, on the other hand, to remove any electronic system from adjustment (trimmer) at the time base.
  • the divider has auxiliary electrical inputs whose logic state determines the division ratio
  • the timepiece includes a memory, connected to these auxiliary inputs, for retaining in coded form the information determining the division ratio by acting on these auxiliary inputs.
  • the system which has just been briefly described requires a relatively complex arrangement of the integrated circuit incorporated in the watch.
  • it includes a whole timed sequence circuit for programming control which starts when the power is brought to 6.3 volts. It also requires several detectors of different voltage levels.
  • the present invention provides an internal circuit to the watch which is simpler, which lowers the cost and increases its reliability.
  • the complexity of the programming circuits is transferred above all to an accessory external to the watch, which in itself poses no problem and rids the timepiece of a large number of elements or components that are only used when of programming. To do this, the means which appear in the claims are used.
  • FIG. 1 is a schematic representation of the device used according to the invention.
  • the timepiece 1 is here a wristwatch comprising a case 2, hands 3 driven by a stepping motor not shown and a battery housing 4 normally intended to receive a power source.
  • the watch also includes an integrated electronic circuit 5 powered by contacts 6 and 6 'leading to the battery housing.
  • the connector is provided with terminals 9 and 9 'which come into contact with contacts 6 and 6' of the watch.
  • the connector is connected to a measuring and adjusting device 10 by a cable 11.
  • the device 10 is connected to the industrial network by the cord 12.
  • the frequency of the internal oscillator of the watch can be measured by means of inductive or capacitive sensors which pick up the engine advance steps or the vibrations emitted by the quartz of the timepiece.
  • Quartz is generally cut so that its frequency is higher than the standard frequency, although there are systems where the frequency of the quartz is kept lower than the standard frequency.
  • the frequency divider is then adjusted by altering its division rate represented by a number k of pulses delivered by a stage of the divider.
  • pulses will be suppressed, which leads to the well-known inhibition systems.
  • less common we will add missing pulses. All the description which follows is based on the inhibition system, but the invention could be extended to the pulse addition system by analogy.
  • the number of bits is 6 which also indicates the number of divisors by 2 which will be affected by the correction.
  • the programming device comprises first means 14 controlled by the end of a driving pulse produced by the watch motor to introduce into certain determined stages of the divider of said watch a binary state corresponding to the number k of pulses measured by the device 10, and second means 5 to block the content of said stages as soon as the binary state in question is reached, then to write said content in the non-volatile memory.
  • This programming phase can be followed by a control phase in fast mode which makes it possible to check that the memory has indeed been programmed by the desired binary value.
  • the timepiece is removed from its setting, then fitted with a battery. From this moment the watch operates normally and the inhibition is executed with the periodicity which has been chosen.
  • FIG. 2 is a detailed diagram of the electronic circuit contained inside the watch, that is circuit 5 shown diagrammatically in FIG. 1.
  • a quartz 20 driving an oscillator 21 supplying a frequency at 32,768 Hz. This frequency is divided several times.
  • the frequency at 1 Hz drives a driver circuit 31 which in turn controls the stepping motor M which thus advances by one step per second.
  • the outputs Q1 to Q6 of each of the stages 24 to 29 are connected to the corresponding recording inputs of an electrically alterable non-volatile memory at 6 bits 32. All the elements of the circuit 5 are supplied by the voltage + V / -V in from the external circuit 14 linked to the connector 8.
  • the memory 32 is well known from the state of the art. A detailed description can be found, for example, in the book “Jeck der annometrie” volume 33, 1982, pages 47 to 55 under the title: “Non-volatile EEPROM memories, application to digital adjustment of a watch to quartz”. Suffice it to recall here that this type of memory can be programmed by the data present at its inputs by raising for a certain time (approximately 250 ms) its supply voltage at the same time as it is supplied to its PRGM input a registration authorization signal. The supply voltage required for registration is here of the order of 6V. Note that the memory is provided with internal amplifiers which raise this voltage to a value greater than 25V.
  • the authorization signal is itself supplied by a voltage detector 33, the output of which is 0 if the applied voltage is below a certain threshold and 1 if this voltage is above this threshold.
  • the detector 33 can be a comparator, for example an operational circuit.
  • the threshold is fixed at 3.5V, which means that the detector supplies a signal 0 when the supply voltage is at low level (for example 1.5V) and a signal 1 when this voltage is at high level (for example 6V).
  • FIG. 2 also shows that the output signal PRGM of the detector 33 is connected via an inverter 34 to a first input of an AND gate 35, the second input of this gate receiving pulses at 8 kHz from of the divider 23.
  • the output of the AND gate 35 is connected to the input of the chain of dividers 24 to 29.
  • FIG. 3 is a detailed diagram of the electronic circuit contained in the measuring device, outside the watch, that is circuit 14 shown diagrammatically in FIG. 1.
  • This circuit is equipped with a quartz time base 60 which delivers a frequency roughly tuned to the frequency of the watch's oscillator, here 32 kHz.
  • the signal at 32 kHz is applied to a first divider by 4 referenced 61 and which supplies a signal at 8 kHz.
  • the signal at 8 kHz in turn attacks a six-stage divider or down memory or memory 62 to 67 of the same binary weight as the six-stage divider 24 to 29 contained in the watch circuit.
  • Each stage of the down-counter has an input S (set) through which a binary value supplied by a corresponding AND gate 68 to 73 can be entered.
  • the first input of each of the AND gates leads to a switch 74 to 79 whose terminals switching are connected respectively to the. + and - of a DC power supply V.
  • the position of each of the switches is representative of the number k itself representative of the frequency difference between the frequency of the watch oscillator and a frequency standard, this difference being measured by the apparatus 10 in FIG. 1 as explained above.
  • the second inputs of AND gates 68 to 73 are connected together and receive an output signal from a flip-flop D 80 whose input D is connected to the value + V.
  • the clock input CI of the flip-flop 80 receives the output signal from an OR gate 81 itself provided with three inputs 82, 83 and 84.
  • the internal circuit 5 of the watch is supplied by terminals 9 and 9 ′, ie by a first power source at 1.5V through a switch 86, or by a second power source at 6V through a switch 87. In series in this supply there is a resistance Rm.
  • the input 84 of the OR gate 81 receives it , through the inverter 85, a signal 92 representative of the current Imot in the motor coil when the latter is supplied.
  • FIG. 3 also shows that the output 90 of the down-counting divider 62 to 67 is connected both to the input R of the flip-flop 80, to the input of a monostable flip-flop 89 and to the input S of an RS 88 flip-flop.
  • the output of the monostable 89 is connected to the R input of the RS 88 flip-flop whose output 0 controls the switch 86 and whose output Q controls the switch 87.
  • the flip- flop 88 thus plays the role of a switch enabling the circuit 5 of the watch to be supplied either with a low level voltage (1.5V) or with a high level voltage (6V) via the switch 87.
  • the apparatus 10 measures the frequency difference existing between the frequency of the watch oscillator and the standard frequency. This difference is expressed by a number k which is in binary form. Let 21 be this number which is written 101010 in 6-bit binary notation. This binary value is present in circuit 14 thanks to switches 74 to 79 positioned as illustrated in FIG. 3.
  • the binary state introduced into the dividers 24 to 29 (Q1 to Q6) of the circuit 5 corresponds to the emission of the pulse 91 from the last down-counter 67 of the circuit 14. It s' So now acts to block the content of the dividers 24 to 29 which corresponds to the binary number to be introduced into the non-volatile memory 32. To do this, the pulse 91 is introduced at the input S of the RS 88 flip-flop. moment its output Ci goes to zero and its output Q goes to 1 which has the effect of supplying circuit 5 of the watch with a high level voltage (6V) by the switch 87 which is activated.
  • 6V high level voltage
  • This high-level voltage has the effect of providing a signal 1 at the output of the voltage detector 33 (PRGM) which blocks the AND gate 35 by the inverter 34.
  • PRGM voltage detector 33
  • the non-volatile memory 32 is then supplied with a high level voltage and is thus predisposed to accept the writing of the binary value present at the outputs Q1 to Q6 of the dividers 24 to 29.
  • This writing requires a certain time which can be estimated at around 250 ms.
  • the duration of this registration period Ti is determined by the monostable flip-flop 89 contained in the external circuit 14 and which is controlled by the rising edge 94 of the pulse 91.
  • the flip-flop 89 therefore starts its counting time Ti at the same time as the high level voltage is applied to the memory 32.
  • the end of the period Ti resets the flip-flop 88 which toggles which has the effect of opening the switch 87 and closing the switch 86. From this instant, circuit 5 of the watch is again supplied with the low-level voltage of 1.5V and the programming phase is completed (PRGM signal at zero).
  • the programming phase which has been described above takes as reference the current caused by the driving pulse making the motor advance by one step. For this, only the battery terminals are necessary. If we had access to the motor terminals M1 and M2, we could use the same device as shown in Figure 3. In this case the motor terminals would be connected to additional inputs 97 and 98 of circuit 14, these terminals being connected respectively to inputs 82 and 83 of the OR circuit 81, the operation of the entire device remaining exactly the same.
  • the non-volatile memory programming device which has just been described in detail constitutes the main object of the present invention.
  • the internal circuit of the watch enabling this programming is sufficient with a single additional element in addition to the conventional elements present when it comes to inhibition: the voltage level detector 33.
  • the access to the battery terminals is sufficient to program the memory and this at the cost of an internal circuit whose complexity is reduced to its simplest expression.
  • the watch When the watch's power supply battery is reinstalled in its housing, the watch works normally with the inhibition imposed on it by the binary number written in the memory and this with a periodicity which has been discussed above.
  • the manner in which inhibition is carried out is known from the state of the art and is therefore not part of the present invention. However, it is believed that it should be described here for the sake of presenting a description which is complete and complete.
  • FIG. 5 presents on the first line the alternating driving pulses M1 and M2 and emitted every second.
  • Line 2 shows an inhibition authorization signal (ENINH) triggered every 60 seconds by a driving pulse M1.
  • Line 3 is the actual inhibition signal that is created while the ENINH signal lasts.
  • the dividers 24 to 29 are supplied through the AND gate 35 which is conducting for the pulses at 8 kHz designated by 8kP and delivered by the divider 23.
  • the divider 23 also supplies pulses at 8 kHz designated by 8kPl which are always inserted between the 8kP pulses.
  • the signal of 1 s which appears at the output of the divider 30 is applied to the input of the divider by 60 referenced 52.
  • the output of this divider produces every 60 seconds a pulse designated by 60sP which is applied to the input of the AND gate 48.
  • the gate 48 allows the 60sP pulse to pass and, through the OR circuit 50, causes the flip-flop RS 51 to toggle whose output Q goes to 1.
  • the signals of lines A and B are produced by the divider 30 and are decoding signals making it possible to fix the moment when the signal ENINH must be activated by signed by 128HP, but only once every 60 seconds, the signal ENINH.
  • This signal is applied to an input of AND gate 47 and predisposes said gate to be on when all of its other inputs are at 1.
  • the upper inputs of AND gate 47 are connected to outputs Q1 to Q6 of dividers 24 to 29 and pass all at 1 just before the next 128HP pulse marked with dotted lines in FIG. 6 appears.
  • an 8kP1 intermediate pulse is emitted and the AND gate 47 is on and produces the inhibition pulse INH.
  • the non-volatile memory presents at its outputs Q1 M to Q6M the binary value which has been programmed there according to the process indicated above. This value is carried over to the first inputs of the AND circuits 40 to 45.
  • the binary value, chosen at 101010 is carried over to the inputs R1 to R6 of the dividers 24 to 29 and modifies the content of said dividers as indicated in the diagram in FIG. 6.
  • inhibition pulse INH is used to reset the RS 51 flip-flop to zero, which ends the signal ENINH.
  • the programming phase can be followed by a control phase in quick mode to check whether the memory has been programmed at the desired binary value. This constitutes a characteristic dependent on the invention.
  • the device comprise third means, implemented after the application of the first and second means previously discussed, to check that the division rate corresponds to the number k introduced into memory.
  • these third means comprise a detector sensitive to the return of the voltage to its low level at the end of the period Ti to accelerate, for a predetermined period Tf, the motor to a speed v faster than that used to display the time, and the adjustment of the division rate at a speed v / 2, which thus allows the alternation of intervals between driving pulses with and without adjustment to measure the difference in frequency existing between the frequency of l watch oscillator and standard frequency.
  • the diagram in FIG. 7 schematically explains the phase of operation in fast mode.
  • FAST fast mode signal
  • the motor receives pulses (MOT) at 32 Hz and the signal authorizing the inhibition (ENINH), as well as the inhibition signal which is linked to it ( INH), are emitted at a speed twice as slow, ie 16 Hz.
  • ENINH the inhibition signal which is linked to it
  • INH inhibition signal which is linked to it
  • the circuit inside watch 5 includes a flip-flop D 55 as well as an AND gate 56 arranged as shown in FIG. 2.
  • the signals at 32 and at 16 Hz are taken from the divider by 128 referenced 30.
  • the signal at 32 Hz is sent to the driver circuit 31 and excites the motor at this speed when the FAST signal is present.
  • the signal at 16 Hz is sent to an input of the AND gate 56, a gate which plays exactly the same role as the AND gate 48 for the signal at 60 seconds 60sP.
  • the AND gate 48 is blocked by the inverter 49.
  • the signals ENINH and INH are created at the speed of 16 Hz and at a time fixed by the signals A and B as was the case for the normal execution phase of inhibition.
  • the FAST signal begins when the supply voltage has returned to its low level, at the end of the programming period Ti.
  • the detector 33 emits a signal received by the input CI of the flip-flop 55, the output Q of which passes to the high potential of its input D.
  • the signal FAST is thus present at the output Q of the flip -flop 55 and allows the control phase in rapid mode described above.
  • This control phase will last a period Tf, for example 4 times 1/32 of a second.
  • the period Tf is ended by a reset signal RAZ of the input R of the flip-flop 55. This signal can be taken from the combination of signals present in the divider at 128 referenced 30. As soon as the signal FAST is canceled, the watch circuit operates in normal mode.
  • FIG. 8 shows that the circuit authorizing the control phase in rapid mode can be used to advantage for control purposes only during a revision of the watch for example.
  • the time constant of the monostable 89 of the external circuit 14 is considerably shortened, so that the period Ti has insufficient duration to start the programming phase.
  • the falling edge of the pulse Ti which has previously been brought to a voltage greater than that of the triggering of the voltage detector 33 of the internal circuit 5, immediately starts the control phase in fast mode (FAST).
  • the frequency difference is then measured by the QUIS device of which we have already spoken. If this difference is correct, we will stop there. If this is not the case, a new programming phase is started.
  • a period Ti composed of a rise time of 300lis reaching 4V, followed immediately by a fall time of 3OOgs also, is perfectly suited to the only rapid control process.

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Abstract

This programming arrangement for a non-volatile memory incorporated in the inner circuit of a timepiece for adjusting the frequency of the time base thereof includes a support provided with a connector to be plugged in in place of the energy cell. The rate of division of the frequency divider is adjusted by the introduction into the memory of a number k representative of the frequency difference between the time base frequency and a standard frequency. To effect this the arrangement comprises an electronic circuit external to the timepiece and which is coupled thereto by the connector. The electronic circuit introduces the number k into certain predetermined stages of the divider. When such number k is thus introduced the state of such stages is blocked by the inner circuit of the timepiece such state then being transferred into the non-volatile memory.

Description

La présente invention est relative à un dispositif de programmation d'une mémoire non volatile altérable électriquement pour pièces d'horlogerie, ladite pièce comportant un oscillateur, un diviseur de fréquence à plusieurs étages dont il s'agit d'adjuster le taux de division par altération d'un nombre k d'impulsions délivrées par un étage du diviseur, le nombre k étant représentatif de la différence de fréquence existant entre la fréquence de l'oscillateur et une fréquence étalon et se présentant sous une forme binaire inscrite dans la mémoire non volatile pour modifier, à intervalles réguliers, le contenu de certains étages déterminés du diviseur, un moteur pas à pas recevant des impulsions motrices issues du diviseur pour afficher le temps de manière analogique et un logement pour recevoir une pile d'alimentation.The present invention relates to a device for programming an electrically alterable non-volatile memory for timepieces, said part comprising an oscillator, a frequency divider with several stages, the rate of division of which is to be adjusted by alteration of a number k of pulses delivered by a stage of the divider, the number k being representative of the frequency difference existing between the frequency of the oscillator and a standard frequency and being in a binary form written in the memory not volatile to modify, at regular intervals, the content of certain determined stages of the divider, a stepping motor receiving driving pulses coming from the divider to display the time in analogical manner and a housing for receiving a supply battery.

Comme il a été dit, à propos de l'exposé d'invention CH 534 913 (US 3 895 486) l'ajustement de l'oscillateur à quartz d'un garde-temps est particulièrement compliqué. Si l'ajustement grossier se fait d'abord par usinage mécanique de précision puis par ajustement fin sur le quartz encapsulé, l'ajustement final se fait à l'aide d'un trimmer qui, d'une part, compense l'augmentation des capacités parasites et, d'autre part, permet de corriger une dérive de la base de temps lorsque le quartz a vieilli. Comme la consommation de l'oscillateur est proportionnée au carré de la valeur des capacités du circuit aùquel il est rattaché, on comprend qu'il faut réduire ces capacités autant que possible, d'où l'intérêt de supprimer le trimmer. Cette suppression présente aussi l'avantage d'améliorer la stabilité de fréquence et de se passer d'une pièce coûteuse et délicate. Le brevet cité propose, d'une part, de supprimer certaines opérations d'ajustement de la fréquence du quartz et d'abaisser par conséquent son prix de revient tout en améliorant sa stabilité et, d'autre part, de supprimer tout système électronique de réglage (trimmer) au niveau de la base de temps. Ces buts sont atteints en ce que le diviseur présente des entrées électriques auxiliaires dont l'état logique détermine le rapport de division, et en ce que le garde-temps comporte une mémoire, reliée à ces entrées auxiliaires, pour retenir sous forme codée l'information déterminant le rapport de division en agissant sur ces entrées auxilaires.As has been said, in connection with the disclosure of invention CH 534 913 (US 3,895,486) the adjustment of the quartz oscillator of a timepiece is particularly complicated. If the rough adjustment is done first by precision mechanical machining and then by fine adjustment on the encapsulated quartz, the final adjustment is done using a trimmer which, on the one hand, compensates for the increase in parasitic capacities and, on the other hand, makes it possible to correct a drift of the time base when the quartz has aged. As the consumption of the oscillator is proportional to the square of the value of the capacities of the circuit to which it is attached, we understand that these capacities must be reduced as much as possible, hence the advantage of eliminating the trimmer. This suppression also has the advantage of improving frequency stability and doing without an expensive and delicate part. The cited patent proposes, on the one hand, to eliminate certain operations for adjusting the frequency of the quartz and consequently to lower its cost price while improving its stability and, on the other hand, to remove any electronic system from adjustment (trimmer) at the time base. These aims are achieved in that the divider has auxiliary electrical inputs whose logic state determines the division ratio, and in that the timepiece includes a memory, connected to these auxiliary inputs, for retaining in coded form the information determining the division ratio by acting on these auxiliary inputs.

Le système qui vient d'être évoqué nécessite l'emploi d'un certain nombre d'interrupteurs qui fournissent un certain nombre d'ordres d'inhibition par période de réglage. La difficulté de réaliser ces interrupteurs sous forme miniaturisée présente l'inconvénient d'en limiter le nombre, ce qui restreint la plage de réglage possible. De plus, les opérations de réglage de marche sont compliquées et nécessitent l'intervention d'un horloger rhabilleur. Pour remédier à ces inconvénients, l'exposé d'invention CH 570 651 (US 3 914 706) propose l'utilisation d'une mémoire électronique altérable (à la place des interrupteurs) qui offre les avantages d'être réalisée par la même technologie que le reste des circuits et intégrée sur la même puce, de ne plus limiter le nombre de bits (plage de réglage élargie) et de pouvoir modifier l'état de la mémoire par une action purement électronique. Pour parvenir à ce but, l'exposé dernièrement cité comprend un bloc d'apprentissage qui compare la période du signal fourni à l'affichage avec une référence extérieure, qui calcule ensuite la correction à effectuer et qui transfère enfin le résultat dans la mémoire altérable.The system which has just been mentioned requires the use of a certain number of switches which supply a certain number of inhibition orders per adjustment period. The difficulty of producing these switches in miniaturized form has the disadvantage of limiting the number, which limits the possible adjustment range. In addition, the walking adjustment operations are complicated and require the intervention of a dressmaker. To remedy these drawbacks, the disclosure of invention CH 570 651 (US 3,914,706) proposes the use of an alterable electronic memory (instead of switches) which offers the advantages of being produced by the same technology than the rest of the circuits and integrated on the same chip, to no longer limit the number of bits (extended setting range) and to be able to modify the state of the memory by a purely electronic action. To achieve this goal, the presentation cited above includes a learning block which compares the period of the signal supplied to the display with an external reference, which then calculates the correction to be made and which finally transfers the result to the alterable memory .

Pour comparer la fréquence du signal étalon avec la fréquence délivrée par l'oscillateur de la pièce d'horlogerie, le second document cité prévoit une borne d'entrée pour le signal étalon ce qui complique la réalisation pratique du garde-temps. Pour remédier à cet inconvénient, il a déjà été proposé des systèmes qui ne nécessitent aucune entrée auxiliaire et qui se suffisent des seules bornes de la pile d'alimentation, normalement accessibles dans ce genre de pièce d'horlogerie, pour mener à bien tout l'ajustement du diviseur de fréquence, ainsi que le contrôle de cet ajustement si nécessaire. On comprend l'avantage d'un tel système pour une montre-bracelet complètement scellée et non démontable où ne sont accessibles que les bornes de la pile. JJn tel type de montre se trouve couramment sur le marché aujourd'hui et est réalisé généralement en matière plastique (US-A 4 147 022).To compare the frequency of the standard signal with the frequency delivered by the oscillator of the timepiece, the second cited document provides an input terminal for the standard signal which complicates the practical realization of the timepiece. To overcome this drawback, systems have already been proposed which do not require any auxiliary input and which are sufficient from the only terminals of the supply battery, normally accessible in this kind of timepiece, to carry out all the adjustment of the frequency divider, as well as control of this adjustment if necessary. We understand the advantage of such a system for a completely sealed and non-removable wristwatch where only the battery terminals are accessible. JJn such a watch is commonly found on the market today and is generally made of plastic (US-A 4,147,022).

Les actes du 59ème congrès de la Société Suisse de Chronométrie tenu les 4 et 5 octobre 1985 comprennent une communication intitulée: "A watch circuit with EEPROM for digital frequency adjustment" et présentée par Ronald Geddes. Cette communication décrit déjà un système de programmation d'une mémoire non volatile pour une pièce d'horlogerie où toute la programmation et le contrôle ont lieu par les seules bornes de la pile d'alimentation. A cet effet, il est prévu un circuit de programmation extérieur à la montre et connecté aux bornes de la pile et dans lequel est emmagasiné tout d'abord un nombre k d'impulsions représentatif de la différence de fréquence existant entre la fréquence de l'oscillateur de la montre et une fréquence étalon. On élève ensuite la tension du circuit de programmation à 6,3 volts ce qui a pour effet de mettre à zéro la chaîne des diviseurs. Le nombre k d'impulsions est alors introduit dans cette chaîne en abaissant k fois la tension d'alimentation à 5 volts. Ceci fait, on écrit le contenu de la chaîne dans la mémoire non volatile en maintenant pendant environ 200 ms la tension d'alimentation à 5 volts.The proceedings of the 59th congress of the Swiss Chronometry Society held on October 4 and 5, 1985 include a communication entitled: "A watch circuit with EEPROM for digital frequency adjustment" and presented by Ronald Geddes. This communication already describes a system for programming a non-volatile memory for a timepiece where all programming and control take place by the only terminals of the supply battery. For this purpose, a programming circuit is provided outside the watch and connected to the terminals of the battery and in which is first stored a number k of pulses representative of the frequency difference existing between the frequency of the watch oscillator and a standard frequency. The programming circuit voltage is then raised to 6.3 volts, which has the effect of zeroing the chain of the dividers. The number k of pulses is then introduced into this chain by lowering the supply voltage k to 5 volts. This done, we write the content of the chain in the non-volatile memory while maintaining for approximately 200 ms the supply voltage at 5 volts.

Le système qui vient d'être décrit sommairement nécessite un arrangement relativement complexe du circuit intégré incorporé dans la montre. Il comprend notamment tout un circuit à séquence temporisée pour la commande de la programmation qui démarre quand l'alimentation est portée à 6,3 volts. Il nécessite aussi plusieurs détecteurs de niveaux de tension différents. Pour remédier à ces inconvénients la présente invention propose un circuit interne à la montre qui est plus simple, ce qui en abaisse le coût et augmente sa fiabilité. Dans le système selon l'invention, on reporte la complexité des circuits de programmation avant tout sur un accessoire externe à la montre ce qui ne pose pas de problème en soi et débarrasse la pièce d'horlogerie d'un grand nombre d'éléments ou de composants qui ne sont utilisés que lors de la programmation. Pour ce faire, on met en oeuvre les moyens qui apparaissent dans les revendications.The system which has just been briefly described requires a relatively complex arrangement of the integrated circuit incorporated in the watch. In particular, it includes a whole timed sequence circuit for programming control which starts when the power is brought to 6.3 volts. It also requires several detectors of different voltage levels. To overcome these drawbacks, the present invention provides an internal circuit to the watch which is simpler, which lowers the cost and increases its reliability. In the system according to the invention, the complexity of the programming circuits is transferred above all to an accessory external to the watch, which in itself poses no problem and rids the timepiece of a large number of elements or components that are only used when of programming. To do this, the means which appear in the claims are used.

L'invention va être expliquée maintenant dans la description qui va suivre, donnée à titre d'exemple, en s'aidant des dessins qui s'y rapportent et dans lesquels:

  • La figure 1 est une représentation schématique du dispositif selon l'invention,
  • La figure 2 est un schéma détaillé du circuit électronique contenu dans la pièce d'horlogerie,
  • La figure 3 est un schéma détaillé du circuit extérieur à la pièce d'horlogerie et qui est utilisé notamment pour programmer la mémoire non volatile,
  • La figure 4 est un diagramme expliquant le fonctionnement de la phase de programmation de la mémoire,
  • La figure 5 est un diagramme montrant le fonctionnement normal de la pièce d'horlogerie après programmation,
  • La figure 6 est un diagramme expliquant plus en détail le fonctionnement de l'ajustement de fréquence sommairement montré en figure 5,
  • La figure 7 est un diagramme montrant le fonctionnement en phase rapide utilisée à des fins de contrôle après la phase de programmation et
  • La figure 8 est un diagramme montrant le fonctionnement en phase rapide opéré avant la phase de programmation.
The invention will now be explained in the description which follows, given by way of example, with the aid of the drawings which relate to it and in which:
  • FIG. 1 is a schematic representation of the device according to the invention,
  • FIG. 2 is a detailed diagram of the electronic circuit contained in the timepiece,
  • FIG. 3 is a detailed diagram of the circuit external to the timepiece and which is used in particular to program the non-volatile memory,
  • FIG. 4 is a diagram explaining the operation of the programming phase of the memory,
  • FIG. 5 is a diagram showing the normal operation of the timepiece after programming,
  • FIG. 6 is a diagram explaining in more detail the operation of the frequency adjustment briefly shown in FIG. 5,
  • FIG. 7 is a diagram showing the rapid phase operation used for control purposes after the programming phase and
  • FIG. 8 is a diagram showing the operation in rapid phase operated before the programming phase.

La figure 1 est une représentation schématique du dispositif mis en oeuvre selon l'invention. La pièce d'horlogerie 1 est ici une montre-bracelet comportant un boîtier 2, des aiguilles 3 entraînées par un moteur pas à pas non représenté et un logement de pile 4 destiné normalement à recevoir une source d'alimentation. La montre comporte aussi un circuit électronique intégré 5 alimenté par des contacts 6 et 6' aboutissant au logement de pile. Lorsqu'il s'agit d'ajuster le taux de division du diviseur de fréquence contenu dans le circuit 5, on place la montre sur un posage 7 pourvu lui-même d'un connecteur 8. Le connecteur est muni de bornes 9 et 9' qui entrent en contact avec les contacts 6 et 6' de la montre. Le connecteur est relié à un appareil de mesure et de réglage 10 par un câble 11. L'appareil 10 est branché au réseau industriel par le cordon 12.Figure 1 is a schematic representation of the device used according to the invention. The timepiece 1 is here a wristwatch comprising a case 2, hands 3 driven by a stepping motor not shown and a battery housing 4 normally intended to receive a power source. The watch also includes an integrated electronic circuit 5 powered by contacts 6 and 6 'leading to the battery housing. When it is a question of adjusting the rate of division of the frequency divider contained in the circuit 5, one places the watch on a setting 7 provided itself with a connector 8. The connector is provided with terminals 9 and 9 'which come into contact with contacts 6 and 6' of the watch. The connector is connected to a measuring and adjusting device 10 by a cable 11. The device 10 is connected to the industrial network by the cord 12.

Pour procéder au réglage du diviseur de fréquence, il s'agit de mesurer tout d'abord la différence de fréquence existant entre la fréquence de l'oscillateur monté dans la montre et la fréquence dispensée par un oscillateur étalon réputé exact et stable. La fréquence de l'oscillateur interne à la montre peut être mesurée au moyen de capteurs inductifs ou capacitifs qui captent les pas d'avance du moteur ou les vibrations émises par le quartz de la pièce d'horlogerie.To adjust the frequency divider, you first need to measure the frequency difference between the frequency of the oscillator mounted in the watch and the frequency supplied by a standard oscillator known to be exact and stable. The frequency of the internal oscillator of the watch can be measured by means of inductive or capacitive sensors which pick up the engine advance steps or the vibrations emitted by the quartz of the timepiece.

On taille généralement le quartz de façon à ce que sa fréquence soit plus élevée que la fréquence étalon, bien qu'il existe des systèmes où la fréquence du quartz est maintenue plus basse que la fréquence étalon. On ajuste alors le diviseur de fréquence par altération de son taux de division représenté par un nombre k d'impulsions délivré par un étage du diviseur. Dans le premier cas on supprimera des impulsions ce qui conduit aux systèmes bien connus dit d'inhibition. Dans le second cas, moins courant, on ajoutera des impulsions manquantes. Toute la description qui va suivre est basée sur le système d'inhibition, mais l'invention pourrait être étendue au système d'addition d'impulsions par analogie.Quartz is generally cut so that its frequency is higher than the standard frequency, although there are systems where the frequency of the quartz is kept lower than the standard frequency. The frequency divider is then adjusted by altering its division rate represented by a number k of pulses delivered by a stage of the divider. In the first case, pulses will be suppressed, which leads to the well-known inhibition systems. In the second case, less common, we will add missing pulses. All the description which follows is based on the inhibition system, but the invention could be extended to the pulse addition system by analogy.

Des appareils en vente dans le commerce permettent la mesure de la différence de fréquence. On peut citer par exemple l'appareil commercialisé par la Société ETA SA à Granges (Suisse) et vendu sous le nom de QUIS. Ces appareils sont capables de mesurer l'écart de fréquence existant en ppm (parties par million = 10-6) entre la fréquence étalon et la fréquence réelle du quartz. Si cet écart de fréquence est de x ppm, on peut calculer le nombre k d'impulsions à supprimer par périodes de t secondes à une fréquence f délivrée par un étage du diviseur de fréquence. Ce nombre k vaut:

  • k (impulsions) = f (Hz) - t (s) . x . 10-6
Commercially available devices allow measurement of the frequency difference. One can quote for example the apparatus marketed by the Company ETA SA in Granges (Switzerland) and sold under the name of QUIS. These devices are capable of measuring the frequency difference existing in ppm (parts per million = 10- 6) between the standard frequency and the actual frequency of the quartz. If this frequency difference is x ppm, the number k of pulses to be suppressed can be calculated by periods of t seconds at a frequency f delivered by a stage of the frequency divider. This number k is:
  • k (pulses) = f (Hz) - t (s). x. 10-6

Par exemple, si l'appareil de mesure indique un écart de 128 ppm et que l'inhibition est réalisée à la sortie d'un diviseur délivrant la fréquence de 8192 Hz et ceci toutes les 60 secondes, le nombre k vaudra: 8192 ' 60 • 128 - 10-6 = 63. Comme ce nombre k se présente généralement sous forme binaire, on peut calculer le nombre de bits nécessaires, soit:

  • nombre de bits = log2 k.
For example, if the measuring device indicates a difference of 128 ppm and that the inhibition is performed at the output of a divider delivering the frequency of 8192 Hz and this every 60 seconds, the number k worth 8192 '60 • 128 - 10-6 = 63. As this number k is generally presented in binary form, one can calculate the number of bits necessary, that is to say:
  • number of bits = log 2 k.

Pour un k valant 63, le nombre de bits est de 6 ce qui indique aussi le nombre de diviseurs par 2 qui seront touchés par la correction.For a k equal to 63, the number of bits is 6 which also indicates the number of divisors by 2 which will be affected by the correction.

Il est intéressant aussi de calculer la résolution que peut atteindre le système, c'est-à-dire le plus petit écart de fréquence discernable en ppm, ce qui est réalisé quand k = 1. On a:

Figure imgb0001

  • Si l'on reprend les valeurs citées ci-dessus en exemple on trouve
    Figure imgb0002
Avec une telle résolution et compte tenu du fait qu'il y a 86'400 secondes en un jour, on peut atteindre une précision de 86'400 . 2,03 ' 10-6 = 0,17 secondes par jour ou d'environ 5 secondes par mois. Le tableau ci-dessous donne plusieurs combinaisons pratiques possibles:
Figure imgb0003
 It is also interesting to calculate the resolution that the system can reach, that is to say the smallest discernible frequency difference in ppm, which is achieved when k = 1. We have:
Figure imgb0001
  • If we take the values quoted above as an example we find
    Figure imgb0002
With such a resolution and taking into account that there are 86,400 seconds in a day, an accuracy of 86,400 can be achieved. 2.03 '10 -6 = 0.17 seconds per day or approximately 5 seconds per month. The table below gives several possible practical combinations:
Figure imgb0003

Si l'on revient maintenant à la figure 1, on admet que l'appareil 10 est équipé pour mesurer l'écart de fréquence en ppm ou en k impulsions correspondantes et qu'il retient cette valeur (dans la figure et en exemple k = 21, référence 13). Il s'agit donc maintenant de programmer la mémoire non volatile de la montre, mémoire contenue dans le circuit 5, par la valeur retenue dans l'appareil 10. A cet effet et selon l'invention, le dispositif de programmation comporte des premiers moyens 14 commandés par la fin d'une impulsion motrice produite par le moteur de la montre pour introduire dans certains étages déterminés du diviseur de ladite montre un état binaire correspondant au nombre k d'impulsions mesuré par l'appareil 10, et des seconds moyens 5 pour bloquer le contenu desdits étages dès que l'état binaire en question est atteint, puis pour inscrire ledit contenu dans la mémoire non volatile. Cette phase de programmation peut être suivie par une phase de contrôle en mode rapide qui permet de contrôler que la mémoire a bien été programmée par la valeur binaire voulue. Enfin la pièce d'horlogerie est enlevée de son posage, puis équipée d'une pile. Dès cet instant la montre marche normalement et l'inhibition est exécutée avec la périodicité qui a été choisie.Returning now to FIG. 1, it is assumed that the apparatus 10 is equipped for measuring the frequency difference in ppm or in k corresponding pulses and that it retains this value (in the figure and in example k = 21, reference 13). It is therefore now a matter of programming the non-volatile memory of the watch, memory contained in circuit 5, by the value retained in the device 10. For this purpose and according to the invention, the programming device comprises first means 14 controlled by the end of a driving pulse produced by the watch motor to introduce into certain determined stages of the divider of said watch a binary state corresponding to the number k of pulses measured by the device 10, and second means 5 to block the content of said stages as soon as the binary state in question is reached, then to write said content in the non-volatile memory. This programming phase can be followed by a control phase in fast mode which makes it possible to check that the memory has indeed been programmed by the desired binary value. Finally the timepiece is removed from its setting, then fitted with a battery. From this moment the watch operates normally and the inhibition is executed with the periodicity which has been chosen.

Les trois phases qui viennent d'être mentionnées vont être expliquées maintenant dans le détail en s'aidant des figures qui accompagnent cette description.The three phases which have just been mentioned will now be explained in detail with the aid of the figures which accompany this description.

1. Phase de programmation1. Programming phase

La figure 2 est un schéma détaillé du circuit électronique contenu à l'intérieur de la montre, soit le circuit 5 schématisé en figure 1. On y trouve un quartz 20 pilotant un oscillateur 21 fournissant une fréquence à 32'768 Hz. Cette fréquence est divisée plusieurs fois. Une première fois par les deux étages 22 et 23 à la sortie desquels on trouve un signal à 8192 Hz et référencé 8kP, une deuxième fois par les six étages 24 à 29 qui délivrent un signal à 128 Hz et une troisième fois par un étage 30 comportant 7 diviseurs par 2 pour aboutir à une fréquence de 1 Hz. La fréquence à 1 Hz pilote un circuit driver 31 qui commande à son tour le moteur pas à pas M qui progresse ainsi d'un pas par seconde. Les sorties Q1 à Q6 de chacun des étages 24 à 29 sont connectées aux entrées d'inscription correspondantes d'une mémoire non volatile altérable électriquement à 6 bits 32. Tous les éléments du circuit 5 sont alimentés par la tension +V/-V en provenance du circuit extérieur 14 lié au connecteur 8.FIG. 2 is a detailed diagram of the electronic circuit contained inside the watch, that is circuit 5 shown diagrammatically in FIG. 1. There there is a quartz 20 driving an oscillator 21 supplying a frequency at 32,768 Hz. This frequency is divided several times. A first time by the two stages 22 and 23 at the output of which there is a signal at 8192 Hz and referenced 8kP, a second time by the six stages 24 to 29 which deliver a signal at 128 Hz and a third time by a stage 30 comprising 7 dividers by 2 to result in a frequency of 1 Hz. The frequency at 1 Hz drives a driver circuit 31 which in turn controls the stepping motor M which thus advances by one step per second. The outputs Q1 to Q6 of each of the stages 24 to 29 are connected to the corresponding recording inputs of an electrically alterable non-volatile memory at 6 bits 32. All the elements of the circuit 5 are supplied by the voltage + V / -V in from the external circuit 14 linked to the connector 8.

La mémoire 32 est bien connue de l'état de la technique. On en trouvera une description détaillée par exemple dans l'ouvrage intitulé "Jahrbuch der deutschen Gesellschaft für Chronometrie" volume 33, 1982, pages 47 à 55 sous le titre: "Mémoires non volatiles EEPROM autonomes, application au réglage digital d'une montre à quartz". Qu'il suffise de rappeler ici que ce type de mémoire peut être programmée par les données présentes à ses entrées en élevant pendant un certain temps (environ 250 ms) sa tension d'alimentation en même temps que lui est fourni à son entrée PRGM un signal d'autorisation d'inscription. La tension d'alimentation nécessaire à l'inscription est ici de l'ordre de 6V. A noter que la mémoire est pourvue d'amplificateurs internes qui élèvent cette tension à une valeur supérieure à 25V.The memory 32 is well known from the state of the art. A detailed description can be found, for example, in the book "Jahrbuch der deutschen Gesellschaft für Chronometrie" volume 33, 1982, pages 47 to 55 under the title: "Non-volatile EEPROM memories, application to digital adjustment of a watch to quartz". Suffice it to recall here that this type of memory can be programmed by the data present at its inputs by raising for a certain time (approximately 250 ms) its supply voltage at the same time as it is supplied to its PRGM input a registration authorization signal. The supply voltage required for registration is here of the order of 6V. Note that the memory is provided with internal amplifiers which raise this voltage to a value greater than 25V.

Le signal d'autorisation est lui-même fourni par un détecteur de tension 33 dont la sortie vaut 0 si la tension appliquée est inférieure à un certain seuil et vaut 1 si cette tension est supérieure à ce seuil. Le détecteur 33 peut être un comparateur, par exemple un circuit opérationnel. Dans l'arrangement décrit ici le seuil est fixé à 3,5V, ce qui fait que le détecteur fournit un signal 0 quand la tension d'alimentation est à bas niveau (par exemple 1,5V) et un signal 1 quand cette tension est à haut niveau (par exemple 6V).The authorization signal is itself supplied by a voltage detector 33, the output of which is 0 if the applied voltage is below a certain threshold and 1 if this voltage is above this threshold. The detector 33 can be a comparator, for example an operational circuit. In the arrangement described here, the threshold is fixed at 3.5V, which means that the detector supplies a signal 0 when the supply voltage is at low level (for example 1.5V) and a signal 1 when this voltage is at high level (for example 6V).

La figure 2 montre également que le signal de sortie PRGM du détecteur 33 est relié par l'intermédiaire d'un inverseur 34 à une première entrée d'une porte ET 35, la deuxième entrée de cette porte recevant des impulsions à 8 kHz en provenance du diviseur 23. La sortie de la porte ET 35 est reliée à l'entrée de la chaîne de diviseurs 24 à 29. Ainsi, dans cet arrangement, quand le signal PRGM est présent, la porte ET 35 est bloquée (signal 0 dû à l'inverseur 34) et les impulsions à 8 kHz ne parviennent plus à l'entrée de la chaîne 24 à 29 qui est ainsi bloquée à l'état binaire qu'elle avait au moment de l'arrivée du signal PRGM.FIG. 2 also shows that the output signal PRGM of the detector 33 is connected via an inverter 34 to a first input of an AND gate 35, the second input of this gate receiving pulses at 8 kHz from of the divider 23. The output of the AND gate 35 is connected to the input of the chain of dividers 24 to 29. Thus, in this arrangement, when the PRGM signal is present, the AND gate 35 is blocked (signal 0 due to the inverter 34) and the pulses at 8 kHz no longer reach the input of the chain 24 to 29 which is thus blocked in the binary state it had at the time of the arrival of the PRGM signal.

La figure 3 est un schéma détaillé du circuit électronique contenu dans l'appareil de mesure, à l'extérieur de la montre, soit le circuit 14 schématisé en figure 1. Ce circuit est équipé d'une base de temps à quartz 60 qui délivre une fréquence accordée grossièrement à la fréquence de l'oscillateur de la montre, ici 32 kHz. Le signal à 32 kHz est appliqué à un premier diviseur par 4 référencé 61 et qui fournit un signal à 8 kHz. Le signal à 8 kHz attaque à son tour un diviseur-décompteur ou mémoire à six étages 62 à 67 de même poids binaire que le diviseur à six étages 24 à 29 contenu dans le circuit de la montre. Chaque étage du diviseur-décompteur possède une entrée S (set) par laquelle peut être introduite une valeur binaire fournie par une porte ET correspondante 68 à 73. La première entrée de chacune des portes ET aboutit à un commutateur 74 à 79 dont les bornes de commutation sont reliées respectivement au.+ et au - d'une alimentation continue V. La position de chacun des commutateurs est représentative du nombre k représentatif lui-même de la différence de fréquence entre la fréquence de l'oscillateur de la montre et une fréquence étalon, cette différence étant mesurée par l'appareil 10 de la figure 1 comme cela a été expliqué plus haut. Les secondes entrées des portes ET 68 à 73 sont connectées ensemble et reçoivent un signal de sortieo d'un flip-flop D 80 dont l'entrée D est connectée à la valeur + V. L'entrée d'horloge CI du flip-flop 80 reçoit le signal de sortie d'une porte OU 81 elle-même munie de trois entrées 82, 83 et 84. Le circuit interne 5 de la montre est alimenté par les bornes 9 et 9', soit par une première source d'alimentation à 1,5V à travers un interrupteur 86, soit par une seconde source d'alimentation à 6V à travers un interrupteur 87. En série dans cette alimentation on trouve une résistance Rm. Ainsi l'entrée 84 de la porte OU 81 reçoit-elle, à travers l'inverseurtrigger 85, un signal 92 représentatif du courant Imot dans la bobine du moteur quand celle-ci est alimentée.FIG. 3 is a detailed diagram of the electronic circuit contained in the measuring device, outside the watch, that is circuit 14 shown diagrammatically in FIG. 1. This circuit is equipped with a quartz time base 60 which delivers a frequency roughly tuned to the frequency of the watch's oscillator, here 32 kHz. The signal at 32 kHz is applied to a first divider by 4 referenced 61 and which supplies a signal at 8 kHz. The signal at 8 kHz in turn attacks a six-stage divider or down memory or memory 62 to 67 of the same binary weight as the six-stage divider 24 to 29 contained in the watch circuit. Each stage of the down-counter has an input S (set) through which a binary value supplied by a corresponding AND gate 68 to 73 can be entered. The first input of each of the AND gates leads to a switch 74 to 79 whose terminals switching are connected respectively to the. + and - of a DC power supply V. The position of each of the switches is representative of the number k itself representative of the frequency difference between the frequency of the watch oscillator and a frequency standard, this difference being measured by the apparatus 10 in FIG. 1 as explained above. The second inputs of AND gates 68 to 73 are connected together and receive an output signal from a flip-flop D 80 whose input D is connected to the value + V. The clock input CI of the flip-flop 80 receives the output signal from an OR gate 81 itself provided with three inputs 82, 83 and 84. The internal circuit 5 of the watch is supplied by terminals 9 and 9 ′, ie by a first power source at 1.5V through a switch 86, or by a second power source at 6V through a switch 87. In series in this supply there is a resistance Rm. Thus the input 84 of the OR gate 81 receives it , through the inverter 85, a signal 92 representative of the current Imot in the motor coil when the latter is supplied.

La figure 3 montre encore que la sortie 90 du diviseur-décompteur 62 à 67 est reliée à la fois à l'entrée R du flip-flop 80, à l'entrée d'un flip-flop monostable 89 et à l'entrée S d'un flip-flop RS 88. La sortie du monostable 89 est reliée à l'entrée R du flip-flop RS 88 dont la sortie 0 commande l'interrupteur 86 et dont la sortie Q commande l'interrupteur 87. Le flip-flop 88 joue ainsi le rôle d'un commutateur permettant d'alimenter le circuit 5 de la montre soit par une tension à bas niveau (1,5V), soit par une tension à haut niveau (6V) par l'intermédiaire de l'interrupteur 87.FIG. 3 also shows that the output 90 of the down-counting divider 62 to 67 is connected both to the input R of the flip-flop 80, to the input of a monostable flip-flop 89 and to the input S of an RS 88 flip-flop. The output of the monostable 89 is connected to the R input of the RS 88 flip-flop whose output 0 controls the switch 86 and whose output Q controls the switch 87. The flip- flop 88 thus plays the role of a switch enabling the circuit 5 of the watch to be supplied either with a low level voltage (1.5V) or with a high level voltage (6V) via the switch 87.

A l'aide des circuits des figures 2 et 3 qui viennent d'être décrits et du diagramme présenté en figure 4, on va expliquer maintenant comment est réalisée la phase de programmation de la mémoire non volatile.Using the circuits of FIGS. 2 and 3 which have just been described and the diagram presented in FIG. 4, we will now explain how the programming phase of the non-volatile memory is carried out.

Comme on l'a déjà dit, l'appareil 10 mesure l'écart de fréquence existant entre la fréquence de l'oscillateur de la montre et la fréquence étalon. Cet écart est exprimé par un nombre k qui se présente sous forme binaire. Soit 21 ce nombre qui s'écrit 101010 en notation binaire à 6 bits. Cette valeur binaire est présente dans le circuit 14 grâce aux d'interrupteurs 74 à 79 positionnés comme illustré en figure 3.As already mentioned, the apparatus 10 measures the frequency difference existing between the frequency of the watch oscillator and the standard frequency. This difference is expressed by a number k which is in binary form. Let 21 be this number which is written 101010 in 6-bit binary notation. This binary value is present in circuit 14 thanks to switches 74 to 79 positioned as illustrated in FIG. 3.

Lorsqu'on enfiche la montre 1 sur son posage 7 (figure 1) le circuit 5 de la montre est alimenté par une tension externe de 1,5V en supposant que l'interrupteur 86 du circuit 14 soit fermé. Dès cet instant l'oscillateur 21 démarre ainsi que la chaîne de diviseurs 22 à 30 qui lui est liée. Une impulsion motrice M1 apparaît à la sortie du driver 31 (figure 4). A cette impulsion motrice correspond naturellement un courant Imot circulant dans la bobine du moteur M. Ce courant présente une fin abrupte qui correspond à la fin de l'impulsion M1. Par définition la fin de l'impulsion motrice correspond à la remise à zéro de tous les diviseurs 24 à 29 ce qui est illustré en figure 4 au temps t = 0 pour tous les diviseurs dont les états sont présentés de 01 à Q6. Parallèlement à cela l'impulsion motrice 92, déjà inversée et remise en forme par le trigger 85 de la figure 3, passe la porte OU 81. Son flanc d'entrée fait passer à 1 la sortieO du flip-flop 80. De cette façon le nombre binaire 21 = 101010 présent aux entrées des portes ET 68 à 73 passe lesdites portes et est inscrit dans les décompteurs 62 à 67 par leurs entrées S respectives. Puis le flanc de sortie 93 de l'impulsion 92 fait passer à zéro la sortie 0 du flip-flop 80. Dès cet instant, qui correspond au début d'une période TD, les impulsions à 8 kHz issues du diviseur 61 modifient le contenu des décompteurs jusqu'à ce que ceux-ci atteignent la valeur binaire présente à leurs entrées S. Quand cette valeur est atteinte, le dernier décompteur 67 émet une impulsion de report 91 à sa sortie 90, impulsion qui apparaît à la fin de la période TD.When the watch 1 is plugged into its setting 7 (FIG. 1) the circuit 5 of the watch is supplied by an external voltage of 1.5V assuming that the switch 86 of the circuit 14 is closed. From this moment the oscillator 21 starts as well as the chain of dividers 22 to 30 which is linked to it. A driving pulse M1 appears at the output of the driver 31 (FIG. 4). This driving pulse naturally corresponds to a current Imot flowing in the coil of the motor M. This current has an abrupt end which corresponds to the end of the pulse M1. By definition, the end of the driving pulse corresponds to the resetting to zero of all the dividers 24 to 29 which is illustrated in FIG. 4 at time t = 0 for all the dividers whose states are presented from 01 to Q6. At the same time as this the driving impulse 92, already inverted and reshaped by the trigger 85 of FIG. 3, passes the OR gate 81. Its input flank causes the output O of the flip-flop 80 to go to 1. In this way the binary number 21 = 101 010 present at the inputs of the AND gates 68 to 73 passes through the said gates and is entered in the downcounters 62 to 67 by their respective S inputs. Then the output flank 93 of the pulse 92 causes the output 0 of the flip-flop 80 to go to zero. From this instant, which corresponds to the start of a TD period, the 8 kHz pulses from the divider 61 modify the content down counters until they reach the binary value present at their inputs S. When this value is reached, the last down counter 67 sends a carry-over pulse 91 to its output 90, pulse which appears at the end of the period TD.

Si l'on revient maintenant aux figures 2 et 4, on comprend que les diviseurs 24 à 29, à partir du temps t = 0 qui correspond au début de la période TD définie ci-dessus, sont alimentés avec des impulsions à 8 kHz en provenance du diviseur 23, car la porte ET 35 est passante, le signal PRGM étant à zéro. L'état des diviseurs 24 à 29 va donc se modifier jusqu'à ce que leurs sorties 01 à Q6 portent la valeur binaire 101010 introduite dans le décompteur à 6 bits du circuit 14 de la figure 3. Ainsi on constate que les deux circuits 5 et 14 fonctionnent indépendamment l'un de l'autre, mais parallèlement et en synchronisme puisque les fréquences propres de leurs oscillateurs respectifs 21 et 60 ont à peu près la même fréquence, le début du processus ayant lieu pour les deux circuits au même temps t = 0 qui est celui de la fin de l'impulsion motrice.Returning now to FIGS. 2 and 4, it will be understood that the dividers 24 to 29, from the time t = 0 which corresponds to the start of the period TD defined above, are supplied with pulses at 8 kHz in coming from the divider 23, because the AND gate 35 is on, the PRGM signal being at zero. The state of the dividers 24 to 29 will therefore change until their outputs 01 to Q6 carry the binary value 101010 introduced into the 6-bit down-counter of the circuit 14 of FIG. 3. Thus we see that the two circuits 5 and 14 operate independently of each other, but in parallel and in synchronism since the natural frequencies of their respective oscillators 21 and 60 have approximately the same frequency, the beginning of the process taking place for the two circuits at the same time t = 0 which is that of the end of the driving pulse.

Ainsi à la fin de la période TD, l'état binaire introduit dans les diviseurs 24 à 29 (Q1 à Q6) du circuit 5 correspond à l'émission de l'impulsion 91 issue du dernier décompteur 67 du circuit 14. Il s'agit donc maintenant de bloquer le contenu des diviseurs 24 à 29 qui correspond au nombre binaire à introduire dans la mémoire non volatile 32. Pour ce faire, l'impulsion 91 est introduite à l'entrée S du flip-flop RS 88. A ce moment sa sortie Ci passe à zéro et sa sortie Q passe à 1 ce qui a pour effet d'alimenter le circuit 5 de la montre par une tension à haut niveau (6V) par l'interrupteur 87 qui est activé. Cette tension à haut niveau a pour effet de fournir un signal 1 à la sortie du détecteur de tension 33 (PRGM) ce qui bloque la porte ET 35 par l'inverseur 34. Les impulsions à 8kHz ne parviennent plus aux diviseurs 24 à 29 dont l'état est maintenue à la valeur binaire à introduire dans la mémoire.Thus at the end of the period TD, the binary state introduced into the dividers 24 to 29 (Q1 to Q6) of the circuit 5 corresponds to the emission of the pulse 91 from the last down-counter 67 of the circuit 14. It s' So now acts to block the content of the dividers 24 to 29 which corresponds to the binary number to be introduced into the non-volatile memory 32. To do this, the pulse 91 is introduced at the input S of the RS 88 flip-flop. moment its output Ci goes to zero and its output Q goes to 1 which has the effect of supplying circuit 5 of the watch with a high level voltage (6V) by the switch 87 which is activated. This high-level voltage has the effect of providing a signal 1 at the output of the voltage detector 33 (PRGM) which blocks the AND gate 35 by the inverter 34. The pulses at 8 kHz no longer reach the dividers 24 to 29 of which the state is maintained at the binary value to be introduced into the memory.

La mémoire non volatile 32 est alors alimentée par une tension à haut niveau et est ainsi prédisposée à accepter l'inscription de la valeur binaire présente aux sorties Q1 à Q6 des diviseurs 24 à 29. On a dit plus haut que cette inscription demande un certain temps qui peut être estimé à environ 250 ms. La durée de cette période d'inscription Ti est déterminée par le flip-flop monostable 89 contenu dans le circuit extérieur 14 et qui est commandé par le flanc montant 94 de l'impulsion 91. Le flip-flop 89 démarre donc son temps de comptage Ti en même temps que la tension à haut niveau est appliquée à la mémoire 32. La fin de la période Ti remet à zéro le flip-flop 88 qui bascule ce qui a pour effet d'ouvrir l'interrupteur 87 et de fermer l'interrupteur 86. Dès cet instant le circuit 5 de la montre est à nouveau alimenté par la tension à bas niveau de 1,5V et la phase de programmation est terminée (signal PRGM à zéro).The non-volatile memory 32 is then supplied with a high level voltage and is thus predisposed to accept the writing of the binary value present at the outputs Q1 to Q6 of the dividers 24 to 29. We said above that this writing requires a certain time which can be estimated at around 250 ms. The duration of this registration period Ti is determined by the monostable flip-flop 89 contained in the external circuit 14 and which is controlled by the rising edge 94 of the pulse 91. The flip-flop 89 therefore starts its counting time Ti at the same time as the high level voltage is applied to the memory 32. The end of the period Ti resets the flip-flop 88 which toggles which has the effect of opening the switch 87 and closing the switch 86. From this instant, circuit 5 of the watch is again supplied with the low-level voltage of 1.5V and the programming phase is completed (PRGM signal at zero).

La phase de programmation qui a été décrite ci-dessus prend pour référence le courant provoqué par l'impulsion motrice faisant progresser le moteur d'un pas. Pour cela seules les bornes de la pile sont nécessaires. Si l'on avait accès aux bornes M1 et M2 du moteur, on pourrait mettre en oeuvre le même dispositif comme le montre la figure 3. Dans ce cas les bornes du moteur seraient connectées à des entrées supplémentaires 97 et 98 du circuit 14, ces bornes étant reliées respectivement aux entrées 82 et 83 du circuit OU 81, le fonctionnement de tout le dispositif restant exactement le même.The programming phase which has been described above takes as reference the current caused by the driving pulse making the motor advance by one step. For this, only the battery terminals are necessary. If we had access to the motor terminals M1 and M2, we could use the same device as shown in Figure 3. In this case the motor terminals would be connected to additional inputs 97 and 98 of circuit 14, these terminals being connected respectively to inputs 82 and 83 of the OR circuit 81, the operation of the entire device remaining exactly the same.

Le dispositif de programmation de la mémoire non volatile qui vient d'être décrit en détail constitue l'objet principal de la présente invention. On a vu que le circuit interne de la montre permettant cette programmation se suffit d'un seul élément supplémentaire en plus des éléments classiques présents losqu'il s'agit de faire de l'inhibition: le détecteur de niveau de tension 33. Ici l'accès aux seules bornes de la pile suffisent pour programmer la mémoire et cela au prix d'un circuit interne dont la complexité est réduite à sa plus simple expression.The non-volatile memory programming device which has just been described in detail constitutes the main object of the present invention. We have seen that the internal circuit of the watch enabling this programming is sufficient with a single additional element in addition to the conventional elements present when it comes to inhibition: the voltage level detector 33. Here the access to the battery terminals is sufficient to program the memory and this at the cost of an internal circuit whose complexity is reduced to its simplest expression.

2. Phase d'exécution de l'inhibition2. Phase of inhibition execution

Quand on réinstalle la pile d'alimentation de la montre dans son logement, la montre marche normalement avec l'inhibition qui lui est imposée par le nombre binaire inscrit dans la mémoire et ceci avec une périodicité qui a été discutée plus haut. La manière dont l'inhibition est exécutée est connue de l'état de la technique et ne fait donc pas partie de la présente invention. On pense cependant qu'il y a lieu de la décrire ici par souci de présenter une description qui soit entière et complète.When the watch's power supply battery is reinstalled in its housing, the watch works normally with the inhibition imposed on it by the binary number written in the memory and this with a periodicity which has been discussed above. The manner in which inhibition is carried out is known from the state of the art and is therefore not part of the present invention. However, it is believed that it should be described here for the sake of presenting a description which is complete and complete.

Si l'on se reporte à nouveau à la figure 2, on peut énumérer les éléments contenus dans le circuit de la montre qui sont nécessaires à l'exécution périodique de l'inhibition. Ce sont: les portes ET à deux entrées 40 à 45, la porte ET 47 à huit entrées, la porte ET à quatre entrées 48, l'inverseur 49, le circuit OU 50, le flip-flop RS 51 et le diviseur par 60 référencé 52. Tous ces éléments sont combinés entre eux et aux éléments déjà décrits comme l'indique le schéma de la figure 2.If we refer again to FIG. 2, we can list the elements contained in the watch circuit which are necessary for the periodic execution of the inhibition. These are: AND gates with two inputs 40 to 45, AND gate 47 with eight inputs, AND gate with four inputs 48, inverter 49, OR circuit 50, flip-flop RS 51 and divider by 60 referenced 52. All of these elements are combined with one another and with the elements already described as indicated in the diagram in FIG. 2.

Pour fixer les idées on prendra ici une périodicité de 60 secondes, un nombre de bits égal à 6 et une correction réalisée à partir de 8192 Hz, ce qui correspond à la combinaison donnée à la première ligne du tableau présenté plus haut. On supposera également que le nombre binaire inscrit dans la mémoire est de 101010 (k = 21).To fix the ideas, we will take here a periodicity of 60 seconds, a number of bits equal to 6 and a correction made from 8192 Hz, which corresponds to the combination given in the first line of the table presented above. We will also assume that the binary number written in the memory is 101010 (k = 21).

Le diagramme de la figure 5 présente sur la première ligne les impulsions motrices alternées M1 et M2 et émises toutes les secondes. La ligne 2 montre un signal d'autorisation de l'inhibition (ENINH) déclenché toutes les 60 secondes par une impulsion motrice M1. La ligne 3 est le signal d'inhibition proprement dit qui est créé pendant que dure le signal ENINH. On se reportera maintenant au schéma de la figure 2 et au diagramme de la figure 6, diagramme qui est un agrandissement dans le temps de ce qui se passe pendant et après l'application du signal ENINH de la figure 5.The diagram of FIG. 5 presents on the first line the alternating driving pulses M1 and M2 and emitted every second. Line 2 shows an inhibition authorization signal (ENINH) triggered every 60 seconds by a driving pulse M1. Line 3 is the actual inhibition signal that is created while the ENINH signal lasts. We will now refer to the diagram in FIG. 2 and to the diagram in FIG. 6, a diagram which is an enlargement in time of what happens during and after the application of the signal ENINH of FIG. 5.

Les diviseurs 24 à 29 sont alimentés à travers la porte ET 35 qui est passante pour les impulsions à 8 kHz désignées par 8kP et délivrées par le diviseur 23. Pour les besoins qui apparaîtront plus loin, le diviseur 23 fournit également des impulsions à 8 kHz désignées par 8kPl qui sont toujours intercalées entre les impulsions 8kP. Le signal de 1 s qui apparaît à la sortie du diviseur 30 est appliqué à l'entrée du diviseur par 60 référencé 52. La sortie de ce diviseur produit toutes les 60 secondes une impulsion désignée par 60sP qui est appliquée à l'entrée de la porte ET 48. Si la sortie de l'inverseur 49 est à 1 de même que les lignes A et B, la porte 48 laisse passer l'impulsion 60sP et, à travers le circuit OU 50, fait basculer le flip-flop RS 51 dont la sortie Q passe à 1. Les signaux des lignes A et B sont produits par le diviseur 30 et sont des signaux de décodage permettant de fixer l'instant où le signal ENINH doit être activé par signé par 128HP, mais seulement une fois toutes les 60 secondes, le signal ENINH. Ce signal est appliqué à une entrée de la porte ET 47 et prédispose ladite porte à être passante quand toutes ses autres entrées seront à 1. Les entrées supérieures de la porte ET 47 sont connectées aux sorties Q1 à Q6 des diviseurs 24 à 29 et passent toutes à 1 juste avant que n'apparaisse la prochaine impulsion 128HP marquée en pointillés sur la figure 6. Au même instant est émise une impulsion intercalaire 8kPl et la porte ET 47 est passante et produit l'impulsion d'inhibition INH.The dividers 24 to 29 are supplied through the AND gate 35 which is conducting for the pulses at 8 kHz designated by 8kP and delivered by the divider 23. For the needs which will appear later, the divider 23 also supplies pulses at 8 kHz designated by 8kPl which are always inserted between the 8kP pulses. The signal of 1 s which appears at the output of the divider 30 is applied to the input of the divider by 60 referenced 52. The output of this divider produces every 60 seconds a pulse designated by 60sP which is applied to the input of the AND gate 48. If the output of the inverter 49 is at 1 as well as the lines A and B, the gate 48 allows the 60sP pulse to pass and, through the OR circuit 50, causes the flip-flop RS 51 to toggle whose output Q goes to 1. The signals of lines A and B are produced by the divider 30 and are decoding signals making it possible to fix the moment when the signal ENINH must be activated by signed by 128HP, but only once every 60 seconds, the signal ENINH. This signal is applied to an input of AND gate 47 and predisposes said gate to be on when all of its other inputs are at 1. The upper inputs of AND gate 47 are connected to outputs Q1 to Q6 of dividers 24 to 29 and pass all at 1 just before the next 128HP pulse marked with dotted lines in FIG. 6 appears. At the same instant, an 8kP1 intermediate pulse is emitted and the AND gate 47 is on and produces the inhibition pulse INH.

La mémoire non volatile présente à ses sorties Q1 M à Q6M la valeur binaire qui y a été programmée selon le processus indiqué plus haut. Cette valeur est reportée aux premières entrées des circuits ET 40 à 45. Au moment où apparaît l'impulsion INH sur les secondes entrées des mêmes portes réunies ensemble, la valeur binaire, choisie à 101010, est reportée aux entrées R1 à R6 des diviseurs 24 à 29 et modifie le contenu desdits diviseurs comme indiqué sur le diagramme de la figure 6. On remarque en particulier que la présence d'une valeur 1 sur les entrées R1, R3 et R5 fait basculer les sorties des diviseurs correspondants 01, Q3 et Q5, tandis que la présence d'une valeur 0 sur les entrées R2, R4 et R6 retient les sorties des diviseurs correspondants Q2, Q4 et Q6 à leurs valeurs hautes. Ainsi l'impulsion 128HP, marquée en pointillés et qui serait apparue si l'inhibition n'avait pas eu lieu, n'apparaît pas et est retardée dans le sens de la flèche f. Comme le montre le diagramme de la figure 6, il faudra 21 impulsions 8kP pour que toutes les sorties Q1 à Q6 des diviseurs 24 à 29 se retrouvent à zéro et qu'apparaisse l'impulsion à 128HP. Ce nombre k = 21 est représentatif de la différence de fréquence existant entre la fréquence de l'oscillateur de la montre et la fréquence étalon et s'écrit 101010 en valeur binaire.The non-volatile memory presents at its outputs Q1 M to Q6M the binary value which has been programmed there according to the process indicated above. This value is carried over to the first inputs of the AND circuits 40 to 45. When the INH pulse appears on the second inputs of the same gates combined together, the binary value, chosen at 101010, is carried over to the inputs R1 to R6 of the dividers 24 to 29 and modifies the content of said dividers as indicated in the diagram in FIG. 6. It is noted in particular that the presence of a value 1 on the inputs R1, R3 and R5 switches the outputs of the corresponding dividers 01, Q3 and Q5 , while the presence of a value 0 on the inputs R2, R4 and R6 retains the outputs of the corresponding dividers Q2, Q4 and Q6 at their high values. Thus the 128HP pulse, marked in dotted lines and which would have appeared if the inhibition had not taken place, does not appear and is delayed in the direction of the arrow f. As the diagram in FIG. 6 shows, it will take 21 8kP pulses for all the outputs Q1 to Q6 of the dividers 24 to 29 to be zero and for the pulse to appear at 128HP. This number k = 21 is representative of the difference in frequency between the frequency of the watch oscillator and the standard frequency and is written 101010 in binary value.

On notera enfin que l'impulsion d'inhibition INH est utilisée pour remettre à zéro le flip-flop RS 51 ce qui met fin au signal ENINH.Finally, note that the inhibition pulse INH is used to reset the RS 51 flip-flop to zero, which ends the signal ENINH.

3. Phase de contrôle en mode rapide3. Control phase in fast mode

Comme on l'a déjà mentionné, la phase de programmation peut être suivie par une phase de contrôle en mode rapide pour contrôler si la mémoire a bien été programmée à la valeur binaire voulue. Ceci constitue une caractéristique dépendante de l'invention.As already mentioned, the programming phase can be followed by a control phase in quick mode to check whether the memory has been programmed at the desired binary value. This constitutes a characteristic dependent on the invention.

Le mode rapide utilisé pour ce contrôle est avantageux par le gain de temps qu'il apporte. En effet si ce contrôle devait se faire en march normale de la montre, il faudrait attendre 60 secondes (dans l'exemple choisi) pour obtenir un résultat et encore ne serait-on pas sûr de son exactitude puisque chaque période d'inhibition serait espacée par 59 périodes sans inhibition.The fast mode used for this control is advantageous because of the time savings it brings. Indeed if this control were to be done in normal watch market, we would have to wait 60 seconds (in the example chosen) to obtain a result and again we would not be sure of its accuracy since each inhibition period would be spaced by 59 periods without inhibition.

Aussi, d'après un mode d'exécution de l'invention, le dispositif comprend-il des troisièmes moyens, mis en oeuvre après l'application des premier et second moyens précédemment discutés, pour contrôler que le taux de division correspond au nombre k introduit dans la mémoire. Dans une version préférée de l'invention ces troisièmes moyens comportent un détecteur sensible au retour de la tension à son niveau bas dès la fin de la période Ti pour accélérer, pendant une période prédéterminée Tf, le moteur à une vitesse v plus rapide que celle utilisée pour afficher le temps, et l'ajustement du taux de division à une vitesse v/2, ce qui permet ainsi l'alternance d'intervalles entre impulsions motrices avec et sans ajustement pour mesurer la différence de fréquence existant entre la fréquence de l'oscillateur de la montre et la fréquence étalon.Also, according to an embodiment of the invention, does the device comprise third means, implemented after the application of the first and second means previously discussed, to check that the division rate corresponds to the number k introduced into memory. In a preferred version of the invention, these third means comprise a detector sensitive to the return of the voltage to its low level at the end of the period Ti to accelerate, for a predetermined period Tf, the motor to a speed v faster than that used to display the time, and the adjustment of the division rate at a speed v / 2, which thus allows the alternation of intervals between driving pulses with and without adjustment to measure the difference in frequency existing between the frequency of l watch oscillator and standard frequency.

Le diagramme de la figure 7 explique schématiquement la phase de fonctionnement en mode rapide. Dès qu'un signal dit de mode rapide (FAST) est émis, le moteur reçoit des impulsions (MOT) à 32 Hz et le signal autorisant l'inhibition (ENINH), de même que le signal d'inhibition qui lui est lié (INH), sont émis à une vitesse deux fois plus lente, soit 16 Hz. Il y a ainsi alternance entre périodes avec et sans inhibition ce qui permet de contrôler en un temps très court (par exemple en 4 périodes de 1/32 s) le rapport existant entre fréquence ajustée et fréquence non ajustée. La mesure proprement dite peut être réalisée au moyen de l'appareil QUIS dont on a parlé plus haut.The diagram in FIG. 7 schematically explains the phase of operation in fast mode. As soon as a so-called fast mode signal (FAST) is sent, the motor receives pulses (MOT) at 32 Hz and the signal authorizing the inhibition (ENINH), as well as the inhibition signal which is linked to it ( INH), are emitted at a speed twice as slow, ie 16 Hz. There is thus alternation between periods with and without inhibition which allows control in a very short time (for example in 4 periods of 1/32 s) the relationship between adjusted frequency and unadjusted frequency. The actual measurement can be carried out using the QUIS device mentioned above.

Pour mettre en oeuvre ce mode particulier de l'invention le circuit intérieur à la montre 5 comporte un flip-flop D 55 de même qu'une porte ET 56 arrangés comme le montre la figure 2. Dans ce schéma les signaux à 32 et à 16 Hz sont tirés du diviseur par 128 référencé 30. Le signal à 32 Hz est envoyé au circuit driver 31 et excite le moteur à cette vitesse quand le signal FAST est présent. Le signal à 16 Hz est envoyé à une entrée de la porte ET 56, porte qui joue exactement le même rôle que la porte ET 48 pour le signal à 60 secondes 60sP. Quand le signal FAST est présent à l'entrée de la porte ET 56, la porte ET 48 est bloquée par l'inverseur 49. Ainsi les signaux ENINH et INH sont créés à la vitesse de 16 Hz et à un moment fixé par les signaux A et B comme c'était le cas pour la phase d'exécution normale de l'inhibition.To implement this particular mode of the invention, the circuit inside watch 5 includes a flip-flop D 55 as well as an AND gate 56 arranged as shown in FIG. 2. In this diagram the signals at 32 and at 16 Hz are taken from the divider by 128 referenced 30. The signal at 32 Hz is sent to the driver circuit 31 and excites the motor at this speed when the FAST signal is present. The signal at 16 Hz is sent to an input of the AND gate 56, a gate which plays exactly the same role as the AND gate 48 for the signal at 60 seconds 60sP. When the FAST signal is present at the input of the AND gate 56, the AND gate 48 is blocked by the inverter 49. Thus the signals ENINH and INH are created at the speed of 16 Hz and at a time fixed by the signals A and B as was the case for the normal execution phase of inhibition.

Le signal FAST débute quand la tension d'alimentation est retournée à son niveau bas, à la fin de la période de programmation Ti. On se reportera aux figures 2 et 4 pour comprendre ce fonctionnement. A la fin de la période Ti, le détecteur 33 émet un signal reçu par l'entrée CI du flip-flop 55 dont la sortie Q passe au potentiel haut de son entrée D. Le signal FAST est ainsi présent à la sortie Q du flip-flop 55 et permet la phase de contrôle en mode rapide exposée ci-dessus. Cette phase de contrôle va durer une période Tf, par exemple 4 fois 1/32e de seconde. On met fin à la période Tf par un signal de remise à zéro RAZ de l'entrée R du flip-flop 55. Ce signal peut être tiré de la combinaison de signaux présents dans le diviseur à 128 référencé 30. Dès que le signal FAST est annulé, le circuit de la montre fonctionne en mode normal.The FAST signal begins when the supply voltage has returned to its low level, at the end of the programming period Ti. We will refer to Figures 2 and 4 to understand this operation. At the end of the period Ti, the detector 33 emits a signal received by the input CI of the flip-flop 55, the output Q of which passes to the high potential of its input D. The signal FAST is thus present at the output Q of the flip -flop 55 and allows the control phase in rapid mode described above. This control phase will last a period Tf, for example 4 times 1/32 of a second. The period Tf is ended by a reset signal RAZ of the input R of the flip-flop 55. This signal can be taken from the combination of signals present in the divider at 128 referenced 30. As soon as the signal FAST is canceled, the watch circuit operates in normal mode.

La figure 8 montre qu'on peut mettre à profit le circuit autorisant la phase de contrôle au mode rapide pour des besoins de contrôle uniquement lors d'une révision de la montre par exemple. Pour cela on raccourcit considérablement la constante de temps du monostable 89 du circuit extérieur 14, de telle sorte que la période Ti ait une durée insuffisante à démarrer la phase de programmation. Le flanc descendant de l'impulsion Ti, qui a été préalablement porté à une tension supérieure à celle du déclenchement du détecteur de tension 33 du circuit intérieur 5, démarre immédiatement la phase de contrôle en mode rapide (FAST). L'écart de fréquence est alors mesuré par l'appareil QUIS dont on a déjà parlé. Si cet écart est correct on en reste là. Si tel n'est pas le cas, on fait démarrer une nouvelle phase de programmation. Ici on a trouvé qu'une période Ti composée d'un temps de montée de 300lis atteignant 4V, suivi immédiatement d'un temps de descente de 3OOgs également, convient parfaitement au seul processus de contrôle rapide.FIG. 8 shows that the circuit authorizing the control phase in rapid mode can be used to advantage for control purposes only during a revision of the watch for example. For this, the time constant of the monostable 89 of the external circuit 14 is considerably shortened, so that the period Ti has insufficient duration to start the programming phase. The falling edge of the pulse Ti, which has previously been brought to a voltage greater than that of the triggering of the voltage detector 33 of the internal circuit 5, immediately starts the control phase in fast mode (FAST). The frequency difference is then measured by the QUIS device of which we have already spoken. If this difference is correct, we will stop there. If this is not the case, a new programming phase is started. Here it has been found that a period Ti composed of a rise time of 300lis reaching 4V, followed immediately by a fall time of 3OOgs also, is perfectly suited to the only rapid control process.

Claims (4)

1. Programming arrangement for an electrically alterable non-volatile memory (32) for a timepiece (1), said timepiece including an oscillator (21), a multistage frequency divider (22 to 30) the division rate of which is adjustable by alteration of a number k of pulses furnished by a stage (23) thereof, the number k being representative of the frequency difference between the oscillator frequency and a standard frequency and appearing in a binary form recorded in the non-volatile memory in order to modify the contents of certain predetermined stages (24 to 29) of the divider at regular intervals, a stepping motor (M) receiving driving pulses from the divider to display time in an analog manner and a receptacle (4) adapted to accomodate an energy cell, characterized by the fact that such arrangement includes first means controlled by the end of a driving pulse so as to introduce into said predetermined divider stages a binary state corresponding to said number k and second means for blocking the contents of said stages as soon as said binary state has been attained and thereafter recording said contents in said non-volatile memory.
2. Programming arrangement according to claim 1, characterized by the fact that the first means are located externally to the timepiece and are electrically coupled thereto by means of a connector (8) plugged into the energy cell receptacle by its two terminals, said first means comprising an energy source for energizing the timepiece by a low level voltage (1.5 V) or a high level voltage (6 V) a memory- counter (62 to 67) into which may be introduced the number k, a time base (60) the frequency of which is coarsely adjusted to the frequency of the timepiece oscillator (21), a detector (80) for driving pulses (Imot, M1, M2) the output edges (93) of which coincide with the zero resetting of said predetermined divider stages, the output edge of one of said driving pulses defining the beginning of a period TD the duration of which is defined by the time necessary to introduce into said predetermined stages the binary state corresponding to the number k contained in the memorycounter (62 to 67), a switch (88) for switching the energy source over to the high level voltage (6 V) as soon as the end of said period TD is reached and a delay circuit (89) for maintaining said voltage at its high level over a predetermined period Ti, and that the second means are incorporated into the timepiece and include a voltage level detector (33) which, when said voltage has attained a predetermined value situated between said low and high level voltages, blocks the contents of said predetermined divider stages at the binary value they have attained at the end of said period TD and records said contents in said non-volatile memory (32) during said predetermined period Ti.
3. Programming arrangement according to claim 1, characterized by the fact that it further comprises third means put into operation following operation of the first and second means so as to check that the rate of division corresponds to the number k representing the difference in frequency existing between the oscillator frequency and the standard frequency.
4. Programming arrangement according to claim 3, characterized by the fact that the first means are located externally to the timepiece and are electrically coupled thereto by means of a connector (8) plugged into the energy cell receptacle by its two terminals, said first means comprising an energy source for energizing the timepiece by a low level voltage (1.5 V) or a high level voltage (6 V) a memory- counter (62 to 67) into which may be introduced the number k, a time base (60) the frequency of which is coarsely adjusted to the frequency of the timepiece oscillator (21), a detector (80) for driving pulses (Imot, M1, M2) the output edges (93) of which coincide with the zero resetting of said predetermined divider stages, the output edge of one of said driving pulses defining the beginning of a period TD the duration of which is defined by the time necessary to introduce into said predetermined stages the binary state corresponding to the number k contained in the memory-counter (62 to 67), a switch (88) for switching the energy source over to the high level voltage (6 V) as soon as the end of said period TD is reached and a delay circuit (89) for maintaining said voltage at its high level over a predetermined period Ti, that the second means are incorporated into the timepiece and include a voltage level detector (33) which, when said voltage has attained a predetermined value situated between said low and high level voltages, blocks the contents of said predetermined divider stages at the binary value they have attained at the end of said period TD and records said contents in said non-volatile memory (32) during said predetermined period Ti and that the third means comprise a detector (55) responsive to restoration of the voltage to its low level at the end of the period Ti thereby to accelerate the motor during a predetermined period Tf to a higher speed v than that normally employed for time display and adjust the rate of division to a speed v/2 thus permitting the alternation of intervals between driving pulses with and without adjustment so as to measure the frequency difference between the oscillator frequency (21) and the standard freauencv.
EP87109566A 1986-07-10 1987-07-03 Device for programming a non volatile memory of a time piece Expired EP0253227B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH277386A CH664868GA3 (en) 1986-07-10 1986-07-10
CH2773/86 1986-07-10

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EP0253227A1 EP0253227A1 (en) 1988-01-20
EP0253227B1 true EP0253227B1 (en) 1989-11-29

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EP (1) EP0253227B1 (en)
JP (1) JP2519464B2 (en)
CH (1) CH664868GA3 (en)
DE (1) DE3761065D1 (en)
HK (1) HK2295A (en)

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Also Published As

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CH664868GA3 (en) 1988-04-15
JPS6329291A (en) 1988-02-06
US4763309A (en) 1988-08-09
JP2519464B2 (en) 1996-07-31
HK2295A (en) 1995-01-13
DE3761065D1 (en) 1990-01-04
EP0253227A1 (en) 1988-01-20

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