EP0252911A1

EP0252911A1 - Programmable circuit for the control of a liquid crystal indicator.

Info

Publication number: EP0252911A1
Application number: EP86901788A
Authority: EP
Inventors: Manfred Koslar; Peter Hubski
Original assignee: Createc Gesellschaft fuer Elektrotechnik mbH
Current assignee: Kontron Elektronik GmbH
Priority date: 1985-03-06
Filing date: 1986-03-06
Publication date: 1988-01-20
Anticipated expiration: 2006-03-06
Also published as: AU5581386A; ATE70920T1; EP0252911B1; JPS62502992A; DE3508321A1; DE3683155D1; WO1986005305A1; US4839638A

Abstract

PCT No. PCT/DE86/00094 Sec. 371 Date Nov. 6, 1986 Sec. 102(e) Date Nov. 6, 1986 PCT Filed Mar. 6, 1986 PCT Pub. No. WO86/05305 PCT Pub. Date Sep. 12, 1986.Programmable circuit for controlling a liquid crystal display (LCD controller), possibly through the intermediary of driver stages, for two bus structures, one of which serves for the exchange of data with a computer while the other serves for the exchange of data with at least one addressable memory which is associated with the liquid crystal display (LCD), with both bus structures being configured as complete, parallel bus structures composed of address, data and control lines which, when the control circuit is in a given switching state and possibly in response to a corresponding additional signal from the computer, are interconnected in such a manner that data exchange is possible between the memory associated with the liquid crystal display and the computer.

Description

Programmable circuit for controlling a liquid crystal display

Description

The invention relates to a control circuit of the type specified in the preamble of claim 1.

Circuits of this type are known which make it possible to organize a matrix-like control to derive the necessary liquid-containing (LCD) display module, information-containing signals from a processor system, the clock and timing signals for the LCD display being generated in the control circuit itself. The characters to be reproduced are usually generated with the aid of memories which are present in the control circuit and are capable of displaying complete characters on the LCD display when a corresponding command is given.

In the case of conventional liquid crystal displays of high resolution, signal sequences are to be created in accordance with the matrix-like control, which on the one hand emit corresponding signal patterns in sequential image lines, but on the other hand also ensure that the characters are rewritten, for example using the known "two-thirds method" , is carried out in a regular repetition and, in addition, polarity reversals are carried out at intervals in order to avoid electrolysis phenomena in the liquid crystal arrangements. In addition, switching means may have to be provided to supply several of the display areas next to one another, since the maximum controllable area is limited by the repetition intervals to be observed. The signals generated in this way reach the LCD module via driver stages.

It is disadvantageous that the known control devices for changing the image content require more or less complex operations which have in common that the processor's access to the memory area assigned to the LCD display is only indirect after a corresponding one Request can be made via the control circuit, waiting cycles and similar delays must be accepted. In other embodiments, the content of the liquid crystal display can only be initiated indirectly via a memory, which in turn contains the components necessary for generating complete drawing elements composed of point groups.

In contrast, the invention specified in claim 1 is based on the task of largely simplifying a control device of the type mentioned at the outset, changes in the screen content being made as independently as possible of the functional cycles of the control circuit without taking into account special time conditions.

The invention is based on the finding that time-optimal processing of signals present in an image memory is possible if the memory area assigned to the image can be achieved essentially independently of the internal control sequence of the circuit and largely unaffected by the times required to supply the screen with data from memory are required. The access times for the control of the LCD display module can be kept so short that the data access from the computer system is not or hardly affected at all.

The control circuit is therefore for the connected

Computer "quasi-transparent", so that a change in the screen (memory) content at any time regardless of the cyclical internal processes of the control device can follow. The memory for holding the screen contents appears to the processor system as part of the memory areas which it can directly access. It is controlled via memory-oriented addressing in accordance with the usual addressing of RAM or ROM memory modules. The access to the "reserved" memory areas for the LCD display is carried out in a regular sequence with short-term shutdown of access by the computer, with appropriate buffering between the computer and the screen memory can be achieved that no or at most a slight time delay for the processor system occurs.

It is of particular importance that changes in image content can be made with minor changes in information without subjective interference to the viewer by directly interfering with the current image display.

In the case of complex changes to the image representations, it is possible to switch between two or more different storage areas with equal rights, each of which comprises the entire image content. In this case, the image change takes place "suddenly" by switching the control circuit, while if the processor wishes to successively change the image content, the control times of the changes in individual image sections can be selected such that image elements "build up" one after the other before the eyes of the viewer. By calling up two connected by means of mathematical / logical connections Image contents can be generated at any time further image representations, which result from a combination or other logical assignment of the image elements of the superimposed image contents of the two memory areas. This control is carried out - likewise memory-oriented - by means of registers which are addressable by the computer and preferably provided within the control circuit, the contents of which are read and evaluated by the control circuit.

If the timing of the switching is determined by the internal timing of the control circuit in such a way that the times for which the internal lines of the control circuit are connected to the BUS structure for transmitting data to the liquid crystal display are of the order of the times Transmission of individual data words during data exchange with the computer, and are preferably smaller, the access to the memory areas assigned to the LCD modules is not or only occasionally hindered, so that the access of the computer is not restricted. Data words are preferably read out from the memory for driving the LCD module one after the other, in particular the time of the subsequent parallel-serial conversion giving the computer access time again. The computer and control circuit operate asynchronously in their timing control relative to one another.

Advantageous developments of the invention are characterized in the subclaims or are shown in more detail below together with the description of the preferred embodiment of the invention with reference to the figures. Show it: FIG. 1 shows a block diagram of the control device according to the invention within a processor system that controls an LCD display unit,

Figure 2 is a block diagram to explain the internal signal processing for an embodiment of the invention and

FIG. 3 details of the internal circuitry of the exemplary embodiment according to FIG. 2.

In the block circuit shown in FIG. 1, a control circuit 1 is provided between a first complete bus structure 2, consisting of data bus 2a, address bus 2b and control bus 2c. This bus structure forms the system bus, which enables data operations between the control circuit according to the invention and a computer 3 and a main memory 4 assigned to the computer. The system bus 2 forms a known bus structure, as is used in the conventional microprocessors.

The control device 1 is connected to a further bus structure 5, which likewise consists of a data bus 5a, an address bus 5b and a control bus 5c. Several - in the present example two - memory areas 6, 7 are connected to this second bus structure, each of which contains the complete image content of graphic information to be reproduced on an LCD module. The LCD module 8 is controlled by the control circuit 1 via a driver stage 9, the data stored in the memories 6 or 7 existing data are converted by the control circuit into serially transmitted information which is adapted to the respective LCD module. In addition to the line-by-line transmission of the image content in cycles required for refreshing the image, polarity reversals and possibly further control pulses are necessary, which are necessary for the operation of such a display module. The data are transmitted over two or more lines (display data), the number of these data lines depending on how many fields the display area is divided into.

In the internal circuitry of the control part 1 shown in FIG. 2, an interface circuit 11 is distinguished in terms of block circuitry, which maintains the data communication with the bus structure 2 and thus forms the communication interface with the external computer system.

The block diagram of the internal circuit shown in FIG. 2 further shows how the control lines (control bus in FIG. 1) are composed in detail. The following signal names were used:

Name of function

D0 - D7 bidirectional system data bus.

A0 - A15 system address bus

Image memory 2 selection signal, active LOW, selects image RAM 2 for data exchange with the system computer

Image memory 1 selection signal, active LOW, selects image RAM 1 for data exchange with the system computer

Circuit selection signal, active LOW, activates the internal address decoder for internal register programming

Write pulse, active LOW

Read pulse, active LOW

resets the circuit without registering loss of hold

XIN, XOUT connections for the internal oscillator, XIN can also be used as an external clock input

TEST Chip test inputs / outputs RD0 - RD7 Bi-directional frame buffer data bus

RA0 - RA15 image memory address bus

Output enable image memory control signal,

Active LOW

R / W read / write frame buffer control signal, HIGH = read, LOW = write Selection signal, first frame buffer

Selection signal, second image memory CP1, CP2 LCD control signal, shift clock

LP LCD control signal, shift cycle end pulse

FP LCD control signal, end of the first shift cycle pulse

FR LCD control signal for reversing the polarity of the operating voltage for the LCD segments

BLC flashing frequency clock input Interrupt output for the system computer, can be deleted

Ready signal of the control circuit, LOW = control circuit is ready to exchange data with the system computer DL1, DL2 data outputs for controlling the LCD module etc.

Correspondingly, the names and functions of the connections to the LCD module 8 can be seen from the table above. A time control 12 is synchronized by an externally connectable crystal 13. An additional test device 14 can be controlled externally and transmits an acknowledgment output "test" signal after the function test of the module has been properly completed. The connections to the external control bus are made by means of a module 14 which effects the data transmission to the second bus structure 5 according to FIG. 1.

A control module 15 generates the serial data signals for controlling the data lines of the LCD module. The further control pulses for the LCD display come from the LCD driver controller 16, which generates the signals that are supplied to the external driver circuits.

The control pulses which are generated by means of the driver controller 16 can be influenced via internal registers, the various control sequences corresponding to the various commercially produced LCD modules being represented by different data words.

In the illustration according to FIG. 3, those components are shown schematically which are functionally effective during the operation of the control circuit according to the invention the. The designation of the external modules corresponds to the form used in FIGS. 2 and 3.

A central element for linking the two bus structures 2 and 5 is a multiplexer 21, to which the external bus structure 2 (data, address and control bus 2a, 2b and 2c) is fed via a data buffer 22. The connection to the external bus structures for the individual bus lines is influenced as a function of the current operating state of the control circuit 1 by means of the switch connections shown as internal blocks. The connection of the bus lines with the memory areas 6 and 7 assigned to the image has priority over the access of the computer via lines 2. The bus lines 5a to 5c are therefore normally reserved for the internal access of the control circuit 1 in order to use the in the Store 6 and 7 data found to build up the image information.

Controlled by the preferably quartz-stable timer 12, 13, the pulse sequences required to build up the image display are generated in a fixed time grid, one of the memories 6 or 7 being accessed for the image content. Because the two memory areas of the control unit are available with priority, difficulties due to possible collisions with the computer access are avoided. The LCD display shows the memory content, the type of display being triggered by an external command from the computer via the bus structure 2 and the corresponding commands being stored in a register 23. The storage of commands in the Register 23 can occur at any time regardless of the state of the image generation, provided that only the type of image representation is affected. (Those commands which change the type of control of the LCD display 8 and practically ensure the adaptation to another LCD module. Can be disregarded here.)

Both memories 6 and 7 can then be accessed twice in succession with respect to the same picture content elements, whereby logical links between these picture contents can be generated in an arithmetic unit 24, so that a pixel is displayed in black if one of the corresponding pixels in both memories is black should be controlled (OR-linked display) or only if both are darkly controlled (AND-) or it can also be achieved that the screen content is only blanked if one of the corresponding memory locations contains the information "black" contains (EXCLUSIVODER or EXOR representation). The memories 6 and 7 are addressed in such a way that successive memory addresses identify memory locations which also follow one another in the image display. Corresponding memory addresses in memories 6 and 7 identify corresponding image areas. The data words recorded in the memories 6 and 7 describe - according to their bit length - the state of a corresponding sequence of pixels in the LCD display 8. Changes which affect the register 23, which occur during the image construction, do not disturb the human observer , because - if the image information in the following in general is retained - this "change of image" is perceived as a natural change.

The fact that the image information is obtained directly from memories 6 and 7 - without the interposition of character generators. the structure of the control circuit 1 is extremely simple. The need for information to be recorded for the image structure in memories 6 and 7 increases. However, since the relevant data can be stored and changed without loss of time by the circuit according to the invention, there would be no simplification through the use of character generators within the control part 1. By contrast, the direct access to the memories 6 and 7, as will be described below, increases the universality of the use of the control circuit considerably.

When using the data read from the memories 6 and 7 by means of the bus structure 5 and transferring them - possibly after an arithmetic operation in the module 24 in a parallel-serial converter 15 - a data word is in each case in the clock of the timer 12 as bitwise pulse train to a corresponding data line to the driver circuit 9. For reasons of simplicity, FIG. 3 shows only one data line. For the simultaneous control of several separate image areas, the parallel-serial converter 15 would have to be provided several times.

As part of the time cycle generated by the timer, the internal Control part 22 and the timer contained therein generates a pulse which sets the data transmission in the multiplexer 21 so that the internal bus lines are connected to the external bus 5. Due to the simultaneous addressing of the respective memory area 6 or 7 (depending on a data word contained in the register 23), the memory content is transferred to the parallel-serial converter 15 and, after the clock signal has been delayed by a delay element 26 for a short time, the Reading of this data word from the parallel-serial converter is effected via a data line to the driver circuit 9. While the parallel-serial converter 15 is still busy reading the data word, the multiplexer 21 is again switched in the direction of data traffic between the bus structures 2 and 5 via a further delay circuit 27.

The delay lines 26 and 27 have only symbolic meaning in the block diagram shown. The relevant signal delays can also be generated in other ways, for example by counters, natural line delays in signal transmission etc.

Because the access times for the parallel-serial conversion for the transmission of a data word to the LCD unit are relatively short, the computer connected to the bus structure 2 has almost unlimited access to the memories 6 and 7.

The memory areas 6 and 7 for the connected computer circuit are now directly accessible and the Control circuit 1 is "quasi-transparent". The data available in memories 6 or 7 can be changed or deleted during access to control the LCD. In order to obtain a constant image display, a complete image change is carried out continuously. While the computer accesses one of the memory areas 6 or 7, a change in the information of a complete image display is carried out, a fixed image with the necessary “refresh” cycles can be reproduced from the other memory area without being influenced by the image change. In a preferred application of the invention, completely generated image contents are stored in the correct order with respect to the addressing in the main memory 4 (FIG. 1), which can be briefly transferred to a memory 6 or 7 assigned to the LCD, if required. All information elements used for character formation are present in main memory 4 and can be addressed as a unit by macro commands and transferred to the corresponding memory areas of memory 6 and 7. There is a high degree of flexibility, since fixed character grids etc. are not required. The LCD display can be used in an independent graphics-capable company, whereby complex characters such as letters and numbers etc. can be read in at short notice by means of appropriate data transfers.

If the memory areas 6 or 7 are not exactly that

Correspond to memory requirements of the LCD element and - as in normal cases - slightly exceed its capacity, the surplus memory spaces can be saved by the computer if used as storage area in quasi-direct access. The memory areas 6 and 7 can also be addressed in DMA mode by external modules, since corresponding control lines ("ready") are available.

The data buffer 22 ensures that the data for access via the bus structure 2 are still available for a short time even when the multiplexer 21 is already in its operating state for the transmission of data in the internal control part 25. Correspondingly, data can be read into the buffer area when the multiplexer is busy with the transfer of data from the memories 6 or 7 to the LCD display 8. In a practical embodiment, the addressed data are still transferred to the buffer, for example in read mode, by means of a corresponding clock cycle before the multiplexer again allocates the bus 5 to the control circuit internally. In the write mode, the data transmitted by the computer are recorded and only read into the memories 6 or 7 via the multiplexer when the bus 5 is again available to the computer.

This so-called "handshake" operation is carried out in accordance with the agreements with the associated control lines that are common in processor technology. By using a data and address buffer in the configuration shown, there is the possibility, by increasing the speed of the internal processing of the access of the LCD display to the memory compared to the speed of the external computer, the data processing with the computer approximately by To make half slower than the internal clock frequency of data processing. With such a time control using the buffer, the internal operation of the LCD module no longer appears to the computer in a time-delaying manner.

By providing a "ready" line within the control bus 2c, an external unit is signaled that it is ready to accept or deliver data. This state is always displayed when the buffer register 22 - depending on the direction of the transfer - has data ready or can accept it. Such a control line makes the control unit 1 with the downstream memory areas 6 and 7 appear as directly addressable memories. The "Ready" signal is emitted if the buffer register has meanwhile been discharged to the address in memory 6 or 7, also contained in the buffer register, or if a read cycle has been carried out from these memories, so that control of DMA-capable modules in is possible in a favorable manner.

The embodiment of the invention is not limited to the preferred exemplary embodiment specified above. Rather, a number of variants are conceivable which make use of the solution shown, even in the case of fundamentally different types.

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Claims

Expectations

1. Programmable circuit for controlling a liquid crystal display (LCD controller), optionally with the interposition of driver stages, for two separate bus structures, one of which is used for data exchange with a computer, while the other is used for data exchange with at least one addressable memory associated with the liquid crystal display (LCD)

characterized ,

that both bus structures are designed as complete, parallel bus structures, consisting of address, data and control lines, which are interconnected so that a given switching state of the control circuit and, if appropriate, a corresponding additional signal from the computer Data can be exchanged between the memory assigned to the liquid crystal display and the computer.

2. Control circuit according to claim 1, characterized in that the predetermined switching state of the control circuit consists in that the BUS structure, which is used for connection to the memory area assigned to the liquid crystal display, not with internal control lines, the control circuit for transmitting data to the liquid crystal display is switched, the timing of the establishment of this connection being determined by the internal timing of the control circuit.

3. Control circuit according to one of the preceding claims, characterized in that the connection between the BUS structure, via which the data exchange takes place with the memory associated with the liquid crystal display, and the BUS structure, which serves for data exchange with the computer, with the inclusion of at least one Buffer memory is made.

4. Control circuit according to one of claims 2 or 3, characterized in that the timing determined by the internal timing of the control circuit of the switching takes place in such a way that the times for which the internal lines of the control circuit with the BUS structure for the transmission of data are connected to the liquid crystal display, are in the order of magnitude of the times for the transmission of individual data words during data exchange with the computer and are in particular smaller.

5. Control circuit according to one of the preceding claims, characterized in that the parallel-serial conversion of a data word intended for transmission to the liquid crystal display takes place during a period at which the bus structure, which is used for Connection to the memory area assigned to the liquid crystal display is not connected to the internal lines of the control circuit for transmitting data to the liquid crystal display.

6. Control circuit according to one of the preceding claims, characterized in that a multiplexer is provided, the BUS structure, via which the data exchange takes place with at least one addressable memory, which is assigned to the liquid crystal display (LCD), as a function of the internal timing of the control circuit alternately connects on the one hand with the bus structure assigned to the computer and on the other hand with the internal control lines for the transmission of data to the liquid crystal display.

7. Control circuit according to one of the preceding claims, d a d u r c h g e k e n e z e i c h n e t that the programming of operating states of the control circuit is carried out via its internal register, which can be reached with the bus structure connected to the computer.

8. Control circuit according to one of the preceding claims, characterized in that Steuerleitungeh (ready) are provided which allow direct access of DMA-compatible components to the BUS structure for data exchange with the liquid crystal display.

9. Control circuit according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that different memory areas assigned to the liquid crystal display can be reached under identical addresses, the selection being carried out via additional control lines (CS1 and CS2).

10. Control circuit according to one of the preceding claims, characterized in that various memory areas assigned to the liquid display can be logically linked by means of data words that can be stored in a register, the individual pixels corresponding to the result of the logical linking of the memory contents corresponding to one another when the corresponding data word characterizing this state is stored Pixels are reproduced.

11. Control circuit according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that different memory areas assigned to the liquid crystal display can be selected separately by means of data words that can be stored in a register and can be displayed on the liquid crystal display.

12. Control circuit according to one of the preceding claims, characterized in that a plurality of simultaneously controllable data lines are provided for supplying fields, each of which transfer different image content.

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