EP0251734A2 - Statische RAM-Speicheranordnungen - Google Patents

Statische RAM-Speicheranordnungen Download PDF

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Publication number
EP0251734A2
EP0251734A2 EP87305719A EP87305719A EP0251734A2 EP 0251734 A2 EP0251734 A2 EP 0251734A2 EP 87305719 A EP87305719 A EP 87305719A EP 87305719 A EP87305719 A EP 87305719A EP 0251734 A2 EP0251734 A2 EP 0251734A2
Authority
EP
European Patent Office
Prior art keywords
selecting
circuit
memory device
pull
column
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP87305719A
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English (en)
French (fr)
Other versions
EP0251734B1 (de
EP0251734A3 (en
Inventor
Hitoshi Taniguchi
Keisuke Ishio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of EP0251734A2 publication Critical patent/EP0251734A2/de
Publication of EP0251734A3 publication Critical patent/EP0251734A3/en
Application granted granted Critical
Publication of EP0251734B1 publication Critical patent/EP0251734B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Definitions

  • This invention relates to static random-access memory devices.
  • RAM random-access memory
  • address data designates a selected memory cell
  • chip selection for designating a selected chip is also performed.
  • a 128-kbit memory static RAM may comprise two chips each having 64-kbit memory cells.
  • a 17-bit signal is used as an address signal supplied to the address input terminals.
  • the most significant bit is used as a chip selection signal which is supplied to the respective chip by means of a decoder, so as to designate which one of the chips is to be used.
  • the remaining 16 bits are supplied to the designated chip to be used as an address signal to designate the memory cell to be accessed.
  • a high-speed static RAM comprising a single chip, which includes memory cells each comprising a flip-flop circuit composed of, for example, metal-oxide semiconductor field-effect transistors (MOSFETs), has previously been proposed.
  • MOSFETs metal-oxide semiconductor field-effect transistors
  • the number of memory cells (for example 64) is actually equal to the memory capacity, and the memory cells are arranged in the form of a lattice.
  • One of the memory cells is selected by address input signals comprising X (line) and Y (column) signals.
  • both of the bit lines are at a high-level, so that both of the column-selecting transistors are OFF at the time that the chip is accessed. Therefore, operation is impeded until the electrical potentials of the bit lines are decreased to a given level, and thus transferring of the data signals from the bit lines to the data lines is delayed. Accordingly, there is a disadvantage in that the transfer rate of data signals is decreased when selection between the chips is necessary, as compared with the situation when only selection of an address for a single chip is necessary. This makes the design of a high-speed static RAM difficult.
  • a static random-access memory device comprising:
  • a preferred embodiment of the invention overcomes or at least reduces the aforementioned disadvantage and provides a SRAM device which can operate at high speed, not only when address selecting operations but also when chip selecting operations are required.
  • the voltage control circuit adjusts the electrical potential of the bit lines to allow a column-selecting transistor to operate while selection of one of the chips is being performed.
  • the voltage control circuit may be a pull-down circuit.
  • the voltage control circuit comprises n-channel MOSFETs, the drains of which are connected to the bit lines, which the sources being connected to earth (ground) and the gates being connected to each other.
  • the preferred static random-access memory device further comprises a bit-line equalising circuit and a data-line load circuit.
  • a static random-access memory device which has a plurality of chips, comprises:
  • a static random-access memory comprises two chips 1 and 2.
  • each of the chips 1 and 2 may have 64-kbit memories so that the combined static RAM therefore totals 128 kbits of memory capacity.
  • a 17-bit signal is used as an address signal to be supplied to address input terminals 3.
  • the most significant bit thereof is used as a chip selection signal CS which is supplied to a selected one of the chips 1 and 2 by means of a decoder 4, so as to select which one of the chips is to be used.
  • the remaining 16 bits are used as an address signal AD for memory cell selection to be supplied to the chips 1 and 2. Therefore, a data signal stored in the one of the chips which is selected by the chip selection signal, at the memory cell which is selected by the 16-bit address signal AD, is output to an output terminal 5.
  • each of the chips 1 and 2 includes a plurality of (for example 64) memory cells 6, the number of which is chosen to be equal to the number of bits of memory capacity.
  • the memory cells 6 each comprise a flip-flop circuit including a metal-oxide semiconductor field-effect transistor (MOSFET), arranged in the form of a lattice.
  • MOSFET metal-oxide semiconductor field-effect transistor
  • One of the memory cells 6 is selected by an address input signal comprising X (line) and Y (column) components.
  • a power supply terminal Vcc to which, for example, direct current at 5V is supplied, is connected to one end of each of bit lines B and B by means of respective n-channel MOSFETs Q and Q constituting respective loads.
  • the other ends of the bit lines B and B are each connected to a corresponding end of respective data lines D and D by means of n-channel MOSFETs Q 4 and 0 5 constituting column-selecting transistors.
  • the other ends of the data lines D and D are connected to the data signal output terminal 5 by means of a common data line, output circuitry and the like.
  • a given number of memory cells 6, for example eight memory cells, are connected between the bit lines B and B .
  • bit lines B are inverted relative to those of the corresponding bit lines B. That is, one is at a high level "Hi” when the other is at a low level “Lo".
  • the sources and drains of p-channel MOSFETs Q 3 constituting bit line equalising transistors are connected between the bit lines B and B .
  • Equalising signals 4 E o are supplied from an equalising signal input terminal 7 to the gates of the MOSFETs Q 3 .
  • the equalising signals EQ are thus supplied, current flows through the MOSFETs Q 3 .
  • address signals are supplied to a Y decoder 8 by means of half of the address-signal input terminals A 0 , A 1 and A 2 and to a X decoder 9 by means of the other half of the address-signal input terminals A 3 , A 4 and A 5 .
  • the address signal is composed of 16 bits
  • 8 bits each of the address signal are supplied to the Y decoder 8 and to the X decoder 9.ln addition, the Y decoder 8 supplies column selecting signals Y 1 , Y 2 , --- Y 8 to the junction between both gates of the MOSFETs Q 4 and Q which constitute column selecting transistors.
  • the X decoder 9 supplies column selecting signals X 1 , X 2 , --- X 8 to respective memory cells 6.
  • a chip selecting signal CS input at a chip selecting input terminal 10 is supplied to the X decoder 9.
  • V BH V CC (V TH + A V TH )
  • the bit lines B and B are connected to the drains of n-channel MOSFETs Q and Q 7 constituting voltage control circuits or pull-down circuits.
  • the sources of the MOSFETs Q 6 and Q 7 are connected to earth.
  • the gates of the MOSFETs Q 6 and Q 7 are connected to each other. The junction of the gates is connected to a pull-down signal input terminal 11, to which pull-down signals ⁇ PD are supplied when one of the chips is selected.
  • the pull-down signals ⁇ PD are produced by a pull-down signal producing circuit, shown in Figure 3, which includes a chip selecting signal input terminal 12 to which the chip selecting signals cs are supplied.
  • the chip selecting signal input terminal 12 is connected to one input terminal of a NAND circuit 14 by means of four inverter circuits 13a, 13b, 13c and 13d connected in series.
  • the other input terminal of the NAND circuit 14 is connected to the output of the inverter circuit 13a.
  • the output of the NAND circuit 14 is connected to a pull-down signal output terminal 16 by means of a further inverter circuit 15.
  • the inverter circuits 13b, 13c and 13d constitute a time-delay circuit.
  • the pull-down signal output terminal 16 produces a pull-down signal ⁇ PD as shown in Figure 4C.
  • the electrical potential of each of the data lines D and D is, as shown in Figure 4H, the intermediate potential between the high level “Hi” and the low level “Lo” electrical potentials, which is for example 3.85V when the high level “Hi” and the low level “Lo” electrical potentials are 4V and 3.7V, respectively.
  • the data signal is output from the memory cell which is selected by the column-selecting signal and the line-selecting signal shown in Figure 4B, which signals are produced from the Y and X decoders 8 and 9, respectively, and the data signals are rapidly transferred to the data lines D and D from the bit lines B and B .
  • These data signals are supplied to the data output terminal 5 by means of the common data line and other circuitry.
  • the pull-down signals ⁇ PD shown in Figure 4C and the bit line equalising signals EQ shown in Figure 4D are produced by the chip selecting signals cs , and the pull-down signals PD are supplied to the pull down signal input terminal 11. Therefore, the MOSFETs Q 6 and Q 7 which constitute the pull-down circuit and are connected to the bit lines B and B , are ON when the pull-down signals ⁇ PD are supplied thereto.
  • the electrical potentials of the bit lines B and a are decreased below, for example, 3.2V which is the electrical potential at which the column-selecting transistors Q 4 and Q 5 turn ON.
  • the electrical potentials of the data lines D and D become the intermediate potential as shown in Figure 4F, for example 3.85V, between the high level "Hi” and the low level “Lo".
  • the equalising signals EQ have the operating potential shown in Figure 4D
  • the aforementioned operation is performed to allow the transistors Q 4 and Q 5 of the chips 1 and 2 to have electrical potentials by which the transistors Q 4 and Q 5 are operated.
  • data signals are output to the bit lines B and B from that memory cell which is selected by the column-selecting signals and the line-selecting signals produced from the Y and X decoders 8 and 9, respectively, and rapidly transferred to the data lines D and D .
  • the chip selecting operation is also performed, data signals can be transferred at the same speed as in the case where only an address is selected.
  • large - capacity high-speed static RAMs having a plurality of chips can readily be manufactured.
EP87305719A 1986-06-30 1987-06-26 Statische RAM-Speicheranordnungen Expired - Lifetime EP0251734B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP153311/86 1986-06-30
JP61153311A JPS639097A (ja) 1986-06-30 1986-06-30 スタテイツクｒａｍ

Publications (3)

Publication Number Publication Date
EP0251734A2 true EP0251734A2 (de) 1988-01-07
EP0251734A3 EP0251734A3 (en) 1989-07-12
EP0251734B1 EP0251734B1 (de) 1992-09-09

Family

ID=15559711

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87305719A Expired - Lifetime EP0251734B1 (de) 1986-06-30 1987-06-26 Statische RAM-Speicheranordnungen

Country Status (5)

Country Link
US (1) US5034924A (de)
EP (1) EP0251734B1 (de)
JP (1) JPS639097A (de)
KR (1) KR880000969A (de)
DE (1) DE3781607T2 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0394652A2 (de) * 1989-04-21 1990-10-31 Motorola, Inc. Speicher, der verteiltes Laden von Datenleitungen verwendet
EP0498336A1 (de) * 1991-02-07 1992-08-12 Texas Instruments Incorporated Verbindung mit gemeinsamer Leitung für ein integriertes Speicher-Array

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3057836B2 (ja) * 1991-08-19 2000-07-04 日本電気株式会社 半導体記憶装置
FR2694826B1 (fr) * 1992-08-13 1994-09-16 Thomson Composants Militaires Circuit intégré de mémoire avec protection contre des perturbations.
US5710742A (en) * 1995-05-12 1998-01-20 International Business Machines Corporation High density two port SRAM cell for low voltage CMOS applications

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0139385A2 (de) * 1983-09-14 1985-05-02 Mitsubishi Denki Kabushiki Kaisha Halbleiterspeicheranordnung

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130286A (en) * 1981-02-06 1982-08-12 Fujitsu Ltd Static semiconductor memory
US4791613A (en) * 1983-09-21 1988-12-13 Inmos Corporation Bit line and column circuitry used in a semiconductor memory
GB2160046B (en) * 1984-04-20 1987-12-23 Hitachi Ltd Semiconductor memory device
US4730279A (en) * 1985-03-30 1988-03-08 Kabushiki Kaisha Toshiba Static semiconductor memory device
US4636991A (en) * 1985-08-16 1987-01-13 Motorola, Inc. Summation of address transition signals
US4621315A (en) * 1985-09-03 1986-11-04 Motorola, Inc. Recirculating MOS charge pump

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0139385A2 (de) * 1983-09-14 1985-05-02 Mitsubishi Denki Kabushiki Kaisha Halbleiterspeicheranordnung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
THIRD CALTECH CONFERENCE ON VERY LARGE SCALE INTEGRATION, 21st-23rd March 1983, Pasadena, CA., edited by Randal Bryant, pages 275-285, Rockville, MD., US; E.H.FRANK et al.: "A self-timed static RAM" *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0394652A2 (de) * 1989-04-21 1990-10-31 Motorola, Inc. Speicher, der verteiltes Laden von Datenleitungen verwendet
EP0394652A3 (de) * 1989-04-21 1993-01-07 Motorola, Inc. Speicher, der verteiltes Laden von Datenleitungen verwendet
EP0498336A1 (de) * 1991-02-07 1992-08-12 Texas Instruments Incorporated Verbindung mit gemeinsamer Leitung für ein integriertes Speicher-Array

Also Published As

Publication number Publication date
KR880000969A (ko) 1988-03-30
EP0251734B1 (de) 1992-09-09
EP0251734A3 (en) 1989-07-12
DE3781607D1 (de) 1992-10-15
JPS639097A (ja) 1988-01-14
US5034924A (en) 1991-07-23
DE3781607T2 (de) 1993-03-25

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