EP0244991A2 - Schaltung mit veränderlicher Verzögerung - Google Patents

Schaltung mit veränderlicher Verzögerung Download PDF

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Publication number
EP0244991A2
EP0244991A2 EP87303608A EP87303608A EP0244991A2 EP 0244991 A2 EP0244991 A2 EP 0244991A2 EP 87303608 A EP87303608 A EP 87303608A EP 87303608 A EP87303608 A EP 87303608A EP 0244991 A2 EP0244991 A2 EP 0244991A2
Authority
EP
European Patent Office
Prior art keywords
data
signal
unit
delay
time delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP87303608A
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English (en)
French (fr)
Other versions
EP0244991A3 (de
Inventor
Richard James Humpleman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AMT Holdings Ltd
Original Assignee
Active Memory Technology Ltd
AMT Holdings Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Active Memory Technology Ltd, AMT Holdings Ltd filed Critical Active Memory Technology Ltd
Publication of EP0244991A2 publication Critical patent/EP0244991A2/de
Publication of EP0244991A3 publication Critical patent/EP0244991A3/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players

Definitions

  • This invention relates to variable delay circuits.
  • the invention is particularly, although no exclusively, concerned with a delay circuit for use in a data processing system comprising a processing unit and a display terminal remote from the processing unit.
  • the display terminal normally produces synchronisation signals for controlling the scanning of the display. It has been proposed to use these synchronisation signals to generate request signals, which are sent to the processing unit requesting it to supply video data to the terminal.
  • request signals which are sent to the processing unit requesting it to supply video data to the terminal.
  • a problem arises in that, when the data arrives at the display terminal, it will not be in the correct timing relationship with the synchronisation signals: it will be delayed relative to the synchronisation signals by an amount which depends on the transmission delay between the display terminal and the processing unit. This delay will be unknown, and will vary if the connections between the display terminal and processing unit are altered.
  • One object of the present invention is to provide a variable delay circuit which can used to overcome this problem.
  • variable delay circuit comprising a variable delay line, characterised by means (30,31) for measuring the time delay between two control signals (QUAL3, ENTER5+), and means for automatically setting the delay of the delay line (31,32) to a value corresponding to the measured delay.
  • the two control signals may be, for example, a request signal from a display terminal, requesting a processing unit to supply video data, and a data qualifier signal which is returned to the display terminal along with the requested data, and the delay circuit may be used to delay a synchronisation signal in the display terminal.
  • the delay circuit can be arranged to automatically adapt itself to compensate for delays between the display terminal and the processing unit, so as to ensure that the synchronisation signal is correctly aligned with the data.
  • Figure 1 shows a data processing system comprising a display terminal 10 and a data processing unit 11 interconnected by an interface 12.
  • the distance between the terminal 10 and processing unit 11 may be typically of the order of 10 metres.
  • the display terminal 10 includes a video monitor 13 having a conventional raster-scanned display.
  • the display terminal has a video timing generator 14 for producing the conventional synchronisation signals for the monitor, including a horizontal synchronisation signal HSYNC, a vertical synchronisation signal VSYNC, and a blanking signal BLANK. Normally, the synchronisation signals would be applied directly to the monitor, but in the present system they are delayed, as will be described below.
  • Both the monitor 13 and the video timing generator 14 may be conventional units and will not be described in any further detail.
  • the video monitor 13 and the video timing generator 14 are both controlled by a clock signal CLK from a clock generation circuit 15.
  • This clock has a frequency equal to the pixel (picture element) rate of the monitor.
  • the display terminal also includes a request generation circuit 17, which receives the request clock RCLK, the vertical synchronisation signal YSYNC, and the blanking signal BLANK. Wherever the signal VSYNC occurs, indicating the start of a frame, the circuit 17 produces a series of request signals QUAL, one for each request clock RCLK for which BLANK is false. Each of these request signals QUAL requests the processing unit 11 to supply a word of video data.
  • the number of QUAL signals produced after each VSYNC is a present number, equal to the number of video data words required to make up a frame.
  • the request signal QUAL is transmitted over the interface 12, along with the request clock RCLK, to the processing unit 11.
  • the processing unit receives a request signal QUAL, it outputs a word of video data, in synchronisation with the received request clock RCLK, and transmits it back to the display terminal 10, along with a data qualifier QUALD which indicates the presence of a data word.
  • the data processing unit 11 also returns the clock signal RCLK to the display terminal along with the data, as a data clock signal DCLK, to which the data is synchronised.
  • the display Terminal 10 When the data is received by the display Terminal 10, it is clocked through two registers 18,19 by the data clock DCLK.
  • the output of the register 19 is fed to a parallel-to-serial converter 20, which converts each 32-bit data word into a series of groups of 32/R bits, at the pixel clock rate, each group representing one pixel of the display.
  • the output of the converter 20 is then fed to the video monitor 13 where it is converted to analog form to provide the video input signal for the monitor.
  • the data input to the monitor 13 is delayed, relative to the original VSYNC signal that produced the request for the data, by five beats of the clock signal RCLK, plus the unknown delay in travelling around the loop from the display terminal to the processing unit and back again. (These five clock beat delays occur respectively in the request generator 17, the processing unit 11, the register 18, the register 19, and the parallel-to-serial converter 20).
  • the synchronization signals HSYNC and VSYNC will not be in the correct timing relationship with the data, and must be delayed by the same amount (5 clock beats plus the loop delay) before being applied to the monitor. The way in which this is done will now be described.
  • the synchronisation signals HSYNC and VSYNC are clocked through a pipeline comprising two registers 21,22 by the request clock signal RCLK. These signals pass through the pipeline twice as shown, to that they emerge four beats later as signals HSYNC4 and VSYNC4. At the same time, the request signal QUAL is clocked once through the pipeline registers 21,22, to emerge two beats later as signal QUAL 3. (The "3" indicates that this signal occurs three clock beats after the original VSYNC signal, including one clock beat delay in the request generator 17).
  • the first data qualifier QUALD returning from the processing unit to the display terminal is clocked into a register 23 by the data clock DCLK and is latched there by a feedback connection. This produces a signal ENTER 3+ which remains true until the register 23 is reset by a RESET signal.
  • the "3+” indicates that this signal is delayed relative to the original VSYNC signal by three clock beats (in the request generator 17, the processing unit 11, and the register 23) plus the unknown loop delay in travelling from the display terminal 10 to the processing unit 11 and back again.
  • the signal ENTER 3+ is clocked through the pipeline registers 21,22 to emerge two clock beats later as a signal ENTER 5+. This resynchronises this signal to the clock RCLK, eliminating any fraction of a clock beat delay between QUAL 3 and ENTER 5+.
  • the signals QUAL 3 and ENTER 5+ are applied to a delay circuit 24, which measures the time delay between these signals in terms of number of beats of the clock RCLK.
  • the delay circuit 24 also receives signals HSYNC4 and VSYNC4 and delays them by an amount one clock beat less than the measured delay between QUAL 3 and ENTER 5+, to produce output synchronisation signals HSYNCOUT and VSYNCOUT for the monitor 13. It can be seen that HSYNCOUT and VSYNCOUT are therefore delayed, relative to the original VSYNC signal, by five beats of RCLK, plus the loop delay in travelling between the display terminal and the processing unit and back again (ignoring any fraction of a clock beat). In other words, these signals HSYNCOUT and VSYNCOUT are delayed by the same number of whole clock beats as the data applied to the video monitor 13.
  • the delay circuit 24 will now be described in more detail with reference to Figure 2.
  • the delay circuit 24 comprises a three-bit binary counter 30 which produces an output signal SQ.
  • the delay circuit 24 also includes a shift register 32 which receives the signal VSYNC4 at its serial data input and is controlled by the clock signal RCLK. Thus, the signal VSYNC4 is shifted through successive stages of the shift register at successive beats of RCLK.
  • the outputs of the stages of the register 32 are connected to respective inputs of the multiplexer 31. The output of the multiplexer 31 provides the signal VSYNCOUT.
  • the delay circuit 24 therefore operates as follows.
  • ENCOUNT will stay true, and hence the counter continues to step forward one state at each clock beat, until ENTER 5+ goes true.
  • the counter 30 is then disabled, and hence is frozen in its current state.
  • QUAL 3 triggers the counter 30 to start counting, and the counter will then count up one at each successive clock beat until ENTER 5+ arrives, whereupon it is frozen.
  • VSYNCOUT is delayed relative to VSYNC4 by one clock beat less than the measured delay between QUAL 3 and ENTER 5+.
  • the delay circuit 24 also includes similar circuits (not shown) for delaying the signal HSYNC4 by the same amount to produce HSYNCOUT.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
EP87303608A 1986-05-03 1987-04-24 Schaltung mit veränderlicher Verzögerung Withdrawn EP0244991A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB868610888A GB8610888D0 (en) 1986-05-03 1986-05-03 Variable delay circuit
GB8610888 1986-05-03

Publications (2)

Publication Number Publication Date
EP0244991A2 true EP0244991A2 (de) 1987-11-11
EP0244991A3 EP0244991A3 (de) 1989-10-18

Family

ID=10597319

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87303608A Withdrawn EP0244991A3 (de) 1986-05-03 1987-04-24 Schaltung mit veränderlicher Verzögerung

Country Status (2)

Country Link
EP (1) EP0244991A3 (de)
GB (1) GB8610888D0 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11744342B2 (en) 2016-05-13 2023-09-05 L'oreal Device for treating the hair, and related method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3887769A (en) * 1973-04-04 1975-06-03 Bell Telephone Labor Inc Frame syncrhonization of elastic data bit stores
JPS5630369A (en) * 1979-08-20 1981-03-26 Toshiba Corp Audio signal delay compensator
GB2073515A (en) * 1980-04-04 1981-10-14 Int Standard Electric Corp Frequency locked loop
GB2128450A (en) * 1982-10-04 1984-04-26 Hitachi Ltd Time-division switching unit
JPS59216334A (ja) * 1983-05-24 1984-12-06 Nippon Telegr & Teleph Corp <Ntt> 複局制御信号タイミング調整方式
EP0175564A2 (de) * 1984-09-21 1986-03-26 Amt(Holdings) Limited Datenübertragungssystem
EP0180450A2 (de) * 1984-10-31 1986-05-07 Rca Licensing Corporation Fernsehanzeigeanordnung umfassend einen Zeichengenerator mit einem nicht mit der Zeilenfrequenz synchronisierten Taktgeber

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3887769A (en) * 1973-04-04 1975-06-03 Bell Telephone Labor Inc Frame syncrhonization of elastic data bit stores
JPS5630369A (en) * 1979-08-20 1981-03-26 Toshiba Corp Audio signal delay compensator
GB2073515A (en) * 1980-04-04 1981-10-14 Int Standard Electric Corp Frequency locked loop
GB2128450A (en) * 1982-10-04 1984-04-26 Hitachi Ltd Time-division switching unit
JPS59216334A (ja) * 1983-05-24 1984-12-06 Nippon Telegr & Teleph Corp <Ntt> 複局制御信号タイミング調整方式
EP0175564A2 (de) * 1984-09-21 1986-03-26 Amt(Holdings) Limited Datenübertragungssystem
EP0180450A2 (de) * 1984-10-31 1986-05-07 Rca Licensing Corporation Fernsehanzeigeanordnung umfassend einen Zeichengenerator mit einem nicht mit der Zeilenfrequenz synchronisierten Taktgeber

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 5, no. 82 (E-59)(754) 29 May 1981; & JP-A-56 030 369 (TOKYO SHIBAURA DENKI K.K.) 26.03.1981 *
PATENT ABSTRACTS OF JAPAN vol. 9, no. 85 (E-308)(1808) 13 April 1985; & JP-A-59 216 334 (NIPPON DENSHIN DENWA KOSHA) 06.12.1984 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11744342B2 (en) 2016-05-13 2023-09-05 L'oreal Device for treating the hair, and related method

Also Published As

Publication number Publication date
EP0244991A3 (de) 1989-10-18
GB8610888D0 (en) 1986-06-11

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