EP0203357B1 - Apparatus for substituting a memory in a motor vehicle control system - Google Patents

Description

State of the art

The invention relates to a device in an electrical control device according to the preamble of the main claim.

From the publication "Bosch Technical Reports" Volume 5 (1977), No. 5/6, page 253, it is known to provide a computer in electronic ignition systems that processes engine speed, engine load and various switching signals as input signals. The computer determines, for example, ignition timing, current flow time and speed thresholds. Motor vehicle-specific data are stored in a special, once programmable memory (so-called PROM memory), which is queried by the computer.

Furthermore, it is generally known to use integrated circuits in special contact sockets provided for the physical implementation of such computers, so that e.g. The replacement of an initially erasable memory (so-called EPROM memory) with a non-erasable PROM memory is easily possible as soon as e.g. a data record in the erasable EPROM memory has been shown to be useful for a final determination in a non-erasable PROM memory, or that a certain PROM memory can still be replaced afterwards, be it because of a defect or because of the desire to change a previously defined one Record.

It is also known to produce corresponding computer arrangements using so-called hybrid technology, in which unpackaged IC chips are applied to a ceramic-like substrate material and connection connections with e.g. conductor tracks produced in thick film technology can be produced on the substrate material by means of bond wires. Such designs - called hybrid circuits - allow a small design, high mechanical strength due to low inertial forces, and high long-term reliability due to the lack of susceptible plug contacts. Such hybrid circuits are therefore increasingly being used not only in control devices for aircraft, but also in those for motor vehicles, since in the latter there are very large temperature fluctuations and high mechanical stresses - e.g. under vibration - occur and can be mastered.

The disadvantage is that when processing such unpacked PROM IC chips, the programming can only take place when the chips are completely assembled and connected. This means that error-free or faulty programming can only be determined as a hybrid circuit after the completion of a corresponding computer. Since it is not economical or not possible at all to replace faulty chips, the entire hybrid circuit becomes a waste if there is a fault on a PROM chip as a data carrier.

DE-A-32 00 626 describes a method for checking whether a memory which is not the main memory is inserted into a microcomputer system, the check being carried out by means of the internal microcomputer system itself. An auxiliary memory is provided as an insertable memory, which contains some changes to the stored contents of the main memory. This method does not provide for the main memory to be replaced by the auxiliary memory in all its functions. The check itself as well as the activation of the auxiliary memory and the corresponding deactivation of the main memory is carried out exclusively on a software basis.

In US-A-3 753 242 a system is described with a main memory which has several individually addressable segments. Another memory corresponds in its addressing to a segment of the main memory. Access to either the additional memory or the corresponding segment of the main memory can be controlled via control memory by storing access instructions to the addresses of the additional memory or the corresponding segment of the main memory. There is also the option of activating or overriding the additional memory using switches. It is not intended to completely replace the main memory by means of a further memory. Only one segment of the main memory, the addressing of which corresponds to the addressing of the further memory, is switched inactive.

Advantages of the invention

The invention has for its object to provide a device which makes it possible in a simple manner to reduce the rejection of corresponding computer circuits designed in chip form due to errors or incorrect programming of PROM chips. In addition, a possibility is to be created, if necessary, of subsequently exchanging data records even if they were originally stored in a hybrid-processed PROM memory without, for example, a highly integrated hybrid circuit, which in addition to such a computer can also contain a large number of other function blocks, must be replaced and discarded.

This object is achieved by a device with the features of the main claim.

The invention has the advantage that a PROM memory that is faulty or loaded with data that is no longer up-to-date and mounted as a chip in a hybrid circuit can be shut down in a simple manner and its function can be taken over by an upgradable PROM memory in a conventional housing packaging. For this purpose, the hybrid circuit, or a printed circuit board connected to the hybrid circuit, has a base for accommodating such a conventional PROM memory and further components in order to unambiguously assign the activated one PROM memory and the computer to enable. As a result, a corresponding computer can be integrated together with other function modules in one and the same hybrid circuit, and these can be produced inexpensively using commercially available PROM memory chips, with rejects due to defective PROM chips being avoided. In addition, each hybrid circuit can be subsequently provided with a new data record by adding a correspondingly programmed and tested PROM or ROM memory in a conventional version.

drawing

In the single figure of the drawing, an embodiment of the invention is illustrated in a schematic block diagram, which is explained in more detail below.

Description of the embodiment

The address outputs 2 of a microcomputer 1 are connected via decoupling resistors 3 to the address inputs 4 of a PROM memory 5 in chip form. Analogously, data inputs 6 of the microcomputer 1 are connected to data outputs 7 of the PROM memory 5 in chip form. At the same time, the address outputs 2 of the microcomputer 1 are connected to connections 8 of a plug socket 9, which can be connected to address inputs of a similar PROM memory 16, which is packaged conventionally as a discrete semiconductor component and can be inserted into this plug socket. Analogously, the data inputs 6 of the microcomputer 1 are connected to connections 10 of the plug-in base 9, which can be connected to data outputs of the PROM memory 16, which is of a conventional design and can be inserted into the plug-in base 9. Wiring the connection 11 of the PROM memory 5 in chip form with a high or low potential allows the activation or deactivation of the PROM memory 5 in chip form. For this purpose, the connection 11 is connected on the one hand via a resistor 13 to a supply voltage terminal 14, and on the other hand via a disconnectable bridge 12 with ground potential 15. The corresponding connection 17 of the plug base 9, via which the conventional PROM memory 16 can be activated or deactivated, is, for example, permanently connected to ground potential 15 in order to activate a conventional PROM memory 16 inserted in the plug base 9.

In the normal case, the microcomputer 1 corresponds to the PROM memory 5 in chip form, as long as the separable bridge 12 is closed and thus the connection 11 of the PROM memory 5 in chip form is connected to ground potential. In this case, plug socket 9 is not equipped with a PROM memory in a conventional design. The resistance values of the decoupling resistors 3 are dimensioned such that, on the one hand, no inadmissible falsifications of logic signal levels can occur at the address inputs 4 of the PROM memory 5 in chip form, and that, on the other hand, when the PROM memory 5 in chip form is shut down, there is no undue burden on the corresponding address inputs of the in the socket 9 used PROM memory 16 occurs in a conventional design. To start up such a PROM memory 16 inserted into the plug-in base 9, it is only necessary to disconnect the separable bridge 12 so that the connection 11 of the PROM memory 5 in chip form is then connected to the supply voltage terminal potential 14 via the resistor 13 with the effect that that the PROM memory 5 in chip form on address signals at its address inputs 4 no longer outputs data signals at its data outputs 7. The PROM memory 16 inserted into the plug base 9 is activated by connecting the corresponding connection of the PROM memory 16 inserted into the plug base 9 in a conventional design by means of a fixed connection of the corresponding connection 17 of the plug base 9 to ground potential. In this way, the PROM memory 16 in a conventional design can be addressed by the microcomputer 1 in chip form without disruptive effects from the shutdown PROM memory 5.

Claims (4)

1. Device containing in an electronic control unit of a motor vehicle a first data memory (5) which is permanently applied to a component carrier in chip form and which is connected via address and data lines to a microcomputer (1), with a spare socket (9) for accommodating a second data memory (16) which can be retrofitted and which can be activated by being fitted into the spare socket (9), further containing the second data memory, characterized in that terminals (8, 10) of the spare socket (9) are connected to all address and data lines via which the first data memory (5) is connected to the remaining microcomputer (1), that the first data memory (5) can be replaced in all its functions by the second data memory (16) and that the deactivation of the permanently installed data memory (5) is effected by means of a disconnectible current path (12) after the second data memory (16) has been fitted into the spare socket (9).

2. Device according to Claim 1, characterized in that the component carrier is a hybrid board.

3. Device according to Claim 1 or 2, characterized in that ROMs or PROMs are provided as replacement memories (16) which can be retrofitted.

4. Device according to one of the preceding claims, characterized in that the address inputs (4) of the first data memory (5), which is fitted as chip, are connected via decoupling resistors (3) having essentially identical resistance values to the address outputs (2) of the microcomputer (1), that at least one input (11) of the first data memory (5) fitted as chip is connected by opening a current path in the construction of a disconnectible link (12) to a logic potential which results in a deactivation of the first data memory (5), and that the terminal (17) of the socket (9), which can be connected at least to one corresponding input of the second data memory (16) which can be inserted into the plug-in socket (9), is permanently connected to a complementary logic potential.

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