EP0195202A2 - Mécanisme de sélection de registre et organisation d'un tampon de prélecture - Google Patents
Mécanisme de sélection de registre et organisation d'un tampon de prélecture Download PDFInfo
- Publication number
- EP0195202A2 EP0195202A2 EP86101088A EP86101088A EP0195202A2 EP 0195202 A2 EP0195202 A2 EP 0195202A2 EP 86101088 A EP86101088 A EP 86101088A EP 86101088 A EP86101088 A EP 86101088A EP 0195202 A2 EP0195202 A2 EP 0195202A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- array
- bit
- instruction
- address
- prefetch buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000872 buffer Substances 0.000 title claims abstract description 22
- 230000008520 organization Effects 0.000 title description 4
- 239000000203 mixture Substances 0.000 claims 1
- 238000003491 array Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3816—Instruction alignment, e.g. cache line crossing
Definitions
- the subject invention is related to instruction prefetch buffers for microprocessors and, more particularly, to a register selection meachnism which enables instruction access on instruction boundaries when used with a microprocessor that operates with variable length instructions.
- IC microprocessors are of course well known in the art These devices have been developed over the past decade from the relatively simple to the very complex. Early examples were limited to 4-bit devices while currently 32-bit devices are being introduced by various manufactures. Along with an increase in scale, there has been a correspodning increase in sophistication of design to permit greater fiexibility in programming.
- a microprocessor has been developed which operates with variable length instructions. These instructions may be either 32 bits in length or 16 bits in length. It is necessary in order to properly decode the operation codes and operands of the instruction fields that they be accessed on their boundaries.
- the instruction prefetch buffer comprises four registers.
- the instruction prefetch buffer according to the present invention is organized as a one-port-write, two-port-read memory array- Means are responsive to a read pointer for controlling access to odd and even addresses in an array of the buffer.
- Address generation means are responsive to the control means for generating addresses for accessing the array.
- the instruction prefetch buffer is implemented as a 32-bit one-port-write and 16-bit two-port-read array 10. More specifically, the array 10 comprises an even array 101, referred to herein as the A array, and an odd array 102, referred to herein as the B array. Associated with the A array 101 is an address decoding network 103. A corresponding address decoding network 104 is assoaated with the B array 102. The A array 101 is addressed with even address values, while the B array 102 is addressed with odd address values. Each array 101 and 102 is shown as capable of storing 16 half words (16 bits) for a total of 32 half words but those skilled in the art will understand that this is but one specific example. The principles of the invention are equally applicable to larger or smaller arrays and could be extended to byte fields (8 bits) and double word fields (64 bits).
- instruction I 0 is a 32-bit instruction beginning at an even address in the A array 101 and continuing over to an odd address in the B array 102.
- Instruction I 1 is another 32-bit instruction, but this instruction begins at an odd address in the B array 102 and continues to an even address in the A array 101.
- Instruction I 2 is an example of a 16-bit instruction which begins at an odd address and is totally contained in the B array 102, while instruction I 3 is another 16-bit instruction which begins at an even address and is totally contained in the A array 101.
- Fig. 1A shows examples of instruction formats which may be used. In each of these formats, the first eight bits or byte contains the operation code.
- the next four bits of the top two formats specifies a register denoted here as the X register, while the following four bits specifies a register denoted here as the Y register. That is the total content of the second format shown in Fig. 1A, this format being an example of a 16-bit or half word instruction.
- the first format is a 32-bit or word instruction and contains a 16- bit operand address, here denoted as "immediate”.
- Two other examples of 32-bit or word instructions are also shown in Fig. 1A. In one of these there is 24-bit branch address, while in the other a 20-bit branch immediate field address follows a 4-bit register number.
- a 32-bit write bus 12 from main memory is split into two 16-bit buses 121 and 122 in the array 10 with bus 121 supplying the A array 101 with the first two bytes of the word fetched from the memory to be written in that array and bus 122 supplying the B array 102 with the second two bytes of the same word to be written in that array.
- Register 14 temporarily stores the write pointer W which points to the 32-bit location where a new word is to be written.
- the 32-bit location is obtained by combining both 16-bit registers A and B from the array 10 and addressing them as one 32-bit register.
- write address W o addresses the A array address A c and the B array address B, and so forth. Therefore, the W pointer is only four bits long.
- Register 15 temporarily stores the read pointer R which points to the 32-bit location from where the instruction is to be read.
- the 5-bit R pointer is supplied to the address generation and control logic 1 6. This logic generates the 4- bit addresses for each of the arrays 101. Specifically, the 4- bit A address is supplied to the A decoder 1 03 and the 4- bit B address is supplied to the B decoder 104.
- the output of the A array 101 is supplied via a first 16-bit output bus 105 to port A, and the output of the B array 102 is supplied via a second 16-bit output bus 106 to port B.
- the beginning of the instruction has always to be read from the multiplexer 22 whether the instruction is a 1 6- bit instruction or a 32-bit instruction. Also, to access a 32- bit instruction from the array, both sides of the array, odd and even, have to be addressed and data brought to ports A and B. But as already described, a 16-bit portion containing the beginning of the instruction may be either in the A array 101 or the B array 102; i.e., 32-bit instructions can start in either array. Therefore, multiplexers 22 and 24 are provided to read the instructions out of the array 10 in the proper order.
- each multiplexer 22 and 2 4 are each connected to the 16-bit ports A and B of the array 10 but in the opposite order from each other.
- the 16-bit outputs of the multiplexers 22 and 24 are combined to provide a 32-bit instruction output In the case of a 16-bit instruction, the high order 16 bits comprise a null field and are simply disregarded.
- the address generation and control logic 16 is shown in more detail in Fig. 2.
- the four most significant bits - (MSB) of the R pointer register 15 are first of all supplied to opposite inputs of multiplexers 161 and 162.
- MSB most significant bits -
- all five bits of the R pointer register 15 are supplied to an incrementer 163 which adds one to the R pointer.
- the four MSB from the incrementer are then supplied to the remaining inputs of the multiplexers 1 61 and 162.
- the least significant bit (LSB) R o of the R pointer is used to control multiplexers 161 and 162.
- the outputs of these multiplexers are the A and B addresses, respectively.
- equality checkers 164 165 each receive the four bits from register 14.
- Equality checker 16 4 in addition receives the four MSBs from register 1 5, while equality checker 165 receives the four MSBs from incrementer 163.
- the equality checkers may be implemented with exclusive OR gates and a NOR gate.
- the output of equality checker 165 is supplied to one input of AND gate 166 the second input of which is enabled whenever the instruction length is four bytes long; i.e., a 32-bit instruction as opposed to a 16-bit instruction for the specific example being described.
- the output of AND gate 166 and the output of equality checker 165 are connected to the inputs of OR gate 167 which provides an output indicating that the instruction prefetch buffer is empty.
- the disclosed implementation does not require an array having special features.
- the array 10 can be implemented using two general purpose arrays containing 16 registers each of a microprocessor by organizing them as an array having one 32-bit write port and two 16-bit read ports.
- the specific sizes of the arrays and the registers within the arrays may be varied depending on the application. For example, it is altogether possible to provide an array of byte registers with four or even eight subarrays of such byte registers.
- the addressing of such an arrangement, while complex, is a straight forward application of the principles of the invention as described by way of specific example. Output multiplexers in such a case could be part of the subarray decoders all organized into the one array decoder.
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US71321785A | 1985-03-18 | 1985-03-18 | |
US713217 | 1991-06-11 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0195202A2 true EP0195202A2 (fr) | 1986-09-24 |
EP0195202A3 EP0195202A3 (en) | 1988-07-27 |
EP0195202B1 EP0195202B1 (fr) | 1991-12-11 |
Family
ID=24865257
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19860101088 Expired EP0195202B1 (fr) | 1985-03-18 | 1986-01-28 | Mécanisme de sélection de registre et organisation d'un tampon de prélecture |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0195202B1 (fr) |
JP (1) | JPS61214029A (fr) |
CA (1) | CA1233270A (fr) |
DE (1) | DE3682792D1 (fr) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0299526A2 (fr) * | 1987-07-15 | 1989-01-18 | Nec Corporation | File d'attente à grande longueur de mot |
EP0363222A2 (fr) * | 1988-10-07 | 1990-04-11 | Hewlett-Packard Company | Méthode et dispositif de distribution simultanée d'instructions à plusieurs unités fonctionnelles |
EP0436341A2 (fr) * | 1990-01-02 | 1991-07-10 | Motorola, Inc. | Méthode de préextraction séquentielle pour instructions à un, deux ou trois mots |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0769800B2 (ja) * | 1989-02-07 | 1995-07-31 | 松下電器産業株式会社 | データ処理装置 |
DE69032897T2 (de) * | 1989-08-28 | 1999-08-26 | Nec Corp | Mikroprozessor zum verbesserten Startvorgang der Befehlsausführung nach der Ausführung eines bedingten Verzweigungsbefehls |
JP2682761B2 (ja) * | 1991-06-18 | 1997-11-26 | 松下電器産業株式会社 | 命令プリフェッチ装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2298139A1 (fr) * | 1975-01-16 | 1976-08-13 | Int Computers Ltd | Dispositif de recherche et d'execution des instructions dans un process |
US4236206A (en) * | 1978-10-25 | 1980-11-25 | Digital Equipment Corporation | Central processor unit for executing instructions of variable length |
GB2117945A (en) * | 1982-04-01 | 1983-10-19 | Raytheon Co | Memory data transfer |
US4502111A (en) * | 1981-05-29 | 1985-02-26 | Harris Corporation | Token generator |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5836434B2 (ja) * | 1975-12-10 | 1983-08-09 | 株式会社日立製作所 | バツフアメモリソウチ |
JPS5344130A (en) * | 1976-10-05 | 1978-04-20 | Toshiba Corp | Floating access memory device |
JPS54122040A (en) * | 1978-03-15 | 1979-09-21 | Toshiba Corp | Electronic computer |
-
1985
- 1985-09-10 CA CA000490347A patent/CA1233270A/fr not_active Expired
- 1985-12-27 JP JP29341485A patent/JPS61214029A/ja active Pending
-
1986
- 1986-01-28 DE DE8686101088T patent/DE3682792D1/de not_active Expired - Fee Related
- 1986-01-28 EP EP19860101088 patent/EP0195202B1/fr not_active Expired
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2298139A1 (fr) * | 1975-01-16 | 1976-08-13 | Int Computers Ltd | Dispositif de recherche et d'execution des instructions dans un process |
US4236206A (en) * | 1978-10-25 | 1980-11-25 | Digital Equipment Corporation | Central processor unit for executing instructions of variable length |
US4502111A (en) * | 1981-05-29 | 1985-02-26 | Harris Corporation | Token generator |
GB2117945A (en) * | 1982-04-01 | 1983-10-19 | Raytheon Co | Memory data transfer |
Non-Patent Citations (3)
Title |
---|
DATA REPORT, vol. 4, no. 1, 1976, pages 15-17, Munich, DE; H. BERNDT: "Instruction prefetch of the 7.755 central processor" * |
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 23, no. 2, July 1980, pages 670-672, New York, US; T.J. BLAZEJEWSKI et al.: "Instruction buffer with simultaneous store and fetch operations" * |
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 24, no. 3, August 1981, pages 1401-1403, New York, US; F.T. BLOUNT et al.: "Shared instruction buffer for multiple instruction streams" * |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0299526A2 (fr) * | 1987-07-15 | 1989-01-18 | Nec Corporation | File d'attente à grande longueur de mot |
EP0299526A3 (fr) * | 1987-07-15 | 1991-01-09 | Nec Corporation | File d'attente à grande longueur de mot |
EP0363222A2 (fr) * | 1988-10-07 | 1990-04-11 | Hewlett-Packard Company | Méthode et dispositif de distribution simultanée d'instructions à plusieurs unités fonctionnelles |
EP0363222A3 (fr) * | 1988-10-07 | 1992-07-01 | Hewlett-Packard Company | Méthode et dispositif de distribution simultanée d'instructions à plusieurs unités fonctionnelles |
EP0436341A2 (fr) * | 1990-01-02 | 1991-07-10 | Motorola, Inc. | Méthode de préextraction séquentielle pour instructions à un, deux ou trois mots |
EP0436341A3 (en) * | 1990-01-02 | 1993-03-17 | Motorola Inc. | Sequential prefetch method for 1, 2 or 3 word instructions |
Also Published As
Publication number | Publication date |
---|---|
EP0195202B1 (fr) | 1991-12-11 |
DE3682792D1 (de) | 1992-01-23 |
CA1233270A (fr) | 1988-02-23 |
JPS61214029A (ja) | 1986-09-22 |
EP0195202A3 (en) | 1988-07-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4847759A (en) | Register selection mechanism and organization of an instruction prefetch buffer | |
US4363091A (en) | Extended address, single and multiple bit microprocessor | |
US5832288A (en) | Element-select mechanism for a vector processor | |
US5907865A (en) | Method and data processing system for dynamically accessing both big-endian and little-endian storage schemes | |
EP0138419B1 (fr) | Processeur central pour un ordinateur | |
KR950012116B1 (ko) | 명령버퍼장치 | |
US5371864A (en) | Apparatus for concurrent multiple instruction decode in variable length instruction set computer | |
US5255378A (en) | Method of transferring burst data in a microprocessor | |
US4654781A (en) | Byte addressable memory for variable length instructions and data | |
US5131083A (en) | Method of transferring burst data in a microprocessor | |
US5761478A (en) | Programmable memory interface for efficient transfer of different size data | |
US4272828A (en) | Arithmetic logic apparatus for a data processing system | |
US4037213A (en) | Data processor using a four section instruction format for control of multi-operation functions by a single instruction | |
US7865699B2 (en) | Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code | |
US5581774A (en) | Data processor decoding and executing a train of instructions of variable length at increased speed | |
US5117488A (en) | Microprogram controlled microprocessor having a selectively expandable instruction code length including independent description of operand addressing and a type of operation for an operand by single instruction in a common coding scheme | |
US5357620A (en) | Bit addressing system | |
US6263420B1 (en) | Digital signal processor particularly suited for decoding digital audio | |
KR100971626B1 (ko) | 다수의 명령어 세트를 갖는 데이터 처리 장치 내에서의명령어 부호화 | |
US4347566A (en) | Data processor with register file and arithmetic logic circuit on one chip and register means directly connected to the chip | |
US5390311A (en) | Method and apparatus for accessing microcoded instructions in a computer system | |
EP0195202A2 (fr) | Mécanisme de sélection de registre et organisation d'un tampon de prélecture | |
US6408320B1 (en) | Instruction set architecture with versatile adder carry control | |
US4893235A (en) | Central processing unit for a digital computer | |
US5860076A (en) | 48-bit wide memory architecture addressing scheme reconfigurable for 8-bit, 16-bit and 32-bit data accesses |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB IT |
|
17P | Request for examination filed |
Effective date: 19870116 |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): DE FR GB IT |
|
17Q | First examination report despatched |
Effective date: 19900528 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB IT |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRE;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.SCRIBED TIME-LIMIT Effective date: 19911211 |
|
ET | Fr: translation filed | ||
REF | Corresponds to: |
Ref document number: 3682792 Country of ref document: DE Date of ref document: 19920123 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed | ||
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 19921222 Year of fee payment: 8 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 19921223 Year of fee payment: 8 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 19930127 Year of fee payment: 8 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Effective date: 19940128 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 19940128 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Effective date: 19940930 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Effective date: 19941001 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST |