Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04Q—SELECTING
  • H04Q11/00—Selecting arrangements for multiplex systems
  • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L12/40—Bus networks
  • H04L12/407—Bus networks with decentralised control
  • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
  • H04L12/4135—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD] using bit-wise arbitration
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L12/40—Bus networks
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04Q—SELECTING
  • H04Q11/00—Selecting arrangements for multiplex systems
  • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
  • H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04Q—SELECTING
  • H04Q11/00—Selecting arrangements for multiplex systems
  • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
  • H04Q11/08—Time only switching

Definitions

• the present invention relates to a private branch exchange (PBX) in the field of digital telephony and, more particularly, to a timeslot bus and a signaling bus in a digital PBX switch capable of carrying, voice and data signals.
• PBX private branch exchange
• PBXs are increasingly being used in present day telephone systems.
• a PBX system ties together the telephones of an office, building or factory.
• Teen within the PBX system can talk to someone else within the system without the cost and time of using outside lines and facilities.
• PBX systems are becoming digital.
• the analog voice signals of a caller are converted into a digital representation.
• These digital signals are transmitted through the PBX system.
• PBX systems are increasingly used to transport computer data signals. This is due, in part, to the a ' vailability of personal computers in the home and office.
• the heart of the system the PBX switch as shown in Fig. 1, connects callers within the system, connects callers to outside lines if a call outside the PBX system is desired, and connects outside callers to lines within the system.
• a PBX switch generally has a number of modules or "line cards.” Each line card is connected to a number of telephones or “terminals” and the line cards are connected to each other by a set of lines called a "bus", or sometimes, the "backplane bus.”
• the bus such as bus 10 in Fig. 1, has a timeslot bus.
• the timeslot bus carries the digital signals of a voice or the data of a computer, for example.
• the voice signals are sampled at some rate, typically 8000 times per second (8 KHz) , and the resulting voltage samples are converted into a digital representation, typically 8-bit " ⁇ -law” or "A-law” encoding.
• the resulting sequence of bits (8000 times 8, or 64K bits/sec) is called the Pulse Code Modulation (PCM) representation of the original voice signal.
• PCM Pulse Code Modulation
• the digital PBX transports and switches the PCM signals from place to place within the PBX system. Eventually, the PCM signals are converted back into an analog voice signal for a person to hear.
• the PCM signals are carried on the bus 10 on which the signals are carried during particular time intervals, or timeslots.
• Each timeslot can carry the PCM 64K bit/second stream of data so that typically one timeslot is required for each incoming or outgoing voice path.
• a timeslot can also be used to carry computer data at rates up to 64K bits per second.
• the bus 10 has a signaling bus.
• a digital PBX switch must also transport and switch "signaling" or control information associated with individual voice or data ports. For example, for a rotary-dial telephone it is important to know that the handset has been taken “off-hook,” that a digit has been dialed, and so on. Thus, the PBX switch must have a way of gathering signaling information from individual voice ports, and transporting it to a control unit which acts upon this information by, for example, making voice connections. All digital PBX switches must have a timeslot bus and a signaling bus of some kind. Associated with these buses are many conflicting goals and problems. Among these are:
• a bus in a typical system has some number of "position”; each position has a bus connector which mates with a module or line card connector to connect a module to the bus.
• a bus is "universal” if the same signals exist in the same positions in every bus connector in the bus. In a universal bus, any module may be connected at any position in the bus. The advantages of such a system are evident.
• a completely parallel bus topology satisfies the requirements of a universal bus. It is easily laid out in printed circuit board technology. Regardless of the number of positions in the bus, it can be easily connected at any point.
• FIG. 2(a) There are two different timeslot switching techniques that are used in existing PBXs. "Centralized” switching is shown in Figure 2(a) .
• This technique there are logically two timeslot buses to carry voice and data signals.
• One bus carries outgoing timeslot signals from the central control unit to the line card modules containing the individual port circuits, and the other carries incoming timeslot signals, in the opposite direction.
• Each bus has a dedicated timeslot for every port in the system. For example, a voice port "X" always places its PCM signals on an incoming timeslot X, and receives PCM signals on an outgoing timeslot X.
• timeslot-interchange circuits in the central control unit can make all connections. For example, to connect ports X and Y, the timeslot-interchange circuits in the central control unit are programmed to store the PCM samples that arrive on incoming timeslot X and transmit them on outgoing timeslot Y; and to simultaneously store the PCM signals that arrive on the incoming timeslot Y and transmit them on the outgoing timeslot X. In “distributed" switching, shown in Figure
• each line card module has a local timeslot-interchange circuit which can connect the incoming signals from any port to any timeslot on the timeslot bus, and which can also listen to the signals on any timeslot and send them to any outgoing port.
• the central control unit may allocate a pair of timeslots, say P and Q, which need not have any fixed relationship to X and Y. It then instructs the local timeslot-interchange circuit for port X to transmit on timeslot P and receive on Q, while it instructs Y to transmit on Q and receive on P.
• the choice of either centralized or distributed timeslot switching is based on the performance of the switching technique and the cost effectiveness of the technologies available at the time of. the design. For example, the distributed technique utilizes timeslots more efficiently, since timeslots are not allocated for idle ports, while the centralized technique is typically less costly, since it requires just one timeslot-interchange circuit.
• the present invention attains many of these goals and solves or substantially mitigates many of these problems above.
• the present invention provides for a PBX switch comprising a plurality of modules, each module having at least one port for communicating signals to and from the PBX switch; a plurality of parallel lines for communicating the signals between the modules; and clock means coupled to the modules for defining a number of timeslots for the signals on the communication lines and for enabling the modules to communicate during a predetermined portion of a timeslot whereby more than one module may communicate in one timeslot.
• the parallel communication lines provide the universal bus in the present invention. Also, data transfer rate is maximized without increasing the switching speeds of the timeslots.
• Each module can be individually addressed.
• Each module has means for generating signals to identify the module and means, coupled to the identification means and the clock means mentioned above, for selecting a timeslot for the module so that a signal at the selected timeslot on one of the lines coupled to the timeslot selection means addresses the module.
• the invention provides for both the centralized and distributed timeslot switching.
• the PBX switch has a central control module in addition to line card modules having ports to the outside world. In centralized switching, the central control module transmits signals to the line card modules on a first set of the parallel lines and receives signals from the line card modules on a second set of the parallel lines. The control module also transmits and receives control messages to and from the modules on a third set of parallel lines.
• control module has a means for disabling the control module from transmitting signals on the first set of lines in predetermined timeslots and for generating control messages indicative of the control module disablement on the third set of lines.
• the line card modules themselves have means coupled to the third set of lines for transmitting signals on the first or second set of lines and for receiving signals on the first or second set of lines during the predetermined timeslots. During these timeslots the architecture of the PBX switch operates in a distributed manner.
• Fig. 1 shows the configuration of digital PBX switch.
• Fig. 2A shows a digital PBX operating in a centralized switching configuration
• Fig. 2B shows a digital PBX operating in a distributed switching configuration
• Fig. 3 details the timeslot and signaling buses of the present invention.
• Fig. 4 illustrates the clock operations and timeslot timing of the present invention.
• Fig. 5A shows diagramatically, the timeslot decoding circuit used in the line card modules connected to the timeslot bus of Fig. 3; the timing operations of the circuit are shown in Fig. 5B.
• Fig. 6A details the module- selection circuit on each line card module connected to the signaling bus of Fig. 3; the circuit's timing operations are shown in Fig. 6B.
• Fig. 7 illustrates the central control module circuit used in driving the line card module selection line of the signaling bus of Fig. 3.
• Fig. 8 shows the central control module and line card module circuits coupled to the Message In, Message Out and Reset lines of the signaling bus of Fig. 3.
• Fig. 1 shows the configuration of a general digital PBX switch.
• the switch typically has a central control module 10 and line card modules 12A-D.
• the control module 10 operates the central operation of the switch, such as gathering signal information from the individual modules 12A-D and coordinating the operations between the modules 12A-D.
• the line card module 12A-D typically has a plurality of ports through which voice and data is carried to and from the switch.
• These ports each have individual communication lines 13A-13C, which have terminals, such as telephones, connected at the end.
• Other line card modules (such as 12D) may be connected to trunk lines 130, which may be connected to another PBX switch (and another PBX system) or to the general telephone system or the like.
• the central control module 10 and line card modules 12A-D communicate through a bus 10.
• Fig. 3 shows the details of a bus, according to the present invention, particularly useful in digital PBX switches.
• the lines are connected to line card modules through connectors 14A-14D.
• all bus lines are completely parallel, with the exception of the unique module address terminals connected selectively to a ground line 31. This is discussed later.
• the bus in Fig. 3 is divided into three groups.
• the first group is a set of clock lines 21-23.
• the second group is a set of timeslot lines 24, 25 over which voice PCM signals and data signals pass between the modules of the PBX switch.
• the third group is a set of signaling lines 26-29. These lines 26-29 carry the signaling information between the modules.
• bus positions are identical except for the module-address signals, different types of modules may be connected at each bus position.
• one module should be the "bus master” in the sense that it supplies the clocks and other master control signals to which the other modules respond.
• this module is called “the central control unit.”
• One advantage of the present invention is that the central control module (or any other module) may be connected at any bus position.
• the first group of signals in Fig. 3 are clocks provided by the central control module on lines 21-23.
• Fig. 4 shows the timing of these clocks in the present embodiment of the invention.
• the signal TCLKA on the line 21 is a 2.048 MHz, 33% duty-cycle clock;
• the signal TCLKB on the line 22 is a similar 2.048 MHz, 33% duty-cycle clock that is 180 degrees out of phase with TCLKA.
• the importance of the shapes (or duty-cycles) of the clock signals in the invention is discussed later.
• the period of either clock is 1/(2.048 MHz), or approximately 488 nanoseconds (ns) .
• the TFRM signal is a framing signal which is active for one clock period every 125 microseconds ( ⁇ s) , or for one out of every 256 TCLKA or TCLKB periods.
• the interval between successive TFRM pulses is called a "frame.” This 125 ⁇ s period is standard with ⁇ -law or A-law PCM.
• the number of timeslots available for a given maximum clock frequency (2.048 MHz in the present embodiment) is maximized.
• TCLK timeslot clock
• the timeslot bus carries a single PCM or data signal for a full TCLK period.
• a 488 ns TCLK period there is defined 256 timeslots in a 125 ⁇ s frame.
• the present invention uses two 2.048 MHz, 33% duty-cycle clocks, TCLKA and TCLKA, allowing two timeslots to be defined within each 488ns clock period.
• timeslots are divided into two groups, "A” and "B".
• “A” timeslots occur when TCLKA is high, and "B" timeslots occur when TCLKB is high.
• the first timeslot to occur after the TFRM signals occurs is number 0; the remainder are numbered sequentially through 255.
• the TCLKA, TCLKB, and TFRM signals define 512 timeslots, numbered A-0 through A-255 and B-0 through B-255.
• Fig. 3 shows a centralized timeslot switching arrangement.
• Each of these buses is 8 bits wide.
• a bus carries a complete 8-bit PCM or data signal.
• the central control module contains timeslot-interchange circuits which store all of the signals received on the (incoming) TSIN bus 24, and which send the stored signals on any timeslot on the (outgoing) TSOUT bus 25.
• the central control module can connect any incoming timeslot signals to any outgoing timeslot.
• the central control module always drives the TSOUT bus 25, but different line card modules drive the TSIN bus 24 during different timeslots.
• the multiple-source capability for driving the TSIN bus 24 is achieved by the current practice of using three-state drivers on each module. To drive the TSIN bus 24, the TSIN bus driver on a particular module is enabled only during the TSIN timeslots allocated to that module, and disabled at all other times.
• Timeslot B-0 may be driven by module P
• timeslot A-l may be driven by module Q.
• it is important for module P's TSIN driver is disabled before module Q's is enabled. Otherwise, both P and Q modules will be driving the TSIN bus for a short period of time, possibly resulting in increased system noise and/or driver stress (hence, failure rates) , depending on the technology of the drivers.
• driver stress and system noise may be especially severe.
• This dead-time is important on the TSIN bus 24 in the centralized switching arrangement.
• a module merely needs to ensure that is only drives the TSOUT bus when TCLKA or TCLKB is high.
• TCLKA or TCLKB At 2.048. MHz, there is 81 ns of margin available for the propagation delays of the logic circuits on each module that make the enable/disable decision at each clock period.
• each module has a fixed set of timeslots allocated to it while the system is running. These timeslots are allocated when the system is configured (i.e., installed) , typically by hardware jumpers on the modules or by parameters loaded into the modules by a software initialization program.
• the whole purpose of centralized (as opposed to distributed) switching is to minimize the size and cost-of the circuitry on each line card module for allocating timeslots.
• the present invention uses minimal circuitry for allocating timeslots in a module.
• An important innovation in the timeslot allocation circuit is once again the use of the two-phase timeslot clocks (TCLKA and TCLKB).
• TCLKA and TCLKB the timeslot buses 24, 25 (TSIN and TSOUT) each contain 512 timeslots
• a particular module in a centralized switching application references its operation to either TCLKA or TCLKB, and therefore only has access to 256 timeslots (either the A group or the B group) .
• Another important contribution of the present invention is that a minimum number of switches or programmable bits are used to allocate a set of timeslots used by a particular module. For example, if a module needs 8 timeslots, then the 256 timeslots in group A or B are divided into 32 sets of 8, and a 5-bit number allocates one particular set. On the other hand, if a module needs 64 timeslots, then there are only 4 sets of 64, and a 2-bit number makes the allocation.
• Fig. 5A shows a typical embodiment of the timeslot decoding circuit in each line card module.
• This particular embodiment decodes timeslots in either group A or group B, depending on the position of a switch 38.
• the 256 timeslots in the selected group are divided into 16 sets of 16 timeslots each; a particular set is allocated by a 4-bit number in switches 39. Timeslots 0 through 15 are in set 0; 16 through 31 are in set 1; 32 through 47 are in set 2; and so on.
• a counter 31 is an 8-bit binary counter with outputs QA (least significant) through QH (most significant) , which increments every time a rising edge occurs on the CLK input; except that if the LOAD input is 1 at the rising CLK edge, the counter will not count and will instead load the inputs present at A through H.
• a decoder 33 is a circuit that activates at most one of its outputs (Y0 through Y15) at a time. If either the ENl or the EN2 input is 0, all outputs will be 0. However, if both ENl and EN2 are 1, then the output corresponding to the binary number present at inputs A through D will be 1, and all other outputs will be 0.
• a TSIN bus driver 35 is a three-state driver whose output is disabled if its ENABLE input is 0; if ENABLE is 1, then the input values on A0 through A7 are used to drive the TSIN bus 24.
• An input register 36 contains 8 edge-triggered D flip-flops. If the CLK ⁇ NABLE input is 1 when a rising edge occurs at the CLK input, then the D inputs (TSOUT bus values) will be stored in the flip-flops and will appear at the Q outputs for transmission into the line card module; at all other times the Q outputs will maintain their previous values.
• Fig. 5B shows a timing diagram for the decoding circuit of Fig. 5A. Assuming that clock TCLKA has been selected by the switch 38, and the binary value in switches 39 is "0000", then the circuit decodes the timeslots in set 0, that is, timeslots 0 through 15. At the falling edge of the clock TCLKA during the TFRM pulse, a corresponding rising edge occurs at the CLK input of the counter 31, which loads the value llllOOOO, into the counter outputs QH, QG,
• the AND gate 34 controls the ENABLE input of the three-state driver 35 so that it drives the TSIN bus 24 only during timeslots in the allocated set and only when TCLKA is 1, in accordance with the method of TSIN bus operation described earlier.
• the -CLKENABLE input of the register 36 controls the register 36 so that its contents change only in response to timeslots in the allocated set.
• the output lines of decoder 33 and the module timeslot buses for TSIN and TSOUT signals carry signals from or into the internal circuits of the module.
• the internal circuits of the modules are not part of this invention; moreover, this invention is useful to present line card modules and their internal circuits.
• Clearly logical equivalences may be used in any digital logic circuit.
• the inverters 40 in Fig. 5 may be eliminated by redefining the polarity of the switches 39, and the discrete AND gate 32 eliminated by using the "ripple carry output" function already built into the binary counter circuit 31.
• TCLK clock selection and timeslot-set number need not come from the switches 40.
• Other possibilities include, at one extreme,
• TCLK selection switch 38 is a function of the module's position on the bus, while timeslot-set selection switch 39 is programmable through a microprocessor on the module.
• the general scheme shown in Fig. 5 works very well for any number of timeslots that is a power of two, say 2 n .
• 8-n switches are used for the timeslot-set number (switches 39 in Fig. 5) , and an 8-n input AND gate (gate 32) is used, while an n-to-2 n decoder (decoder 33) is used.
• the starting timeslot of the set is always a multiple of the number of timeslots in the set. For example, if there are 8 32-timeslot sets, these start at timeslots 0, 32, 64, 96, 128, 160, 192, and 224, and run for 32- consecutive timeslots.
• a design for the next highest power of two may be "pruned" to Obtain the desired number of decoded timeslots.
• the Y15 and Y14 outputs of the decoder 33 in Fig. 5A are not used inside the module, except that they should be inverted and connected to additional inputs of the AND gate 34 to inhibit the
• the two left-over timeslots could be used by a module which only requires two timeslots.
• timeslot set 0 contains timeslots 0, 16, 32, ..., 240, set 1 contains timeslots 1, 17, 33, 241, and so on.
• a 1-timeslot offset can be obtained in almost any timeslot decoding circuit using flip-flop or register delays at appropriate points in the circuit. More difficult is a - ⁇ -timeslot offset.
• a --.-timeslot offset is particularly easy to obtain by once again exploiting the two-phase clocks (TCLKA and TCLKB) .
• TCLKA and TCLKB two-phase clocks
• TSOUT register 36 could be clocked by the clock TCLKB, and vice versa.
• the EN2 input of the decoder 33 may be enabled by the TCLKA, TCLKB, or both clocks depending on the particular requirements for the decoder outputs inside the module.
• each line card module has a particular number of switches 40 in Fig. 5A or preferably, programmable bits in its timeslot decoding circuit. This number corresponds to the size of the set, i.e., the number of timeslots, required to service the ports on that line card module. Additionally, besides minimizing the amount of circuitry for allocating sets of timeslots in a module, the present invention sets the value in the switches 40 or programmable bits so that different timeslot sets are assigned to different line card modules, even if different modules require different numbers of timeslots. For example, suppose the following modules are present and (for simplicity) all must use timeslots in group B (say, group A is already filled up) :
• modules P, Q, R, S , and T will be allocated as shown in Allocation #1.
• Module T has no longer 64 consecutive timeslots available. However, there is still a total of 96 available timeslots spread throughout the group of 256.
• the present invention makes the timeslot set allocations on each module programmable, directly or indirectly, by processors.
• the timeslot sets are directly programmable by microprocessors on each line card module, a central control module processor instructs the line card module microprocessors to make optimal timeslot-set allocations by sending them messages over a signaling bus described later with reference to Fig. 8.
• the central module microprocessor allocates the timeslot sets by first assigning the sets which are the largest. Then the sets with the next largest number of timeslots are assigned. These steps continue until the smallest sets are assigned. In this manner, timeslot sets are the most effectively allocated. Allocation #2 is an example. This type of program for the central module microprocessor may easily be written by persons skilled in the art.
• Fig. 3 shows that there are four module address connectors lines, MOD3-0, for each module. These connectors may be coupled to ground by a ground line 41 or left open in a different pattern at each module position. Thus, in principle, there are sixteen different "hard-wired" 4-bit module addresses to identify each line card module. (Obviously, additional module address connectors may be used to provide a larger number of module addresses, e.g., five lines for 32 addresses.)
• a typical way in the prior art of addressing modules is the provision of a 4-bit Module Select bus on which the central control module places the address of a selected module.
• a 4-bit comparator on each module compares the Module Select bus with its own hard-wired address (MOD3-0) at all times to see if it is being selected.
• MOD3-0 hard-wired address
• a disadvantage of this prior art is the size of the Module Select bus - four lines for a 4-bit address, and even more lines if more than 16 module addresses are required.
• the Module Select bus in the present invention contains just one signal line 26.
• the MS signal on this line 26 can address up to 512 different modules. In the preferred embodiment that we now describe, this MS line 26 addresses 32 different modules.
• the TCLKA, TCLKB, and TFRM clocks together define 512 unique timeslots.
• a smaller number of "select-slots" is defined.
• the select-slot number is just the remainder obtained from dividing the timeslot number by 16.
• timeslots A-l, A-17, and every sixteenth A-timeslot through A-241 are also select-slot A-l.
• a module is selected if the MS signal is "1" during the corresponding select-slot, or else the module is not selected.
• the central control module may select none, one, some, or all of the line card modules.- This is an improvement over the prior art, which had a parallel 4-bit bus, by which only one line card module was inflexibly selected.
• Fig. 6A shows the selection logic on each module.
• a counter 42 is a 4-bit binary counter with outputs QA through QD, which increments every time a rising edge occurs on the CLK input. However, if the LOAD input is 1 at the rising CLK edge, the counter 42 will load the signals present at A through D input terminals.
• the D flip-flop 43 and inverters 44-46 are standard logic circuits.
• Fig. 6B shows a timing diagram for the circuit to illustrate the operation of the circuit.
• the counter 42 is loaded with the complement of the module address number which is obtained from the MOD3-0 connectors.
• the counter 42 increments on each rising clock TCLKA or TCLKB edge, as selected by a switch 47.
• the counter 42 makes a transition from state 1111 to state 0000 (the counter- "state" is the value at the QD, QC, QB, QA output terminals) .
• This transition in particular the l-to-0 change on the QD output terminal, produces a 0-to-l transition on the output terminal of inverter 45. This in turn clocks the current value of the MS line 26 into the D flip-flop 43.
• This flip-flop output signal, MODSEL indicates whether or not this module is selected.
• the MODSEL signal remains stable until the next llll-to-0000 transition, 16 clock cycles (approximately 8 ⁇ sec) later.
• the select-slot in which the llll-to-0000 transition occurs depends on the module address number. For example, if the module address number of MOD3-0 is 0010, and switch 47 selects TCLKA, then the select-slot of interest is A-2. Thus, the MS signal during the select-slot A-2 determines whether or not the module is selected for the next 8 ⁇ sec.
• a physical switch 47 is not used. Rather, half the line card modules have their counter 42 clock inputs connected to TCLKA and the other half have their inputs connected to TCLKB. This gives rise to the 32 module addresses, A-0 through A-15, and B-0 through B-15.
• the inverters 44, 45 may be eliminated by simply inverting bits 0-2 of the hard-wired module address number.
• the preferred embodiment of the module-select circuit has minimal cost, consisting of an inexpensive 4-bit counter 42 and a D flip-flop 43.
• Fig. 6B shows a circuit in the central control module which can be programmed to select none, one, or all of the line card modules.
• the counter 50 is similar to the counter 42 in Fig. 6A, except that it only counts if its EN input is 1.
• the FFRM signal is a frame signal similar to TFRM, except that the signal occurs 16 times as often; that is, it occurs not only during timeslot 255, but also during timeslots 15, 31, 47, and so on through 255.
• This clock signal can easily be generated by the clock circuit which generates TCLKA, TCLKB and TFRM.
• MODN3-0 in Fig. 7 are connected to a microprocessor 61 (in Fig. 8) in the central control module which selects the line card modules.
• the microprocessor 61 may control these signals as follows:
• Fig. 10 shows the circuitry required on both the central control module and a line card module.
• the line card module circuitry is repeated on all other line card modules.
• UARTs 60, 70, are conventional Universal Asynchronous Receiver
• Transmitters which send and receive serial messages on their TXD (Transmit Data) outputs and RXD (Receive
• the UART function is integrated with a single-chip microcomputer, such as the 8031 manufactured by Intel Corporation of Santa
• Fig. 8 The other elements in Fig. 8 are standard logic gates and components.
• Fig. 8 has several important advantages over conventional party-line signaling buses in the prior art.
• a conventional party-line signaling bus the TXD output from the central control's UART is bused directly to the RXD inputs of all the other module UARTs, and the TXD outputs of all the other module UARTs are "AND-tied" directly, without the benefit of MODSEL gating 62, 66, to drive the RXD input of the central control module's UART.
• Undesirable results of such an arrangement are: ° Whenever the central control transmits, all modules must listen and determine whether or not the message current message is for them.
• a single failed module can bring down the signaling bus for everyone, by generating "garbage” messages on the MI line.
• the central control module can select which module it wishes to communicate with at any time. It does this using the module selection circuitry described previously.
• its MODSEL signal is 1. Therefore, its TXD UART output is driven onto the MI line 27 through an open-collector NAND gate 62, and the signal on the MO line 28 is coupled into its RXD UART input through an OR gate 64. If the module is not selected, then the NAND gate 62 output is inactive (floating) , and the RXD UART input is forced to 1, which is the "idle" condition for a conventional UART.
• the central control module's ability to select a specific module to communicate with brings several advantages not enjoyed by a conventional party-line signaling bus arrangement:
• Fig. 8 illustrates how microprocessors 71 on the line card modules communicate with the - microprocessor 61, such as a Motorola 68000 of Phoenix, Arizona, on the central control module.
• Each of the microprocessors 71 handles operations for its own line card module.
• the central microprocessor 71 handles operations for the entire PBX switch, including the allocation of time slots discussed previously and distributed timeslot switching discussed later. It should be understood that each of the microprocessors 61, 71 are also coupled to the other parts of their modules. The particular connections are dependent on the particular design of the modules.
• Another advantage of the present invention is in the area of polling.
• the master can contact the slaves at any time, but the slaves can contact the master only when the master allows it. Therefore, the master must have some means of finding out when a slave wishes to send something.
• Two conventional methods are:
• RTS Request-to-send
• the polling method requires no extra hardware, but it is slow and requires processing overhead to send and receive the (usually fruitless) polling messages.
• the RTS method is much faster and has less overhead (a slave is not disturbed unless it actually has something to send) , but it requires more hardware and potentially a non-parallel bus to return the RTS lines to the central control module.
• an RTS mechanism is achieved with no extra hardware.
• a line card module simply places a continuous "0" logic value on its UART's TXD output, and waits for the central control module; this continuous 0 is known as a "break" condition in conventional UARTs.
• the central control module may ignore the "break,” and force the selected module to receive a command.
• a module always removes the "break” while communicating with the central control module, and after the conversation it sends "break” only if it still has something more to send.
• Another function of the signaling bus of the present invention is reset. In any digital system, it is necessary to reset the system to a known state at power-up. In addition, it is desirable to be able to reset the system at other times, if, for example, due to some transient error, the system goes into an unknown state during normal operation. For this reason, most systems provide reset pushbuttons, watchdog timers, and other devices.
• the module selection mechanism provides a novel means of selectably resetting modules. As shown in Fig. 3 and Fig. 8, a single RESET signal is bused on a line 29 to all of the modules. The signal is driven by an output port bit of the microprocessor 61 in the central control module. On each line card module, this signal is combined by an AND gate 65 with the local MODSEL signal to provide a local MODRESET signal.
• the central control module selects that module and then asserts RESET signal.
• the central control module must be careful to remove RESET signal before deselecting the module. For example, the control module might select some other module with which module to communicate on the signaling bus. Also, note that with the central control module MS driving circuit shown in Fig. 7, it is possible to select all of the modules, so that all the modules may be reset simultaneously for quick, complete, system initialization.
• the present invention permits the time slot bus 24, 25 to operate in a distributed switching arrangement.
• the timeslot bus 24, 25 of Fig. 3 has been described in a centralized switching arrangement as shown in Fig. 2A.
• the signaling bus, specifically the MI line 27, MO line 28 and MS line 26, with their associated circuitry, provide for the present invention to operate in a distributed switching arrangement.
• the -central control module can easily be programmed not to drive the TSOUT bus 25 during certain timeslots.
• the microprocessor 61 selects a particular line card module and informs the microprocessor 71 on that card that a timeslot or timeslots on the TSOUT bus 25 have been assigned to that line card module.
• the line card module can use the TSOUT bus 25, besides the TSIN bus 26, to send PCM voice and data signals.
• the microprocessor 61 can also allocate other timeslots on the TSOUT bus 25 to other line card modules.
• the microprocessor 61 may allocate timeslots on the TSIN bus 24 for selected line cards to receive voice PCM and data signals.
• the separation of the timeslot bus into a bus carrying outgoing signals (TSOUT bus 25) and a bus carrying incoming signals (TSIN bus 24) is removed.
• the PBX switch with the present invnetion can also operate in a distributed switching arrangement as shown by Fig. 2B.
• the TSIN bus 24 driver circuit and the TSIN bus 25 driver circuit of Fig. 5A may easily be modified for bi-directional transmission and reception for distributed switching.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
• Small-Scale Networks (AREA)
• Sub-Exchange Stations And Push- Button Telephones (AREA)

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• 1984
  • 1984-11-13 JP JP59239313A patent/JPS60240294A/ja active Pending
• 1985
  • 1985-03-28 AU AU41513/85A patent/AU584331B2/en not_active Ceased
  • 1985-03-28 WO PCT/US1985/000526 patent/WO1985005241A1/en not_active Application Discontinuation
  • 1985-03-28 BR BR8506717A patent/BR8506717A/pt unknown
  • 1985-03-28 EP EP19850901843 patent/EP0182798A4/en not_active Withdrawn
  • 1985-04-12 ZA ZA852744A patent/ZA852744B/xx unknown
  • 1985-04-29 KR KR1019850002878A patent/KR900001029B1/ko not_active IP Right Cessation
  • 1985-05-02 IL IL75071A patent/IL75071A/xx unknown
  • 1985-05-03 CA CA000480718A patent/CA1237186A/en not_active Expired
  • 1985-05-06 ES ES542847A patent/ES8700526A1/es not_active Expired
• 1986
  • 1986-06-10 ES ES555892A patent/ES8708105A1/es not_active Expired
  • 1986-06-10 ES ES555893A patent/ES8708106A1/es not_active Expired
• 1989
  • 1989-03-06 AU AU30993/89A patent/AU3099389A/en not_active Abandoned
  • 1989-03-06 AU AU30995/89A patent/AU3099589A/en not_active Abandoned

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