EP0169018A3 - Computer memory system - Google Patents

Computer memory system Download PDF

Info

Publication number
EP0169018A3
EP0169018A3 EP85304873A EP85304873A EP0169018A3 EP 0169018 A3 EP0169018 A3 EP 0169018A3 EP 85304873 A EP85304873 A EP 85304873A EP 85304873 A EP85304873 A EP 85304873A EP 0169018 A3 EP0169018 A3 EP 0169018A3
Authority
EP
European Patent Office
Prior art keywords
memory
memory system
user
user processor
blocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP85304873A
Other languages
German (de)
French (fr)
Other versions
EP0169018A2 (en
Inventor
Donald W. Oxley
Glenn E. Manuel
William M. Knight Jr.
Jeri J. Loafman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of EP0169018A2 publication Critical patent/EP0169018A2/en
Publication of EP0169018A3 publication Critical patent/EP0169018A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

A computer memory system (10) is provided for use with a user processor (20), and which provides automatic memory operations independently of the user processor (30). The memory system (10) includes a logical memory system ((10)) which is accessed by the user processor (20) through a binding register unit (15), enabling the user processor (20) to allocate blocks (40, 45) and specify the length of the blocks. Data (40d, 45d) within the blocks (40, 45) can also be specified by the user by relative indexing ("i", "j") with respect to a block specifier in the binding register unit (15). The user cannot ac­ cess the memory (12) directly, but must access the memory (12) through the binding registers (21-30). The logical memory system (10) is controlled by a separate memory management unit (11) which manages the physical memory (12) of the sys­ tem (10) which manages the memory (12) to have the logical memory system ((10)) appearance to the user processor (20).
EP85304873A 1984-07-12 1985-07-09 Computer memory system Withdrawn EP0169018A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US630476 1984-07-12
US06/630,476 US4989137A (en) 1984-07-12 1984-07-12 Computer memory system

Publications (2)

Publication Number Publication Date
EP0169018A2 EP0169018A2 (en) 1986-01-22
EP0169018A3 true EP0169018A3 (en) 1989-09-13

Family

ID=24527332

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85304873A Withdrawn EP0169018A3 (en) 1984-07-12 1985-07-09 Computer memory system

Country Status (3)

Country Link
US (1) US4989137A (en)
EP (1) EP0169018A3 (en)
JP (1) JPS61112257A (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2545789B2 (en) * 1986-04-14 1996-10-23 株式会社日立製作所 Information processing device
US5384900A (en) * 1988-03-14 1995-01-24 Canon Kabushiki Kaisha Method of managing an image memory by a process independent of an image processing process
JPH0244444A (en) * 1988-08-05 1990-02-14 Nec Corp Memory managing system
US5189733A (en) * 1989-08-22 1993-02-23 Borland International, Inc. Application program memory management system
EP0416767A3 (en) * 1989-09-08 1992-04-29 Digital Equipment Corporation Position independent code location system
US5414826A (en) * 1990-01-31 1995-05-09 Hewlett-Packard Company System and method for memory management in microcomputer
US5410671A (en) * 1990-05-01 1995-04-25 Cyrix Corporation Data compression/decompression processor
JPH0418638A (en) * 1990-05-11 1992-01-22 Fujitsu Ltd Static memory allocation processing method
US5355483A (en) * 1991-07-18 1994-10-11 Next Computers Asynchronous garbage collection
FR2679671B1 (en) * 1991-07-25 1995-04-14 Sogitec Ind PROCESSOR OF COMPLEX STRUCTURES.
US5809551A (en) * 1991-08-23 1998-09-15 International Business Machines Corporation Pending page release
US5742793A (en) * 1991-12-18 1998-04-21 Intel Corporation Method and apparatus for dynamic memory management by association of free memory blocks using a binary tree organized in an address and size dependent manner
WO1994002898A1 (en) * 1992-07-24 1994-02-03 Microsoft Corporation Computer method and system for allocating and freeing memory
US6131150A (en) * 1993-10-05 2000-10-10 Digital Equipment Corporation Scaled memory allocation system
US5611043A (en) * 1994-03-18 1997-03-11 Borland International, Inc. Debugger system and method for controlling child processes
US6745213B2 (en) * 2001-11-21 2004-06-01 Sun Microsystems, Inc. Method and apparatus to facilitate testing of garbage collection implementations
CA2479526C (en) 2002-03-20 2015-11-17 Research In Motion Limited System and method of secure garbage collection on a mobile device
US8042189B2 (en) 2002-03-20 2011-10-18 Research In Motion Limited System and method to force a mobile device into a secure state
US9601199B2 (en) 2007-01-26 2017-03-21 Intel Corporation Iterator register for structured memory
TWI417722B (en) * 2007-01-26 2013-12-01 Hicamp Systems Inc Hierarchical immutable content-addressable memory processor
US8156256B2 (en) * 2007-04-24 2012-04-10 Samsung Electronics Co., Ltd. Method for managing logical address and device thereof
US8370458B2 (en) * 2007-12-21 2013-02-05 Hicamp Systems, Inc. Hierarchical block-identified data communication for unified handling of structured data and data compression
US10089235B1 (en) 2017-07-28 2018-10-02 Citrix Systems, Inc. Dynamic trim processing with disk caching

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4149240A (en) * 1974-03-29 1979-04-10 Massachusetts Institute Of Technology Data processing apparatus for highly parallel execution of data structure operations
JPS5740790A (en) * 1980-08-25 1982-03-06 Fujitsu Ltd Storage control system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4016545A (en) * 1975-07-31 1977-04-05 Harris Corporation Plural memory controller apparatus
DE2641722C3 (en) * 1976-09-16 1981-10-08 Siemens AG, 1000 Berlin und 8000 München Hierarchically organized storage system for a data processing system with virtual addressing
US4398248A (en) * 1980-10-20 1983-08-09 Mcdonnell Douglas Corporation Adaptive WSI/MNOS solid state memory system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4149240A (en) * 1974-03-29 1979-04-10 Massachusetts Institute Of Technology Data processing apparatus for highly parallel execution of data structure operations
JPS5740790A (en) * 1980-08-25 1982-03-06 Fujitsu Ltd Storage control system

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
AFIPS - PROCEEDINGS OF THE SPRING JOINT COMPUTER CONFERENCE, Atlantic City, New Jersey, 18th-20th May 1971, vol. 38, pages 601-616, AFIPS Press, Montvale, NJ, US; W.R. SMITH et al.: "Symbol - A large experimental system exploring major hardware replacement of software" *
COMPUTER, vol. 14, no. 7, July 1981, pages 10-21, IEEE, New York, US; G.J. SUSSMAN et al.: "Scheme-79- Lisp on a chip" *
PATENT ABSTRACTS OF JAPAN, vol. 6, no. 112 (P-124)[990], 23rd June 1982; & JP-A-57 040 790 (FUJITSU K.K.) 06-03-1982 *

Also Published As

Publication number Publication date
US4989137A (en) 1991-01-29
EP0169018A2 (en) 1986-01-22
JPS61112257A (en) 1986-05-30

Similar Documents

Publication Publication Date Title
EP0169018A3 (en) Computer memory system
GB8503481D0 (en) Granting access to computers
ES8407274A1 (en) Dual bus communication system
AU568395B2 (en) An arrangement for the generation of information and/or an instruction intended for input to the program memory of computer
EP0644486A3 (en) Management of data accesses in computer systems.
EP0315945A3 (en) Virtual storage type computer system
GB9304140D0 (en) Computer bus with virtual memory data transfer capability using virtual address/data lines
KR890003688B1 (en) Buffer-storage control system
EP0389001A3 (en) Computer vector multiprocessing control
NO843056L (en) DATAOVERFOERINGSSYSTEM
EP0285346A3 (en) Cache memory device
JPS54142950A (en) Data transfer system
EP0164972A3 (en) Shared memory multiprocessor system
JPS5483728A (en) Common memory lock system
JPS57162162A (en) Multiplex virtual space data processing system
JPS576951A (en) Error logging system
JPS5733471A (en) Memory access control system for multiprocessor
JPS559283A (en) Interface circuit system for floppy disc for microcomputer
JPS5733472A (en) Memory access control system
JPS56153452A (en) Virtual computer system
JPS54144835A (en) Magnetic disc sub-system
EP0287844A3 (en) Cache memory circuit using dual port memories
JPS56100586A (en) Ipl system in decentralized processing electronic exchanger
JPS5591048A (en) Tracing system for program execution state
JPS5532159A (en) Memory system

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): DE FR GB

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19900314

RIN1 Information on inventor provided before grant (corrected)

Inventor name: KNIGHT, WILLIAM M. JR.

Inventor name: LOAFMAN, JERI J.

Inventor name: OXLEY, DONALD W.

Inventor name: MANUEL, GLENN E.