EP0130150B1 - Chronographe électronique, notamment montre-chronographe électronique, analogique, compteur de temps chronométrés - Google Patents

Chronographe électronique, notamment montre-chronographe électronique, analogique, compteur de temps chronométrés Download PDF

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Publication number
EP0130150B1
EP0130150B1 EP84810303A EP84810303A EP0130150B1 EP 0130150 B1 EP0130150 B1 EP 0130150B1 EP 84810303 A EP84810303 A EP 84810303A EP 84810303 A EP84810303 A EP 84810303A EP 0130150 B1 EP0130150 B1 EP 0130150B1
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EP
European Patent Office
Prior art keywords
time
counter
memory
measured
chronograph
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Expired
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EP84810303A
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German (de)
English (en)
French (fr)
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EP0130150A1 (fr
Inventor
Marcel Réne Gerber
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TAG Heuer SA
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TAG Heuer SA
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Publication of EP0130150A1 publication Critical patent/EP0130150A1/fr
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C3/00—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means
    • G04C3/14—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means incorporating a stepping motor
    • G04C3/146—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means incorporating a stepping motor incorporating two or more stepping motors or rotors
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F8/00—Apparatus for measuring unknown time intervals by electromechanical means
    • G04F8/006—Apparatus for measuring unknown time intervals by electromechanical means running only during the time interval to be measured, e.g. stop-watch
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G9/00—Visual time or date indication means
    • G04G9/0082—Visual time or date indication means by building-up characters using a combination of indicating elements and by selecting desired characters out of a number of characters or by selecting indicating elements the positions of which represents the time, i.e. combinations of G04G9/02 and G04G9/08

Definitions

  • the present invention relates to an analog electronic chronograph with timed time counter, in particular an analog electronic chronograph watch with timed time counter, comprising a display device equipped with a minute hand of timed time, a second hand of timed time and means for displaying timed time units of duration less than one second, electronic time counting means, a stepping motor for moving at least said second hand of the timed time in synchronism with the means for counting and a control device comprising several manual organs capable of controlling at least the starting of the chronograph counting, its stopping, the taking and display of an intermediate time, as well as the catching up of the display of the timed time.
  • a piece that can be produced in a wristwatch format which makes it easy to “split (that is to say, to take the exact time)” from a very rapid succession of runners' passages, then to read successively all of these times, in an analog form, would certainly find an interest marked with timekeepers, typically for sports timekeeping, but also for other types of timekeeping.
  • the object of the present invention is to provide an analog electronic chronograph, in particular in the form of an analog electronic chronograph watch, making it possible to achieve the desirable performances, in particular the performances relating to the memorization of different timed times combined with an analog display arrangement. .
  • the invention thus aims to combine in a very flexible and diversified manner in terms of use but remaining very simple in terms of manufacturing, the advantages of electronic storage of the timed times and of the analog display thereof, d '' in a reliable way and allowing verification reminders.
  • the proposed chronograph or chronograph watch must be adaptable with flexibility to the different types of timing that may occur.
  • the chronograph watch comprises a housing 1, containing an electronic assembly for actuating the hands for measuring the current time and the hands of the different chronograph function variants.
  • the current time is displayed, in a conventional manner, by an hour hand 2, central, a minute hand 3, also central, and a second hand 4, in the “six o'clock” position, as has often been done.
  • the hands of the chronograph function consist of a timed time hour hand 8, a timed time minute hand 7, located at "twelve o'clock and" nine o'clock respectively.
  • the most important hands for timing i.e.
  • the hand 6 of the seconds of timed time and the hand 5 of the hundredths of a second of timed time are also central hands, the hand of the hundredths of seconds of timed time working on an entirely external scale of a circular dial on which a unit of a hundredth of a turn can easily be read.
  • the watch comprises a series of timed time memories, and the contents of these memories can be selectively displayed, a digital display field 13 typically with liquid crystal, providing the indication of that of the memories.
  • the hands of the chronograph function indicate the content.
  • the hundredths of a second hand 5 is not permanently moved but it is brought afterwards to the desired value, electronically recorded, once the time to be measured has been apprehended. In operation, the hundredths of a second hand 5 remains stationary as long as the time is being counted and the display of a timed time has not been called up.
  • the SPLIT function is the typical, most common function, which allows intermediate time scores throughout a course or crossing scores of different runners during the same basic timing.
  • a press on a push-button 10 started counting the chronograph, and one or more new presses on this button will make it possible to note intermediate times, even a final time.
  • the counting of time bases will continue until it is ended by a STOP function using a push button 11.
  • each press by which the time of a passage is noted does not interrupt the operation of the basic counter but instantly resets it to zero, which means that a new count begins.
  • This LAP system is used for example for racing circuits when you want to know each time the time taken by a racer to complete a lap. Thus, the timing of the end of the previous lap coincides with the timing of the timing of the next lap.
  • the number of memories that such a watch can contain can be relatively high, relatively simple pieces can have six to eight memories, other pieces, more professional, can count twenty, thirty, even fifty or more.
  • a two-digit display has been provided, which at most would correspond to ninety-nine memories.
  • Pressing push-button 10 starts the time counter, hands 6, 7 and 8 rotate.
  • a second press on the push button 11 resets the counter to zero, that is to say that the four hands 5, 6, 7 and 8 are brought back to zero.
  • the digital display 13, representative of the rank of the memory whose content is displayed remains at zero.
  • the function is the same as above, except for the fact that, following the first pressure on the push-button 11, a new pressure is applied on the push-button 10 so that the hands 6, 7 and 8 start again, while the hundredths of a second hand stays where it was. Then, the next pressure on the pusher 11 again stops the needles, and the process can be repeated as much as desired. At the end, when the pusher 11 has been pressed twice in succession, the second pressure on the pusher brings all the needles to zero. The digital display 13 also remains at zero in this function.
  • Pressing push-button 10 starts counting the time, hands 6, 7 and 8 turn. Pressing push-button 10 again performs a "SPLIT", that is to say that the time counter does not stop, but the first memory stores the time of the SPLIT.
  • the device determining which memory is read causes the reading of the first memory, so that the hands 6, 7 and 8 stop at the time corresponding to the instant when one pressed on button 10, and at the same time hand 5, hundredths of a second, joins the memorized value.
  • the digital display then indicates "1", which means that the content of the first memory is displayed.
  • the hands 6, 7 and 8 join the time value of the time counter, more precisely they join the value of the following memory, which is itself synchronized with the time counter.
  • the needle 5 remains in place; display 13 will mark “2” suggesting that we could take a second SPLIT, but we admit here that there is only one. Then, pressing the button 11 stops the time counter, the hands 6, 7 and 8 stop on the measured time, the needle 5 returns to the position corresponding to the number of hundredths measured.
  • Pressing push-button 10 starts the time counter, hands 6 and 7 rotate. Then, a first press of SPLIT, again on push-button 10, causes the time thus detected to be memorized in a first memory, but the basic time counter does not stop. On the other hand, the hands 6, 7 and 8 stop at the positions corresponding to the time thus memorized and the needle 5 rejoins the memorized value.
  • the digital display 13 indicates 1 1 ". Then, for example, if a certain number of runners arrive very quickly at the aiming point, press the pusher 10 again. The time values are successively memorized, each time in a subsequent memory. The digital display, however, always indicates the value "1 •, and the hands remain positioned on the indications of the first recorded time.
  • This "RATTRAPANTE” or RESYNCHRONIZATION function is useful mainly when, after having loaded all memories, there is still time to collect, that is to say that the number of runners is greater than the number of memories. We can then start again to take times (SPLITS) which will come back successively in memories 1, 2, etc. To call up the display of the next memory, pressure is exerted on the push-button 12. It should be noted that, at the time of the first SPLIT while the digital display 13 is still at zero, the change to "1" is made automatically, and the hands are positioned on the value memorized in the first memory, without it being necessary to act on the push-button 12.
  • a first press on the pusher 10 starts the counter, the hands 6, 7 and 8 rotate. Then, a first time-taking pressure again on the pusher 10 causes the display of the first time thus memorized in the first memory, the digital display 13 indicates "1".
  • a first press on the pusher 10 starts the counter, the hands 6, 7 and 8 rotate. Then, a first time-taking pressure again on the pusher 10 causes the display of the first time thus memorized in the first memory, the digital display 13 indicates "1".
  • push button 11 stop
  • the function RATTRAPANTE, RESYNCHRONISATION may either be possible only when the counter is running, or may also be possible when the counter is stopped.
  • To perform this function always first press push-button 12, which prepares the action, then push-button 11, which resynchronizes all the memories on the basic counter. If it is stopped, all memories will re-synchronize to the value at which the base counter is stopped. On the other hand, because the pusher 11 is pressed while the pusher 12 is also being pressed, this pressure on the pusher 11 does not cause a reset (or RESET).
  • LAP function or LAP-RESET
  • the times are apprehended using the pusher 10, as has been seen previously, but, prior to actuation of the pusher 10, the pusher 12 is pressed which prepares the LAP function or place of the SPLIT function.
  • the time is memorized and the counter does not stop but is instantly reset to zero to start from zero.
  • Hands 6, 7 and 8 stop and the hundredths of a second hand is positioned correctly; digital display 13 indicates "1".
  • the first memory will memorize the time of the first lap, the second memory the time of the second lap, the third memory the time of the third lap, etc. If you have to memorize a number of lap times greater than the number of available memories, you can use the SHIFT, RESYNCHRONIZATION function exactly as seen above; naturally the lap times memorized prior to the RESYNCHRONIZATION are lost, that is to say that the memories are discharged and made free for the next memorizations.
  • the digital display field 13 displays the rank of the memory whose content is displayed.
  • this display field shows the date.
  • a circuit time delay causes that, after approximately 3 sec, the control of display 13 changes and the date appears in this field. This appearance of the date remains as long as the pusher 12 is pressed; as soon as it is released, the memory rank read is displayed again.
  • Such pressure on the pusher 12, to temporarily display the date does not cause the otherwise usual action of a pressure on the pusher 12, that is to say the advancement of a step of the rank of the memory whose contents are displayed.
  • FIG. 2E the four figures 2A, 2B, 2C and 2D form a whole, in the manner which is illustrated in FIG. 2E.
  • Fig. 3 is a diagram of the counter-comparator 51 of FIG. 2B, whose rather particular structure deserved to be represented in more detail.
  • Fig. 4 is a detailed diagram of a memory such as memories 66, 67, 68 1-n of FIG. 2C. It will also be noted that, in order to more easily find the elements, reference signs have been taken between 20 and 39 for FIG. 2A, between 40 and 59 for fig. 2B, between 60 and 79 for fig. 2C and between 80 and 110 for fig. 2D. The reference signs of fig. 3 are between 110 and 120, those of FIG. 4 between 130 and 140.
  • An oscillator 21, controlled by quartz, provides a high frequency which is divided up to 100 Hz in a frequency divider 22. Since then, there is, for the current time display function, a second frequency divider 23 providing a frequency of 1 Hz. This is applied to an AND gate 24, the other input of which is applied a level "1", unless an SO switch (second to zero) is operated and applies a zero level on this other entry. This switch is closed (on) when the crown 9 for resetting the mechanical time of the hands 2, 3 and 4 indicating the current time is operated. In this case, the pulses at 1 Hz can no longer pass through the door 24 and the stepping motor which actuates the seconds hand of the current time is stopped.
  • a mechanical or electronic device could be provided which not only stops the second hand but resets it to zero.
  • pulses at 1 Hz exit from the door 24 and are applied to a circuit 25 which proceeds to the desired shaping of the pulses intended to advance a motor every 36 seconds.
  • This motor 36 actuates, as seen in 37a, a second hand, which, by a conventional gear mechanism, drives a minute hand which itself drives the hour hand.
  • a contact H (see fig. 2B lower left) is actuated twice a day by the hour hand of the current time, for counting the date.
  • the output at 100 Hz of the frequency divider 22 is also applied to a gate 30 which constitutes the control gate of the basic time counter for the chronograph function.
  • a gate 30 which constitutes the control gate of the basic time counter for the chronograph function.
  • the push-button 10 acts first of all on a shaping stage 26, the output signal of which puts a flip-flop 29 in the working state.
  • the output Q of the latter is applied to the second entry of the AND gate 30, so that the basic counter of the chronograph function operates when the flip-flop 29 is in the working state while it is stopped when this flip-flop is in the state of rest.
  • a second flip-flop, 28 follows in its tilting the flip-flop 29, but with a delay equal to the duration of the pulse which acts on the flip-flop 29.
  • the push-button 11 is actuated and its pulse is shaped by a circuit 27.
  • This pulse is applied to an AND gate 37 whose other input receives the signal from the output Q of the flip-flop 28, and of which yet another input receives a signal C which is at level "1 when the push-button 12 is not pressed and which passes to level" 0 ", when the latter is pressed In this way, if the push button 11 is operated while the push button 12 is pressed, the STOP function cannot be carried out.
  • a second manipulation of the push button 11 causes a reset function (RESET) via an AND gate 38, one input of which receives the signal from the pulse generator 27 and one of which another input receives the signal from the output Q of the flip-flop 28.
  • REET reset function
  • the reset necessarily requires two manipulations of the pusher 11, which must first have been released to rock the flip-flop 28 back, before that a new manipulation can cause the reset function through the door 38.
  • the latter also receives the signal C, which has the same effect as has just been explained concerning the door 37.
  • the door 30 is therefore on or off, and the base counter of the chronograph function is either running or stopped.
  • the output signal from gate 30, by a line CT is first applied to a pulse formatter 51 which delivers a pulse every hundredths of a second.
  • This pulse is applied to the clock input of a memory counter 65 o which counts according to a cycle of 100, (preferably two quartetts BCD in series) and which provides the information of hundredths of a second of chronograph.
  • a memory counter 65 o which counts according to a cycle of 100, (preferably two quartetts BCD in series) and which provides the information of hundredths of a second of chronograph.
  • This information is provided on a line formed by a plurality of conductors, which is why the connection is drawn in thick lines.
  • the conductor with the highest weight switches once per cycle and is taken from the output information from the memory counter 65 o to be applied to a pulse formatter 62 which delivers a signal at one pulse per second. Similarly, this signal activates a memory counter 66 0 , which counts to 60 and which provides the indication of seconds on a line comprising a plurality of conductors. Again the information of the driver having the highest weighting is taken from this information to be applied to a pulse trainer 63 which delivers one pulse per minute, which is applied as clock pulse to a memory counter 67 o which count the minutes.
  • the latter delivers the minute information on a multi-conductor line, and the highest weighting signal is taken to be applied to a pulse-forming stage 64 which delivers one pulse per hour to a memory counter 68 0 delivering time information on a multi-conductor line.
  • the set of memory counters 65 0 , 66 o , 67 o and 68 0 constitutes the basic counter for the chronograph function.
  • the four multiple pieces of information output from these counters namely the information of the hundredths of a second of the chronograph, the information of the seconds of the chronograph, the information of the chronograph minutes, and the information of the chronograph hours, are delivered on bus lines which are applied respectively to the positioning inputs E of a whole series of memories 65 1 -65 n for hundredths of a second, 66 1 -66 n for seconds, 671-67n for minutes and 68 1 -68 n for hours.
  • there are groups of four memories each group being however considered to be a time information memory, ranging from hundredths of a second to hours.
  • memory no 1 for the group formed of (partial) memories 65 1 , 66 1 , 67 1 , 68 1 , of memory no 2 for the group formed of the following (partial) memories, etc. .. up to memory no n, for the group made up of (partial) memories 65 n , 66 n , 67 n , 68 n .
  • Each (partial) memory shown in fig. 2C can advantageously have the structure shown in FIG. 4.
  • it consists of a memory element proper 135, the input of which is controlled by a multiple door 134, which lets pass or not the multiple information located on the input E.
  • the output of the memory element 135 is applied to an output circuit 136 which comprises a multiple AND gate circuit 136a, and a group of output stages 136b. Again the information leaving the memory element 135 can be transmitted or stopped according to the command supplied to the multiple door 136a.
  • the output stages In fig. 4, only one of the output stages has been shown, and it can be seen that it is formed by a transistor 137 working on a resistor 138.
  • Such a configuration of output stages makes it possible to easily parallel the stages counterpart output from all memories the same. weighting, this direct galvanic connection of all outputs on a conductor automatically establishing an OR function. It is noted that the resistance 138 can be extremely high, given the fact that there will be a large number of them in parallel. One can also provide for having a resistor 138 only for example on the outputs of the last memories, of rank n, the others being simply deleted.
  • An input Ts controls the multiple output gate 136a, and there is only ever one memory, the first, the second or the n-1 th, or the n th, whose output is on. Indeed, as we will see, there is only one of the memories (complete ranging from hundredths of a second to hours) which receives a signal of level "1 on its input Ts.
  • the inputs Ts of the different memories are supplied by the lines A o -A n , which correspond to the different outputs of the counter-comparator 51 which will be considered below.
  • the memory counters 65 o -68 o include the same output circuit 136a, which makes it possible to control their output exactly like that of simple memories, also by a TS input.
  • these memory counters include two outputs, one (MCO, MSO, MMO, MHO) to permanently supply the corresponding information, for the subordinate memories and another output S , controlled by a circuit similar to circuit 136 of FIG. 4, and which delivers information only when it is desired to display the information even contained in the memory counters, that is to say the basic counter of the chronograph function.
  • the opening or closing of the multiple door 134, at the entry of each (partial) memory is controlled by a flip-flop 132 which is put in the working position on reception of a BL pulse (blocking), passing through a shaping stage 130, and which is put in the rest position by an impulse on an input Sy (Synchronization) via the shaping stage 131.
  • This is the information of the output Q of the flip-flop 132 which controls the multiple door 134, however passing through an OR gate 133.
  • the blocking pulse arriving through the stage 130, puts the flip-flop 132 in the working state and therefore establishes a zero level at the output Q.
  • the level applied to the multiple gate 134 is always level "1 •.
  • the BL pulse makes it non-passing, but only from the moment of its disappearance.
  • a BL pulse is applied while the flip-flop 132 is already in the working state, that is to say that the door 134 is already busy, a level "1" appears at the entry of this gate 134 only during the very short duration of the pulse delivered by the pulse forming stage 130, which means that, for a brief instant, the information present on the input E can pass on the memory element 135.
  • both the memory counters (“basic counter” or “zero counter”) and the various memories (memories no 1, memory no 2 ... memory no n) include the input Ts which allows the delivery of output information for display.
  • a door 35 is made passable and delivers a SPLIT pulse.
  • This pulse is applied to the clock input of a counter 39 having n positions, plus a zero position. At the start, this counter was reset to zero by a pulse on its input r. It is a counter of the type either online or in ring. In the zero position, none of the outputs B 1 to B n carries a signal. When a SPLIT pulse is applied, this counter advances by one row and its output B 1 carries a level “1 a. As can be seen in fig.
  • comparator counter 51 In fig. 2B, there is a comparator counter 51, the details of which are shown in FIG. 3 and will be considered later.
  • This counter has n positions, plus a zero position. It advances by one step each time it receives, on its clock input, a pulse which comes from a pulse former 44. The latter is controlled by the push-button 12, in such a way that it s now is to consider.
  • the push-button 12 can have either its intrinsic function, which of advancing the counter 51 by one step, or an auxiliary function, which is to modify the effects of a pressure on the push-buttons 10 or 11. In this case, its function intrinsic is inhibited.
  • the pusher 12 After passing through a pulse-forming stage 41, the pusher 12 puts a flip-flop 50 in the working position. The output of the latter is applied to an input of an AND gate 43 from which the other input receives the output of an inverter 42, itself also controlled by the push-button 12.
  • the door 43 does not turn on when the output Q of the flip-flop 50 goes to level “1 •.
  • the output Q of the flip-flop 50 activates a uni-vibrator which establishes between its input and its output, a delay of approximately 3 sec for the transition to state "1", the transmission from the transition to the 'state' 0 'being instantaneous.
  • a signal appears at the output of this uni-vibrator 52, and a flip-flop 53 is put in the working position. Its output goes to level "0", and blocks an AND gate 47, which controls a selection 57 of the analog display. In one position, this selector causes the display in field 13 of the chronograph watch, represented at 59 in FIG.
  • this display indicates the date.
  • pressing the switch C for more than 3 seconds causes, during the time it remains pressed beyond these 3 seconds, a temporary switching of the selector 57, which shows the indication of the date instead indication of the rank of the memory whose content is displayed, this being useful for timekeepers.
  • the output Q of the flip-flop 53 is applied to an input of the OR gate 45, so that it returns the flip-flop 50 to the rest state before the switch 12 is released, this which results in the intrinsic function of the latter (advance of one step of the counter-comparator 51) being inhibited.
  • This counter 51 is shown in more detail in FIG. 3. It can be seen in particular that it comprises a “0-n / BCD” converter 120 which delivers information to the aforementioned selector 57, which actuates the digital display 59 via a “BCD / 7 SEGM • 58 converter
  • the other input of the selector 57 receives a BCD signal which comes from a cycle counter of "3", 55, itself receiving a signal from a divider by two 54 which receives, by a switch H, a pulse at each revolution of the hour hand of current time (in 37 fig. 2A).
  • the selector 57 is controlled permanently by a flip-flop 56 which is put in the working position each time either the switch 10 operates (START or SPLIT) or each time the switch 12 operates so as to perform its intrinsic function (output from circuit 44). Furthermore, the flip-flop 56 is returned to the rest state either by the RESET function, resetting all the chronograph circuits, or by the STOP function, provided that at that time the counter- comparator 51 is in the zero position, that is to say controls the display of the basic time counter of the chronograph function and not the display of one of the memories. This reset function of the flip-flop 56 is carried out via an AND gate 40 and an OR gate 40a.
  • the counter-comparator 51 also receives the pulses from SPLIT, just as it receives reset pulses (RESET) or also the pulses from the RESYNCHRONIZATION of the memory, originating from the. AND gate 46. Furthermore, this counter receives information from the state of counter 39, previously considered and used to direct the SPLITS to the various memories.
  • RESET reset pulses
  • RESYNCHRONIZATION the pulses from the RESYNCHRONIZATION of the memory
  • n + 1 outputs of the counter-comparator 51 are applied to the n + 1 groups of inputs TS of the basic counter-memories (zero memories) and of the various memories 1, 2, ... n -1, n. So this is what counter 51 which determines from which memory counter or memory the display will display the content.
  • an input register 111 which simply stores the information received from the counter 39. It also includes an output register 112, which provides the outputs A o ... A n of the counter 51.
  • the input ci of clock pulses each time this counter 112 advances by one step, while the reset input (RZ), as well as the resynchronization input (RM), cause through d 'OR gate 113, resetting this counter 112.
  • This latter comprises a zero position plus n positions, from 1 to n.
  • the input register 111 also includes n positions plus a zero position, although its zero position is only rarely used.
  • the counter-comparator 51 of FIG. 3 includes different doors having different functions.
  • an AND gate 119 receives the SPLIT pulses, just as it receives, delayed by a timer stage 118, the output signal from the zero stage of the counter 112.
  • a level signal “1 appears at the exit of door 119.
  • the latter always includes the information of the rank of the memory having received the last information, if the counter 112 is on zero, a pulse of SPLIT does so automatically move to the position which corresponds to the memory where precisely this SPLIT has just entered a timed time.
  • the passage of the counter 51 to the position 1 is done automatically without requiring pulses on the clock input cl.
  • the counter 51 returns to its zero position and if, for example, a sixth SPLIT intervenes at that time.
  • This sixth SPLIT which will register in the sixth memory, will move the counter 112 to its position 6, which will automatically cause the display of the information contained in the memory no 6, at the same time as the digital display ( 13, 59) will display the number "6".
  • the counter 51 makes it possible to repeat a cycle in order to check recorded timed time values. Its cycle is n + 1. However, if only a small number of splits are recorded, its cycle is shortened so that, to review, for example, six or seven timed times, it is not necessary to pass each time by twenty-five positions of which nearly twenty would be empty. This is why we have the AND gates 115 o.2 , 115 1 , 3 , ... 115 n ⁇ 3 , n ⁇ 1 , 115 n ⁇ 2 , ⁇ . The outputs of all these doors are connected by an OR gate 116, which, via a timer 117, acts on the OR gate 113 for resetting to zero.
  • an input of gate 46 still receives the signal Q, coming from output Q of flip-flop 28, which means that then the function of "memory resynchronization can only take place if the counter is working.
  • the corresponding input of gate 46 is considered to be in the state "1 ' , and" memory resynchronization is also possible when the counter is at rest.
  • the comparator 48 compares the state of the memory display control counter 51 and the state of the counter 39 for controlling the entry of SPLITS into the memories (or of addressing SPLITS into the memories). If the state of the counter 51 is at least as high as the state of the counter 39, this means that all of the stored information has been read at least once and the memories can therefore be resynchronized. If the state of the counter 51 is lower than the state of the counter 39 (if we have for example stored six SPLITS while only four memories have been read), the comparator 48 does not deliver a level signal "1 to at its output, which prevents the operation of the door 46 and therefore prohibits the function of "memory resynchronization". This prevents the risk that timed times will be recorded and lost before being read.
  • the information of hundredths of a second is first applied to an inhibitor circuit 106, at the same time it is applied, by a differentiator 108, to a delay circuit, of the uni-vibrator type, which, for returning to the rest state, exhibits a delay of at least 0.04 sec from the output compared to the entrance.
  • a delay circuit of the uni-vibrator type, which, for returning to the rest state, exhibits a delay of at least 0.04 sec from the output compared to the entrance.
  • circuit 105 will return to the idle state after 0.04 sec, and inhibitor circuit 106 will cease to act, so that the information of hundredths of a second will be applied to comparator 81.
  • comparator 81 does not receive a signal, while it receives the signal of hundredths of a second when the latter is permanent.
  • the comparators 82, 83, 84 compare the setpoint information they receive (TS, TM, TH) with real situation information which they receive from a counter respectively 93, 94, 95.
  • This counter receives a reset pulse when the corresponding needle passes through zero, by mechanical means, by means of contacts R z , R 3 , R 4 . They then receive as many pulses as the motor, which means that their state will be representative of the position of the corresponding needle. If an impulse were to miss its purpose and did not turn the motor rotor, this fault would be quickly eliminated, on the next turn, by the zero crossing contact.
  • the comparators thus compare the real position of the needle with the position that the needle should take, and as long as there is no identity, they give a signal of level "1 on their output Q, which makes pass a carries respectively 85, 86, 87, moreover receiving on another input a clocked signal coming from a timing divider 33 supplied by the frequency divider 22.
  • the frequency of the timing divider will be adapted to the possibilities of the motors, also taking into account inertia of the needles; a frequency of the order of 30 to 50 Hz should be suitable.
  • the setpoint information advances only by one unit at a time, i.e. only one pulse is sent by the corresponding gate, 85, 86, 87, after which the comparator finds already reestablishing coincidence.
  • the gates 85, 86, 87 send a series of pulses.
  • the shaping circuits 97, 98 and 99 put the signals into the shape desired for the actuation of the motors, respectively 102, for the seconds, 103 for the minutes and 104 for the hours.
  • This counter 39 can be an “online” counter which, starting from zero, goes step by step to its last position “n”, then stops, new pulses on its input cl then remaining without effect.
  • this counter could be of the “ring” type, in the sense that a new pulse appearing on the input cl when the counter is already in its last position “n causes the counter to return on position "1 " (but in no case on position "0").
  • a number of SPLITS equal to the capacity “n” of the counter can be recorded, after which the SPLITS (or LAPS) are no longer recorded, unless in the meantime a “memory resynchronization” function was performed, erasing the content of all the memories and bringing the counter to “0”.
  • the recording of a number of SPLITS (or LAPS) greater than the capacity of the counter (corresponding to the number of memories) is possible; assuming for example that there are twenty-five memories and that the 25th memory is already loaded, the next SPLIT (or LAP) will revert to memory no 1, the old content of which will be erased.
  • the timed times n + 1, n + 2, n + 3, etc. will automatically take the place of the old timed contents 1, 2, 3, etc., without it being necessary to carry out a manipulation in the meantime of "resynchronization".
  • the chronograph or the chronograph watch according to the proposed design can also advantageously be produced in the format of a pocket watch.
  • the dial is larger and the various small inner dials, on which the second hand of current time 4, the hand of timed minute 7 and the hour hand of timed time work, would have advantage. to be further from the center than they are in the wristwatch-shaped part shown in fig. 1.
  • a modular arrangement will be used, comprising the stepping motor, the necessary reduction gears and the axis of the needle, forming the point of constructive view a separate subset.
  • This modular arrangement will allow without great difficulty to arrange the aforementioned small dials at a greater or lesser distance from the center depending on whether it will be a piece of wristwatch format or a piece of pocket watch format.
  • the watch could very well be produced in the format of a pocket watch or another format.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
EP84810303A 1983-06-23 1984-06-21 Chronographe électronique, notamment montre-chronographe électronique, analogique, compteur de temps chronométrés Expired EP0130150B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH343583A CH654717GA3 (ja) 1983-06-23 1983-06-23
CH3435/83 1983-06-23

Publications (2)

Publication Number Publication Date
EP0130150A1 EP0130150A1 (fr) 1985-01-02
EP0130150B1 true EP0130150B1 (fr) 1988-03-02

Family

ID=4255905

Family Applications (1)

Application Number Title Priority Date Filing Date
EP84810303A Expired EP0130150B1 (fr) 1983-06-23 1984-06-21 Chronographe électronique, notamment montre-chronographe électronique, analogique, compteur de temps chronométrés

Country Status (5)

Country Link
EP (1) EP0130150B1 (ja)
CA (1) CA1262051A (ja)
CH (1) CH654717GA3 (ja)
DE (1) DE3469614D1 (ja)
WO (1) WO1985000230A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103733145A (zh) * 2011-03-23 2014-04-16 汉密尔顿国际有限公司 用于计算不同阶段的持续期的仪表

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0786538B2 (ja) * 1985-08-28 1995-09-20 カシオ計算機株式会社 ストップウオッチ装置
EP0513429A3 (en) * 1991-05-17 1993-03-17 Ideeja Ohg Parking-time start indicator
DE69936174T2 (de) * 1998-04-21 2007-10-18 Seiko Epson Corp. Uhr und zeitmessverfahren
CH704948B1 (fr) * 2004-02-17 2012-11-30 Lvmh Swiss Mft Sa Montre chronographe électromécanique à affichage rétrograde.
NL1037424C2 (nl) * 2009-10-29 2011-05-02 Atte Nicolaas Bakker Chronograaf.
EP2894523A1 (fr) 2014-01-10 2015-07-15 ETA SA Manufacture Horlogère Suisse Objet portable pour la gestion d'une activité annexe

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3876867A (en) * 1973-03-23 1975-04-08 Murray James W Electronic timer
JPS5452578A (en) * 1977-10-04 1979-04-25 Seiko Instr & Electronics Ltd Stopwatch
JPS5529765A (en) * 1978-08-23 1980-03-03 Akigoro Inoue Order difference conparator
CH627906B (fr) * 1978-11-21 Berney Sa Jean Claude Dispositif d'affichage analogique.
EP0048217A1 (fr) * 1980-09-12 1982-03-24 Compagnie des Montres Longines, Francillon S.A. Pièce d'horlogerie électronique
US4470706A (en) * 1981-03-27 1984-09-11 Citizen Watch Company Limited Analog type of electronic timepiece
CH634713B (fr) * 1981-07-09 Umberto Maglioli Piece d'horlogerie electronique.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103733145A (zh) * 2011-03-23 2014-04-16 汉密尔顿国际有限公司 用于计算不同阶段的持续期的仪表

Also Published As

Publication number Publication date
EP0130150A1 (fr) 1985-01-02
CH654717GA3 (ja) 1986-03-14
WO1985000230A1 (fr) 1985-01-17
CA1262051A (fr) 1989-10-03
DE3469614D1 (en) 1988-04-07

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