EP0100571A3 - Low resistance buried power bus for integrated circuits - Google Patents
Low resistance buried power bus for integrated circuits Download PDFInfo
- Publication number
- EP0100571A3 EP0100571A3 EP83201029A EP83201029A EP0100571A3 EP 0100571 A3 EP0100571 A3 EP 0100571A3 EP 83201029 A EP83201029 A EP 83201029A EP 83201029 A EP83201029 A EP 83201029A EP 0100571 A3 EP0100571 A3 EP 0100571A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- low resistance
- integrated circuits
- power bus
- layer
- buried power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000463 material Substances 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract 1
- 229910052721 tungsten Inorganic materials 0.000 abstract 1
- 239000010937 tungsten Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/404,264 US4503451A (en) | 1982-07-30 | 1982-07-30 | Low resistance buried power bus for integrated circuits |
US404264 | 1982-07-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0100571A2 EP0100571A2 (en) | 1984-02-15 |
EP0100571A3 true EP0100571A3 (en) | 1985-10-30 |
Family
ID=23598889
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP83201029A Withdrawn EP0100571A3 (en) | 1982-07-30 | 1983-07-12 | Low resistance buried power bus for integrated circuits |
Country Status (3)
Country | Link |
---|---|
US (1) | US4503451A (en) |
EP (1) | EP0100571A3 (en) |
JP (1) | JPS5943552A (en) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4683488A (en) * | 1984-03-29 | 1987-07-28 | Hughes Aircraft Company | Latch-up resistant CMOS structure for VLSI including retrograded wells |
US4689656A (en) * | 1984-06-25 | 1987-08-25 | International Business Machines Corporation | Method for forming a void free isolation pattern and resulting structure |
US4631570A (en) * | 1984-07-03 | 1986-12-23 | Motorola, Inc. | Integrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnection |
FR2569055B1 (en) * | 1984-08-07 | 1986-12-12 | Commissariat Energie Atomique | CMOS INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING ELECTRICAL ISOLATION AREAS IN THIS INTEGRATED CIRCUIT |
GB2186424A (en) * | 1986-01-30 | 1987-08-12 | Plessey Co Plc | Method for producing integrated circuit interconnects |
US4980747A (en) * | 1986-12-22 | 1990-12-25 | Texas Instruments Inc. | Deep trench isolation with surface contact to substrate |
FR2616011B1 (en) * | 1987-05-26 | 1989-09-08 | Matra Harris Semiconducteurs | INTEGRATED CIRCUIT WITH UNDERGROUND INTERCONNECTIONS AND METHOD FOR MANUFACTURING SUCH A CIRCUIT |
US4912535A (en) * | 1987-08-08 | 1990-03-27 | Mitsubishi Denki Kabushiki Kaisha | Trench type semiconductor memory device having side wall contact |
GB2212977B (en) * | 1987-11-25 | 1991-01-23 | Marconi Electronic Devices | Semiconductor arrangement |
US4939567A (en) * | 1987-12-21 | 1990-07-03 | Ibm Corporation | Trench interconnect for CMOS diffusion regions |
US5023200A (en) * | 1988-11-22 | 1991-06-11 | The United States Of America As Represented By The United States Department Of Energy | Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies |
DE3931381A1 (en) * | 1989-09-20 | 1991-03-28 | Siemens Ag | Extra interconnect level in silicon integrated circuit - consists of opposite conductivity type from substrate and contacted layers in trenches |
US5248894A (en) * | 1989-10-03 | 1993-09-28 | Harris Corporation | Self-aligned channel stop for trench-isolated island |
US5057895A (en) * | 1990-08-06 | 1991-10-15 | Harris Corporation | Trench conductor and crossunder architecture |
US5196373A (en) * | 1990-08-06 | 1993-03-23 | Harris Corporation | Method of making trench conductor and crossunder architecture |
JP3332456B2 (en) * | 1992-03-24 | 2002-10-07 | 株式会社東芝 | Semiconductor device manufacturing method and semiconductor device |
US5340754A (en) * | 1992-09-02 | 1994-08-23 | Motorla, Inc. | Method for forming a transistor having a dynamic connection between a substrate and a channel region |
US5420061A (en) * | 1993-08-13 | 1995-05-30 | Micron Semiconductor, Inc. | Method for improving latchup immunity in a dual-polysilicon gate process |
JP2684979B2 (en) * | 1993-12-22 | 1997-12-03 | 日本電気株式会社 | Semiconductor integrated circuit device and method of manufacturing the same |
US5849621A (en) * | 1996-06-19 | 1998-12-15 | Advanced Micro Devices, Inc. | Method and structure for isolating semiconductor devices after transistor formation |
US5972758A (en) * | 1997-12-04 | 1999-10-26 | Intel Corporation | Pedestal isolated junction structure and method of manufacture |
US6696746B1 (en) | 1998-04-29 | 2004-02-24 | Micron Technology, Inc. | Buried conductors |
US6025261A (en) | 1998-04-29 | 2000-02-15 | Micron Technology, Inc. | Method for making high-Q inductive elements |
US7045468B2 (en) * | 1999-04-09 | 2006-05-16 | Intel Corporation | Isolated junction structure and method of manufacture |
US6624515B1 (en) | 2002-03-11 | 2003-09-23 | Micron Technology, Inc. | Microelectronic die including low RC under-layer interconnects |
US7102167B1 (en) * | 2002-04-29 | 2006-09-05 | Micrel, Inc. | Method and system for providing a CMOS output stage utilizing a buried power buss |
JP2007194259A (en) * | 2006-01-17 | 2007-08-02 | Toshiba Corp | Semiconductor device, and method of manufacturing same |
US7982284B2 (en) * | 2006-06-28 | 2011-07-19 | Infineon Technologies Ag | Semiconductor component including an isolation structure and a contact to the substrate |
US7691734B2 (en) * | 2007-03-01 | 2010-04-06 | International Business Machines Corporation | Deep trench based far subcollector reachthrough |
US8362660B2 (en) * | 2009-11-09 | 2013-01-29 | Nucleus Scientific, Inc. | Electric generator |
US9245892B2 (en) | 2014-02-20 | 2016-01-26 | International Business Machines Corporation | Semiconductor structure having buried conductive elements |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4037306A (en) * | 1975-10-02 | 1977-07-26 | Motorola, Inc. | Integrated circuit and method |
US4044452A (en) * | 1976-10-06 | 1977-08-30 | International Business Machines Corporation | Process for making field effect and bipolar transistors on the same semiconductor chip |
US4280272A (en) * | 1977-07-04 | 1981-07-28 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for preparing complementary semiconductor device |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3913124A (en) * | 1974-01-03 | 1975-10-14 | Motorola Inc | Integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector including fabrication method therefor |
US4048649A (en) * | 1976-02-06 | 1977-09-13 | Transitron Electronic Corporation | Superintegrated v-groove isolated bipolar and vmos transistors |
JPS5918870B2 (en) * | 1977-05-15 | 1984-05-01 | 財団法人半導体研究振興会 | semiconductor integrated circuit |
US4140558A (en) * | 1978-03-02 | 1979-02-20 | Bell Telephone Laboratories, Incorporated | Isolation of integrated circuits utilizing selective etching and diffusion |
JPS54154979A (en) * | 1978-05-29 | 1979-12-06 | Matsushita Electric Ind Co Ltd | Manufacture of insulated gate type semiconductor device |
JPS55130176A (en) * | 1979-03-30 | 1980-10-08 | Hitachi Ltd | Field effect semiconductor element and method of fabricating the same |
JPS5636143A (en) * | 1979-08-31 | 1981-04-09 | Hitachi Ltd | Manufacture of semiconductor device |
JPS575346A (en) * | 1980-06-13 | 1982-01-12 | Oki Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
JPS5846193B2 (en) * | 1980-07-15 | 1983-10-14 | 株式会社東芝 | semiconductor equipment |
US4339869A (en) * | 1980-09-15 | 1982-07-20 | General Electric Company | Method of making low resistance contacts in semiconductor devices by ion induced silicides |
FR2498812A1 (en) * | 1981-01-27 | 1982-07-30 | Thomson Csf | STRUCTURE OF TRANSISTORS IN AN INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME |
US4435896A (en) * | 1981-12-07 | 1984-03-13 | Bell Telephone Laboratories, Incorporated | Method for fabricating complementary field effect transistor devices |
-
1982
- 1982-07-30 US US06/404,264 patent/US4503451A/en not_active Expired - Fee Related
-
1983
- 1983-07-12 EP EP83201029A patent/EP0100571A3/en not_active Withdrawn
- 1983-07-29 JP JP58139320A patent/JPS5943552A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4037306A (en) * | 1975-10-02 | 1977-07-26 | Motorola, Inc. | Integrated circuit and method |
US4044452A (en) * | 1976-10-06 | 1977-08-30 | International Business Machines Corporation | Process for making field effect and bipolar transistors on the same semiconductor chip |
US4280272A (en) * | 1977-07-04 | 1981-07-28 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for preparing complementary semiconductor device |
Non-Patent Citations (2)
Title |
---|
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 24, no. 9, February 1982, pages 4641-4642, New York, US; H.H. HANSEN et al.: "Self-aligned ion-implanted oxidation barrier for semiconductor devices" * |
TECHNICAL DIGEST OF THE IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 4th-6th December 1978, Washington, page 10, IEEE, New York, US; W. KIM et al.: "Refilled oxide groove isolation technique (ROGI) - A combind isolation and metallization process" * |
Also Published As
Publication number | Publication date |
---|---|
EP0100571A2 (en) | 1984-02-15 |
JPS5943552A (en) | 1984-03-10 |
US4503451A (en) | 1985-03-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Designated state(s): DE FR GB IT NL |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Designated state(s): DE FR GB IT NL |
|
17P | Request for examination filed |
Effective date: 19860428 |
|
17Q | First examination report despatched |
Effective date: 19880118 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 19880201 |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: LUND, CLARENCE A. Inventor name: SUGINO, MICHAEL D. |