EP0095923A2 - Systeme zum Verschleierung von Übertragungen - Google Patents

Systeme zum Verschleierung von Übertragungen Download PDF

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Publication number
EP0095923A2
EP0095923A2 EP83303100A EP83303100A EP0095923A2 EP 0095923 A2 EP0095923 A2 EP 0095923A2 EP 83303100 A EP83303100 A EP 83303100A EP 83303100 A EP83303100 A EP 83303100A EP 0095923 A2 EP0095923 A2 EP 0095923A2
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EP
European Patent Office
Prior art keywords
signals
stores
binary
block
coded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP83303100A
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English (en)
French (fr)
Other versions
EP0095923A3 (de
Inventor
Kenneth Austin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
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Plessey Co Ltd
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Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Publication of EP0095923A2 publication Critical patent/EP0095923A2/de
Publication of EP0095923A3 publication Critical patent/EP0095923A3/de
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04K—SECRET COMMUNICATION; JAMMING OF COMMUNICATION
    • H04K1/00—Secret communication
    • H04K1/06—Secret communication by transmitting the information or elements thereof at unnatural speeds or in jumbled order or backwards

Definitions

  • the invention relates to scrambled communication utilising coded electrical signals such signals normally, but not necessarily, being of analogue type as transmitted but with digitisation and reorganisation before transmission and after reception.
  • the invention has particular envisaged application to communications involving voice signals, whether by radiom for example the so-called “citizens band” systems, or by telephone, or otherwise.
  • signals as transmitted and received are in a coded form wherein components thereof comprising or corresponding (if analogue) to binary words comprise coded reorganisation of original or corresponding (if analogue) binary words according to sequentially different organisations which organisations comprise variable lengths (numbers of binary words) and numbers of blocks of said binary words in variable sequences different from original information order so that said signals are time-different from said original signals.
  • a preferred system is operative relative to storage means for the binary words in blocks read out from storage in a sequence different from sampling order.
  • a plurality of stores may be used, one for each possible block and each usable up to a maximum capacity corresponding to maximum block size.
  • an effectively continuous memory space may be variably partitioned into blocks, if desired retaining the same total number of words in each block arrangement or sequence. It is further preferred that at least some reading out be done in reverse order advantageously to reduce residual intelligibility and add to overall security.
  • each random number determination of number of blocks, of block size and of sequence of readout is preferably accompanied by a following determination relative the complement of such random number(s), so that determination effectively proceeds in pairs of sequences for each random output.
  • a coder/decoder 10 has associated therewith a key code unit 11.
  • the unit 11 serves over lines 12 to control sequences of binary word operation via sequencers 13A, 13B and concerning successive input binary words from lines 14A.
  • Those word operations are shown herein as being sequences representing organisations relative to memories M100 to M115, each organisation comprising a specified number of the memories M100 to M115 and specified effective capacities for those memories M100 to M115.
  • the number of memories for each organisation in a succession of organisations can be in accordance with a set of random numbers, one per organisation per sequence, say ranging from 8 to 16 for the sixteen memories shown. That set of random numbers is readily stored in the sequencer 13A. In fact, several such sets can be so stored in a read- only memory (ROM) component thereof to be selected by the contents of the key code unit, say one field of a key number. Then, it is only necessary for the write routing circuitry to be subjected to a maximum in sequential energisation of the memories M100 to M115 for each random number and the corresponding organisation say via a counter in write-routing circuitry WR.
  • ROM read- only memory
  • the effective capacities of the memories t l 100 to M115 in each organisation is also readily prescribed by a set of random numbers ranging from minimum desired to maximum possible word content of each of the memories. In fact, allowing zero to be specified would enable skipping of memories and thus remove the need for restricting write-routing to a maximum and thus the need for storing the first- mentioned set of random numbers.
  • the contents of each of the memories in each organisation correspond to what we have previously called blocks. If desired, there can be a number of such stored sets of memory capacity determining random numbers equal to the number of organisations (n) in a cyclic sequence thereof. Those stored sets may be permutated or at least varied as to start set according to the input key code, say a field of a key code number, to give different choices for different users. Similar or extended effects are achievable by storing more sets (m) and selecting therefrom and/or using a constant from the key code of a modifier for the random numbers.
  • Control of the memories according to successive random numbers of a set is readily achieved, say via a counter loaded by such numbers in turn, say each after decrementing the preceding one to zero before moving onto enabling the next memory. It is desired that read out from the memories be.in a different order from writing in, and there will normally be different or effectively different sets of random numbers available to the sequencer 13B for controlling the order in which the memories M100 to M115 are read out for each aforesaid organisation of blocks by read out ordering circuitry RO. The latter is readily operative to step from memory to memory by way of pointers recorded therein or in the memories or in the write routing circuitry during storage in the memories.
  • Binary-to-n permutators, binary-to-n out-of-m coders, and counters operative relative to accumulation are all well known, as are shift registers, ring counters, masking techniques, and selective pointer facilities, so that specific implementation of the sequencers 13A, 13B presents no problems in the art, whether to separate random number stores or to the same store for both of the sequencers 13A, 13B.-
  • the key code number will be used as a "seed" for the pseudo-random generator outputs from which will be used to defer active memories, i.e. number of blocks, memory capacities, i.e. block lengths, and order of reading out to define an organisation hereof.
  • active memories i.e. number of blocks, memory capacities, i.e. block lengths, and order of reading out to define an organisation hereof.
  • the last word output of the pseudo-random generator can and/or a partial combination with the original input, say modulo-2, be used as a "seed" for generation of outputs for the next succeeding operation, and there will be no repetitive overall cycle of organisations.
  • a similar logic-circuit based pseudo-random generator will, of course, produce exactly the same outputs for the same input at the same time, i.e. if operated effectively synchronously one at the transmitter and the other at the receiver.
  • the coder/decoder 10 also supplies coded output data words to lines 14B and suitable timing enable circuitry is included for controlling responses of various items hereof so that coding is performed and outputs taken as required, say with the memories M100 to M115 effectively operating as a coding buffer store. An accurate clock is required and such is indicated at C.
  • the input data words are supplied by a latch circuit 15 from an analogue-to-digital converter 16 itself supplied with audio signals via a band-pass filter 17, preamplifier 18 and amplifier 19 from a suitable input such as a microphone to terminal 20 or loudspeaker to terminals 21 according to the state of switch or relay 22.
  • input analogue signals are prepared for amplitude sampling by the analogue-to-digital converter 16, which is conveniently free-running and with appropriate discrimination, say 256 levels for audio
  • the latch 15 will, of course, be sampled at instants appropriate to operation of the coder/decoder 10.
  • a sampling line 28 is shown for that purpose and includes disable/interrupt logic 26 for ensuring that the latch cannot change while it is being sampled and that, otherwise, each change of the analogue-to-digital converter results in a change of the latch. Sampling of the latch is caused by the signal level on branch line 27 and updating thereof by line 28, change of state of the analog-to-digital converter 16 being signalled on line 29.
  • Coded data sigrals from lines 13 are shown applied to a digital-to-analog converter 35 and thence via preamplifier/mixer 36, filter 37 and amplifier 38 to a communications channel 39.
  • the channel 39 may be of a radio type, say the popular CB band radio system, or telephone type, say via an acoustic coupler.
  • a link 40 is shown between the channel 39 and the junction between relay 22 and band-pass filter 17.
  • a link 40 is shown between the channel 39 and the junction between relay 22 and band-pass filter 17.
  • a suitable start synchronisation system could include a plase-locked loop, operative in conjunction with tone generator 46 and start code specifying system 47, though we find that such is avoidable.
  • the main aspect of synchronisation is to ensure that the sequencers at each end are running in step.
  • Basic communication is achieved using a start burst of a prescribed frequency signal from the tone generator 46 at one end. That burst signal is shown injected at 48 after the band-pass filter 17 to mutualise the transmission side, say topped off for that purpose after the amplifier 19 if a phase-locked loop is used.
  • a connection 51 is also shown from the tone generator to the premaplifier and mixer circuit 36 for transmission purposes and resetting of the receiving side.
  • a synchronisation switch 52 will operate the tone generator 46 and cause transmission of a burst of synchronisation frequency whereby the receiving unit is brought into basic synchronism. Entry of the same start code at the receiving unit will place the coder/decoder and sequencer units at the same position in their sequences of codes for the same transmitted signal. That will largely do away with further plase-locked loop type synchronisation especially if any slight log is within an overcapacity of the memory system M 100 to M 115, and there is a preferably unique delay representing a number of nominal cycle times of the coder/decoder 10.
  • the sending of said synchronising signal from the transmitting station to the receiving station starts the coder/decoder delay times at the transmitter and receiver, effectively taking account of whatever is the transmission time over channel 39.
  • Appropriate specification of any desired start code is via the system 47, which may include delay determining means or simply pass the start code to the coder/decoder for calculation of the delay required.
  • the system 47 is shown connected via an interfacer 53 to the coder/ decoder 10 for setting purposes. In a programmed microprocessor system, the interfacer 53 would simply be to a data bus branched to lines 13 and communications between the microprocessor, its data memory and its program store.
  • start code specifying system will include data-entry means, in the form of key switches or touch-sensitive pads, and display means, usually digital. Details of a system suitable for that and other purposes are shown in Figure 2.
  • a display 60 has any convenient number of digits of which seven are indicated by input lines 61 via resistors 62.
  • the lines 62 are shown extending to appropriate ones of input key switches 64.
  • There are eight input key switches 64 which are connected in common over resistor 65 to ground potential and are also connected to junctions 66 with eight lines 67 extending between a tristate interfacer circuit 68 and, via resistors 69, a positive voltage line 70 shown including the synchronisation switch 52.
  • the tristate interfacer 68 is operative to take binary signals from and supply them to lines 71 branched from a data bus 72.
  • the preferred manner of operation is in a normal display mode for data on lines 71 via the interfacer 68.
  • the line 73 is energised to change from normal display mode to write mode, whereupon all of the junctions 66 go to logic-one except for those connected to key switches 14 that are operated, which go to logic-zero level. There will be automatic display at 60 of what has been entered.
  • the key switches 64 when sequentially operated, load digit display segments automatically, such segments being sequentially energised over lines 74. Key entry debounce circuitry is conveniently avoided by employing a program control to effect plural readings of the lines 61 before settling the display, say after ten reads indicate the same result.
  • the purpose of the synchronisation switch 52 is to ensure that transmissions through the interfacer of entered data takes place after the operator is satisfied with such entry. At that time, of course, for the system of Figure 1, the burst of tone generator output will also be triggered. Also, the contents of each digit position of the display 60 will correspond to a key code word/number.
  • a microprocessor based system is even more secure as to synchronisation, as such can be left to program control so long as accurate clocks are used.
  • Suitable overall programming is indicated by way of flow charts in Figures 3 and 4 specific implementation of which relative to any particular microprocessor system will be readily apparent to and achievable by those skilled in programming.
  • the coding system is of a type virtually wholly analogue to the aforementioned pseudo-random number type of operation for Figure 1.
  • the effect is relative to one effectively continuous random access memory space (RAM) that is split up'into varying numbers and lengths of block spaces effectively nose- to-tail and preferably always filling the available or designated total memory space conveniently called a sheeto
  • the sheet will be loaded in "random" specific blocks in a "random" designated order at which readout word-by-word immediately preceding.
  • the degree of security i.e. difficulty of unauthorised decoding
  • the degree of security is extremely high, especially in circumstances where the input key code number is used to start or "seed" the random number generation for the first pair of organisations and the last produced random number is used, preferably on a random basis of combination or not with the original key word, but for the next pair of organisations and so on. Alternate forwards and backwards operations are preferred.
  • FIG. 2 we also show a programmed microprocessor system comprising a microprocessor chip 80 and data memory 81 interconnected by the data bus 72 o
  • a program memory is also shown at 82 connected to an address bus 83 with connections to the data memory 81, the microprocessor chip 80 and to a chip addressing circuit 84 having outputs 85 each for energising a particular chip of the system when such is required to operate according to the program.
  • the program memory 82 will contain the desired procedures for data coding and decoding to be effected by the microprocessor chip 80 using data from the data memory 81.
  • Outputs 85 from the chip address circuit 84 will serve to enable such chip(s) as are required at any one time, and thereby readily separate the various transmission, reception, display and synchronisation functions required.
  • a particular desirable further feature is indicated at 87 which is a delay circuit operative whenever display is specifically required, which may actually be set from the microprocessor itself, see the two connections thereto, or separately.
  • the purpose of the delay circuit is to assist in multiplexing for the display so that the latter is energised appropriately for display purposes.
  • circuitry such as the key switch/display/interfacer of Figure 2 is capable of much wider application, as indeed is the further combination with the microprocessor/data memory/program members/chip address elements of the same Figure.
  • the system of Figure 2 ' is found to be particularly effective in the context of the coding/ decoding communication system of Figure 1.
  • a relay drive circuit 90 that further includes a delay circuit 91 which allows the coder/decoder to complete any actions necessary regarding the current message.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
EP83303100A 1982-06-02 1983-05-31 Systeme zum Verschleierung von Übertragungen Withdrawn EP0095923A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8216137 1982-06-02
GB8216137 1982-06-02

Publications (2)

Publication Number Publication Date
EP0095923A2 true EP0095923A2 (de) 1983-12-07
EP0095923A3 EP0095923A3 (de) 1985-08-21

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ID=10530811

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EP83303100A Withdrawn EP0095923A3 (de) 1982-06-02 1983-05-31 Systeme zum Verschleierung von Übertragungen

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EP (1) EP0095923A3 (de)
CA (1) CA1205540A (de)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2151886A (en) * 1983-12-21 1985-07-24 British Broadcasting Corp Conditional-access broadcast transmission
EP0624013A1 (de) * 1993-05-05 1994-11-09 Zunquan Liu Einrichtung und Verfahren zur Datenverschlüsselung
WO1994026045A1 (en) * 1993-05-05 1994-11-10 Zunquan Liu A repertoire of mappings for a cryptosystem
EP0676876A1 (de) * 1994-04-05 1995-10-11 International Business Machines Corporation Verschlüsselungsverfahren und -einrichtung
DE4425158A1 (de) * 1994-07-16 1996-01-18 Deutsche Bundespost Telekom Verfahren und Anordnung zur Realisierung von kryptologischen Funktionen
GB2386041A (en) * 2002-03-01 2003-09-03 Sensaura Ltd A method of modifying intermittent audio signals such as speech or musical notes in real time
FR2837644A1 (fr) * 2002-10-25 2003-09-26 Canal Plus Technologies Procede de transmission securisee de messages ou de donnees entre deux entites
WO2006107584A2 (en) * 2005-04-05 2006-10-12 Regal Cinemedia Corporation Multi-channel audio switch
WO2008084508A2 (en) * 2007-01-09 2008-07-17 Telecomponenti S.R.L. Digital signal processing method and system employing such method
FR2927493A1 (fr) * 2008-02-08 2009-08-14 Philippe Thorel Procede et systeme de securisation de diffusion de donnees

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2307441C1 (de) * 1973-02-15 1975-05-07 Licentia Gmbh Verfahren zum Verschleiern von Sprachsignalen
FR2379947A1 (fr) * 1977-02-03 1978-09-01 Secre Procede et dispositif de brouillage permettant la discretion dans la transmission d'informations
US4229817A (en) * 1978-04-28 1980-10-21 Datotek, Inc. Portable electronic cryptographic device
WO1983001717A1 (en) * 1981-11-04 1983-05-11 Mccalmont, Arnold, M. Privacy communication system employing time/frequency transformation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2307441C1 (de) * 1973-02-15 1975-05-07 Licentia Gmbh Verfahren zum Verschleiern von Sprachsignalen
FR2379947A1 (fr) * 1977-02-03 1978-09-01 Secre Procede et dispositif de brouillage permettant la discretion dans la transmission d'informations
US4229817A (en) * 1978-04-28 1980-10-21 Datotek, Inc. Portable electronic cryptographic device
WO1983001717A1 (en) * 1981-11-04 1983-05-11 Mccalmont, Arnold, M. Privacy communication system employing time/frequency transformation

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
1980 CARNAHAN CONFERENCE ON CRIME COUNTERMEASURES, 14th-16th May 1980, Lexington, Kentucky, pages 27-37, New York, US; S. UDALOV: "Analog voice privacy with a microprocessor" *
TECHNISCHE RUNDSCHAU, vol. 68, no. 9, 2nd March 1976, page 21, Bern, CH; "Sprachverschleierungsger{t" *

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2151886A (en) * 1983-12-21 1985-07-24 British Broadcasting Corp Conditional-access broadcast transmission
CN1054245C (zh) * 1993-05-05 2000-07-05 刘尊全 数据加密的装置和方法
EP0624013A1 (de) * 1993-05-05 1994-11-09 Zunquan Liu Einrichtung und Verfahren zur Datenverschlüsselung
WO1994026045A1 (en) * 1993-05-05 1994-11-10 Zunquan Liu A repertoire of mappings for a cryptosystem
US5412729A (en) * 1993-05-05 1995-05-02 Liu; Zunquan Device and method for data encryption
US5539827A (en) * 1993-05-05 1996-07-23 Liu; Zunquan Device and method for data encryption
AU693094B2 (en) * 1993-05-05 1998-06-25 Zunquan Liu A repertoire of mappings for a cryptosystem
EP0676876A1 (de) * 1994-04-05 1995-10-11 International Business Machines Corporation Verschlüsselungsverfahren und -einrichtung
US5548648A (en) * 1994-04-05 1996-08-20 International Business Machines Corporation Encryption method and system
DE4425158C2 (de) * 1994-07-16 2003-07-03 Deutsche Telekom Ag Verfahren und Anordnung zur Realisierung von kryptologischen Funktionen
DE4425158A1 (de) * 1994-07-16 1996-01-18 Deutsche Bundespost Telekom Verfahren und Anordnung zur Realisierung von kryptologischen Funktionen
GB2386041A (en) * 2002-03-01 2003-09-03 Sensaura Ltd A method of modifying intermittent audio signals such as speech or musical notes in real time
FR2837644A1 (fr) * 2002-10-25 2003-09-26 Canal Plus Technologies Procede de transmission securisee de messages ou de donnees entre deux entites
WO2004040818A2 (fr) * 2002-10-25 2004-05-13 Canal+ Technologies Procede de transmission securisee de messages ou de donnees entre deux entites
WO2004040818A3 (fr) * 2002-10-25 2004-06-24 Canal Plus Technologies Procede de transmission securisee de messages ou de donnees entre deux entites
WO2006107584A2 (en) * 2005-04-05 2006-10-12 Regal Cinemedia Corporation Multi-channel audio switch
WO2006107584A3 (en) * 2005-04-05 2007-10-04 Regal Cinemedia Corp Multi-channel audio switch
WO2008084508A2 (en) * 2007-01-09 2008-07-17 Telecomponenti S.R.L. Digital signal processing method and system employing such method
WO2008084508A3 (en) * 2007-01-09 2009-01-08 Telecomponenti S R L Digital signal processing method and system employing such method
FR2927493A1 (fr) * 2008-02-08 2009-08-14 Philippe Thorel Procede et systeme de securisation de diffusion de donnees

Also Published As

Publication number Publication date
EP0095923A3 (de) 1985-08-21
CA1205540A (en) 1986-06-03

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