EP0091657B1 - Data transmission apparatus between two asynchronously controlled data processing systems with a buffer memory - Google Patents

Abstract

In order to avoid unambiguous logic switching statuses in a data and control path upon transfer from one clock system of an outputting data processing system into an independent, asynchronous clock system of an accepting data processing system, and wherein a continuous data flow is to be guaranteed at the output of a buffer memory, a control signal indicating the presence of an intermediately stored data word is synchronized into a forwarding timing pattern of the accepting system via a synchronization circuit for forwarding data words from the buffer memory. A forwarding sync control signal is generated by the synchronization circuit. For controlling the in-flow into the buffer memory, a control signal dependent on the forwarding timing pattern of the accepting system is synchronized into the timing pattern of the outputting system over a further synchronization circuit. A request sync control signal is generated which respectively leads to the transfer of a data word together with a strobe signal to the buffer memory which undertakes the intermediate storage on the basis of the strobe signal. In order to guarantee a continuous data flow at the output of the buffer memory, the buffer memory has at least three, and preferably four memory sections.

Description

The invention relates to a data transmission device between two asynchronously controlled data processing systems with a buffer memory constructed from a plurality of memory sections for intermediate storage of one data word each, and two control devices, one of which, as an input control system, synchronously transfers the data word into a system for the takeover available memory section of the buffer memory and the other as output control synchronous with the system clock of the data-recording system controls the forwarding of a data word from a memory section of the buffer memory available for output to the data-recording system.

Corresponding data transmission facilities are described, for example, by IBM Technical Disclosure Bulletin, Vol. 10, No. 1, June 1967, pp. 34-36. A disadvantage of this known arrangement is that data words can possibly be lost during the transmission between the two asynchronously operating systems if an unloading of the buffer memory with an input or a polling signal with a provision in the buffer memory overlap in such a way that the circuit elements concerned are in a logically improperly defined or metastable state in the period critical for the transmission, as is explained, for example, in “Frequency 31 (1977) 3, pages 71 to 76.

Furthermore, GB-PS 917 853 relates to a comparable arrangement. However, it is not clear what the “input synchronization pulse generator” which effects the control pulses for the transfer into the buffer memory comprises. The same applies to the “output synchronization pulse generator” for the call from the buffer memory. The transmission pulses supplied by these pulse generators take effect immediately in accordance with the disclosure given, regardless of whether, for example, a buffered data word is still contained in the receiving buffer section or not or whether a data word is present in the emitting buffer section or not. Nor can it be ruled out in the disclosed circuit that a set and a reset pulse can act simultaneously on the control flip-flops assigned to each buffer memory section, so that the flip-flops can temporarily reach an undefined switching state. The delay elements provided at the output of the flip-flops do not change this, these delay elements merely ensure that when a data word is retrieved from a buffer memory section, the transmission phase does not become too short, since the polling pulse switches itself off by resetting the associated control flip-flop. In contrast, these delay elements can be dispensed with with regard to ensuring the stabilization of the required dwell time due to the existing circuit cycle times. An arrangement of this type therefore does not meet the overall requirements.

Even the arrangement known from DE-AS 27 19 531 does not work satisfactorily in this regard, even if the retrieval by the free buffer memory is correlated with the trailing edge of the individual clock pulses of the system clock of the issuing data processing system.

The object of the invention is therefore to provide a data transmission device of the type mentioned, which works perfectly regardless of the frequency ratio of the two clock systems and yet ensures the most continuous possible data flow at the output of the buffer memory, in each case with a minimal amount of storage space in the buffer memory, especially when the clock frequency of the receiving System is smaller than that of the issuing system.

This object is achieved by the features mentioned in the characterizing part of patent claim 1. Thereafter, at least three memory sections are required in the buffer memory, namely one for providing the data word to be forwarded for the duration of a clock period; one for bridging the synchronization time before forwarding, as long as the necessary synchronization time is at most equal to the clock period of the receiving system, and one for bridging the latching time of a memory request in the supplying clock pattern in the clock pattern of the receiving system. In addition, not only are the control signals triggering the forwarding synchronized into the clock pattern of the receiving system, but also the control signals derived from the forwarding clock pattern are synchronized into the clock pattern of the issuing system, thus excluding metastable states in the entire data and control path. Furthermore, since the control signals to be synchronized into the clock grid of the emitting system are always correlated with a possible forwarding impulse, the point in time from which a memory section is available for accepting a new data word is always fixed, so that in the steady state only one data word is ever present is transferred to the buffer memory if a buffered data word has previously been forwarded. This means that the inflow takes place at a higher clock frequency of the emitting system, controlled with an intermittent clock in the clock pattern of the emitting system with an independent on Adaptation to the maximum data rate caused by the receiving system, without the need for a separate request / acknowledgment system. The resulting time differences are fully absorbed by the memory sections provided in the buffer memory.

• auf die Ableitung der ins Taktraster des abgebenden Systems einzusynchronisierenden Steuersignale, nämlich unmittelbar von den Taktimpulsen des aufnehmenden Systems oder von einem davon abhängigen, den Freizustand wenigstens eines Speicherabschnittes im Pufferspeicher anzeigenden Steuersignal sowie einer Kombination beider Lösungsvarianten,
• auf die Behandlung dieser Steuersignale und die Ausbildung der Synchronisierschaltungen an beiden Enden des Pufferspeichers, insbesondere auch wenn Anforderungen zur Übernahme in den Puffer infolge der notwenigen Einsynchronisierzeiten zu schnell aufeinanderfolgen, sowie auf die notwendige Erhöhung der Anzahl der Speicherabschnitte im Pufferspeicher abhängig von verschiedenen Randbedingungen,
• auf die Ausbildung der Pufferspeicher als normaler Speicher mit voneinander unabhängigen Schreibe- und Lesesteuerungen oder als asynchron arbeitender Nachziehpuffer mit nachgeschalteteter Synchronisierstufe sowie auf die mögliche Teilintegration der Synchronisierschaltungen in die Steuerung des Pufferspeichers,
• auf die Verwendung der Datenübertragungseinrichtung zusammen mit einem Rechner als Daten abgebendes System in Verbindung mit einem weiteren Pufferspeicher und/oder zusammen mit einem zwei Rechner miteinander koppelnden Übertragungssystem mit abweichendem Taktraster.

Based on this basic principle, further claims relate

• the derivation of the control signals to be synchronized into the clock pattern of the emitting system, namely directly from the clock pulses of the receiving system or from a control signal which indicates the free state of at least one memory section in the buffer memory and a combination of both solution variants,
• on the treatment of these control signals and the formation of the synchronization circuits at both ends of the buffer memory, in particular even if requests for transfer to the buffer follow one another too quickly due to the necessary synchronization times, and on the necessary increase in the number of memory sections in the buffer memory depending on various boundary conditions,
• on the design of the buffer memory as a normal memory with independent write and read controls or as an asynchronous pull-up buffer with a subsequent synchronization stage and on the possible partial integration of the synchronization circuits in the control of the buffer memory,
• on the use of the data transmission device together with a computer as a data-emitting system in connection with a further buffer memory and / or together with a transmission system coupling two computers with a different clock pattern.

• Figur 1 ein Blockschaltbild eines ersten Ausführungsbeispieles gemäß der Erfindung,
• Figur 2 ein Blockschaltbild eines zweiten Ausführungsbeispieles gemäß der Erfindung,
• Figur 3 ein Blockschaltbild eines dritten Ausführungsbeispieles gemäß der Erfindung,
• Figur 4 ein Impulsdiagramm zur Erläuterung der Zeitabhängigkeit beim Einsynchronisieren durch die beiden Synchronisierschaltungen,
• Figur 5 ein Belegungsdiagramm der Speicherabschnitte im Pufferspeicher zur Ableitung der Mindestanzahl von Speicherabschnitten,
• Figur 6 ein erstes Ausführungsbeispiel für die Synchronisierschaltungen,
• Figur 7 ein dazugehöriges Impulsdiagramm für impulsförmige, einzusynchronisierende Steuersignale,
• Figur 8 ein dazugehöriges Impulsdiagramm für aus wechselnden Dauersignalen bestehenden. einzusynchronisierenden Steuersignale
• Figur 9 ein zweites Ausführungsbeispiel für die Synchronisierschaltungen
• Figur 10 ein dazugehöriges Impulsdiagramm,
• Figur 11 ein drittes Ausführungsbeispiel für die Synchronisierschaltungen,
• Figur 12 ein dazugehöriges Impulsdiagramm,
• Figur 13 das Blockschaltbild für ein erstes Ausführungsbeispiel des Pufferspeichers
• Figur 14 ein dazugehöriges Impulsdiagramm,
• Figur 15 ein Blockschaltbild eines weiteren Ausführungsbeispieles des Pufferspeichers,
• Figur 16 ein dazugehöriges Impulsdiagramm,
• Figur 17 ein Blockschaltbild für die Kopplung zweier Rechner durch ein Übertragungssystem mit eigenständigem abweichendem Systemtakt bei Verwendung der Datenübertragungseinrichtung gemäß der Erfindung in Verbindung mit einem weiteren Pufferspeicher und
• Figur 18 ein Blockschaltbild eines zusätzlichen Pufferspeichers auf der Empfängerseite des Übertragungssystems gemäß Fig. 17.

Further details of the invention in this context will be explained in more detail with reference to exemplary embodiments shown in the drawing. Show in detail

• FIG. 1 shows a block diagram of a first exemplary embodiment according to the invention,
• FIG. 2 shows a block diagram of a second exemplary embodiment according to the invention,
• FIG. 3 shows a block diagram of a third exemplary embodiment according to the invention,
• FIG. 4 shows a pulse diagram to explain the time dependency during synchronization by the two synchronization circuits,
• FIG. 5 shows an allocation diagram of the memory sections in the buffer memory for deriving the minimum number of memory sections,
• FIG. 6 shows a first exemplary embodiment for the synchronizing circuits,
• FIG. 7 shows an associated pulse diagram for pulse-shaped control signals to be synchronized.
• Figure 8 is an associated pulse diagram for consisting of changing continuous signals. control signals to be synchronized
• Figure 9 shows a second embodiment for the synchronizing circuits
• FIG. 10 shows an associated pulse diagram,
• FIG. 11 shows a third exemplary embodiment for the synchronizing circuits,
• FIG. 12 shows an associated pulse diagram,
• Figure 13 shows the block diagram for a first embodiment of the buffer memory
• FIG. 14 shows an associated pulse diagram,
• FIG. 15 shows a block diagram of a further exemplary embodiment of the buffer memory,
• FIG. 16 shows an associated pulse diagram,
• FIG. 17 shows a block diagram for the coupling of two computers through a transmission system with an independent, different system clock when using the data transmission device according to the invention in connection with a further buffer memory and
• FIG. 18 shows a block diagram of an additional buffer memory on the receiver side of the transmission system according to FIG. 17.

Fig. 1 gives an overview of the data transmission device, consisting of a buffer memory PUF with four individual registers R3 to RO and the buffer memory controller P-ST for writing in the data words DAT transmitted by the data processing system SYST1 depending on accompanying strobe signals STR in individual registers R3 to RO and for that Reading out and forwarding the buffered data words DAT to the receiving data processing system SYST2 and the two necessary synchronization circuits SYN1 on the input side and SYN2 on the output side of the buffer memory PUF.

Both data processing systems SYST1 and SYST2 work asynchronously with each other with different system clocks f1 and f2 and can represent arbitrarily operating systems, e.g. B. an independently working data memory with rigid write and read cycles or a computer or a transmission system with a transmission channel coupled by transmitting and receiving devices.

Both synchronization circuits SYN1 and SYN2 work in such a way that a supplied control signal st or dv is incorporated or latched into the respective system clock pattern f1 or f2 and then delayed by a time period excluding metastable states as a synchronous control signal f1 'or wl in the respective system clock pattern takes effect and triggers the data transfer or forwarding.

In the exemplary embodiment according to FIG. 1, the control signal st for the synchronizing circuit SYN1 is derived directly from the clock pulses of the system clock f2, which simultaneously trigger the forwarding of a buffered data word. Even if the buffer memory PUF should be filled at this time, it will have a free memory section due to the simultaneous release of a memory section for a data word that has already been forwarded, when the next data word from the remote system SYST1 is supplied. The effort for buffer memory sections is the least in this case, since the storage is done solely by the clock pulses of the recording. System is dependent. However, depending on the frequency ratio of the two clock systems f1 and f2 and on the necessary synchronization times, there is a more or less pronounced time delay between the clock pulse of the clock system f2 triggering the first data word transfer and the actual appearance of this data word at the output of the buffer memory PUF. In contrast, in the steady state with a continuous data flow at the output of the buffer memory PUF at a maximum data rate caused by the clock system f2 of the receiving system SYST2, the memory capacity of the buffer memory is almost fully utilized.

Another solution variant is shown in FIG. 2, in which the control signal st for the synchronization circuit SYN1 on the input side is freely dependent on a signal indicating the availability of a predetermined number of free memory sections, the leading edge of which occurs synchronously with the clock pulses of the clock system f2 of the receiving system SYST2 and thus also represents a control signal dependent on the forwarding clock pattern f2. As a result, in contrast to the exemplary embodiment according to FIG. 1, when the signal is present, data words DAT are continuously entered into the buffer memory PUF continuously with successive clock pulses of the clock pattern f1 until the signal is omitted, and thus the buffer memory is faster with one a continuous data flow at the output of the buffer memory securing number of data words is filled. The trailing edge of the signal free, however, always appears in sync with the clock pulses of the other clock system f1. As a result of the delay caused by the synchronization circuit SYN1, which is normally caused on both signal edges, free memory sections must be reserved in the. Buffer memory PUF, since, due to the delayed effect of the blocking, additional data words DAT can be delivered in the meantime, which the buffer memory PUF must take over without loss.

The number of memory sections to be reserved for this depends on the relevant time conditions. Roughly speaking, at least two memory sections must be kept free, namely one for waiting for the latching into the clock system f1 and one for bridging the metastable switching state after the latching. The signal free must therefore inevitably be terminated before these reserved memory sections are occupied and can only occur if at least n + 1 memory sections are free with n reserved memory sections. Accordingly, at least five memory sections would have to be provided in the buffer memory PUF.

As a result of the delayed appearance of the reappearance of this signal, the buffer memory is temporarily emptied more than is necessary, so that the filling level constantly oscillates around the memory section freely determining the signal and the capacity of the buffer memory is therefore not optimally used.

Reserving memory sections that are normally to be provided in addition. However, if the trailing edges of the signal become effective immediately, which will be explained later, it can be dispensed with, so that it can be left with the original minimum number of memory sections in the buffer memory PUF.

A further solution variant, which consists of a combination of the two solution variants according to FIG. 1 and FIG. 2, is shown in FIG. 3. In this case, the control signal ST is derived both directly from the clocks of the clock system f2 and indirectly from the signal that controls a multiplexer MUX. As long as the signal is free, the clock pulses of the clock system f2 are blocked and instead a continuous signal + is supplied to the synchronizing circuit SYN1 as a control signal st, so that until the signal disappears initially, as in the exemplary embodiment according to FIG. 2, with successive clock pulses of the clock system f1 data words DAT be filled into the PUF buffer memory. The clock pulses of the other clock system f2 then control the inflow, as in the exemplary embodiment according to FIG. 1.

The same applies to the reservation of free storage spaces as in the exemplary embodiment according to FIG. 2, but in this case there is no pendulum effect, since after the buffer store PUF has filled up for the first time, the clocks of the forwarding clock pattern f2 control the inflow synchronously with the outflow. If the termination of the control signal were also made dependent on the occupancy of a single memory section in the buffer memory PUF, one could also leave it at the original minimum number of memory sections in the buffer memory, since at least two free memory sections are still available after occupying a memory section.

Which of the three previously described exemplary embodiments is best to be used in the individual case depends to a large extent on the boundary conditions to be fulfilled, some of which will be explained in more detail below.

First, the essential time relationships when synchronizing one from the one clock grid, e.g. B. f2, derived request in the other clock pattern, e.g. B. f1 explained. For this purpose, with reference to the synchronization circuit SYN1 on the input side of the buffer memory PUF according to FIG. 1 to FIG. 4, the four relevant pulse sequences f1, f1 ', STR and f2 specified. It is assumed that two rigidly coupled cycles for writing S and reading L of a memory system run in the clock pattern f1 with the period t ₁ during each period and that the strobe pulses STR characterizing a data word DAT to be recorded by the buffer memory are respectively out of phase with the actual clock pulses of the clock matrix f1 occur. So that a request triggered by a clock pulse of the forwarding clock pattern f2 leads to reading and transfer of a data word to the buffer memory PUF, the following times must first be waited for: t _RAST1 as the waiting time from the request until the next clock pulse of the responsible system clock f1, t _SYN1 as a delay time for bridging metastable states and t _ZUC as a waiting time until the next possible start of the reading cycle, the sum of all three partial time periods being designated T _ON .

Depending on the phase position between the clock pulses of both clock rasters f1 and f2, the part-time t _{RAST1 can fluctuate} in the range between 0 and t ₁ , while the part- _times t _SYN1 and t _ZUG - once defined - are each constant.

In the present case, the part-time t _{SYN1 is selected to be} equal to the period t ₁ , but it can be smaller or larger as required and thereby determines the part-time t _ZUG . The course of the part-time t _SYN1 in each case triggers a clock-synchronous request pulse f1 ', which then results in a strobe pulse STR after the part-time t _{ZUG has} elapsed with the transfer of the read data word DAT.

The allocation of a memory section in the buffer memory PUF thus always leads to a control signal dv, which is synchronous with the clock pulses of the emitting system f1, for the other synchronization circuit SYN2 and which is to be synchronized into the other clock system f2. In this case, t _RAST2 a waiting time from the time it is occupied until a clock pulse occurs in the clock system f2 and with t _SYN2 a delay time for bridging the metastable states must be waited until the temporarily stored data word can be finally forwarded with a signal wl triggered during the subsequent clock pulse of the forwarding clock pattern f2. A considerable amount of time passes between the request of a data word and its actual forwarding, namely T _off . In this case too, the part-time t _{SYN2 is} again chosen equal to the period t2. It can also be smaller or larger. If the partial time t _SYN2 differs from the integer multiple of the period t ₂ , a point in time which is different from the time of the occurrence of the clock pulses in the clock pattern f2 and is determined by clock pulses of a shifted clock pattern must be selected such that the end of the part time t _SYN2 with the respective subsequent clock pulse ends in the original clock pattern f2. The phase shift of both synchronous clock grids then corresponds to the part-time t _SYN2 , only that the forwarding of the respective data word can begin in _good time with each clock pulse of the original clock grid. In any case, the part-time t _RAST2 can be between 0 and the period t ₂ up to the rest times defined by the pulses of the phase-shifted snap-in _{raster that} start the part-time t _SYN2 . The total time T _ON on the input side could be shortened in an analogous manner, in particular also by shortening the part time t _{ZUG '} . As long as the boundary conditions permit, however, it appears expedient to _{measure the partial times} t _SYN1 and t _SYN2 equal to the period t ₁ and t ₂ , since this is less expensive.

Fig. 5 illustrates the effects of the total times T _ON and T _OFF on the minimum number of memory sections R ... required for the buffer memory. For this purpose, four memory registers RO to R3 are shown, in which the data words A to D are written with S and with L are released for forwarding for the duration of a period t ₂ . As long as t _SYN2 does not exceed the period t ₂ , three memory _sections are sufficient regardless of T _ON . However, in order to be able to intercept phase fluctuations when T _ON approaches an integer multiple of the period t ₂ , an additional memory section is required, ie a total of four memory sections. If, on the other hand, the part-time t _{SYN2 exceeds} the period t ₂ , the minimum number of memory _{sections must} also be increased, namely by one memory section per extension by one period t ₂ .

Fig. 6 shows the basic structure of the synchronization circuits SYN1 and SYN2. In a manner known per se, an RS flip-flop catches the signal st to be synchronized as a catch flip-flop FA-FF, which is then transferred to the synchronizing flip-flop SYN-FF with the trailing edge of the subsequent clock pulse in the decisive clock system f1 and thus “latches”. Delayed by the partial time t _SYN1 , the output signal of the synchronization _flip-flop SYN-FF is then evaluated via an AND _gate U1 with a clock pulse. At t _SYN1 = t ₁ it is a further pulse of the clock pattern f1, which then supplies an output pulse f1 ', which at the same time resets the catch flip-flop FA-FF via the AND gate U2.

An associated pulse diagram is shown in FIG. 7 for a control signal st consisting of individual pulses A and B. From this it can be seen that pulses of the control signal st to be synchronized only lead to a corresponding output pulse f1 'if the distance t ₂ between the control pulses A and B to be synchronized is sufficiently large so that the catch flip-flop FA-FF can be reset in good time. The condition t ₂ ≥ 2t ₁ must therefore be met at t _SYN1 = t ₁ . Would, on the other hand, be compared to the selected If the distance t _{2 is} halved, which is indicated by the dashed intermediate pulse at time X and thus does not meet the time condition to be complied with, this requirement would be suppressed since the catch flip-flop FA-FF has not yet been reset. For these cases, special circuits are therefore required, which will be explained later.

The associated pulse diagram shown in FIG. 8 differs from that of FIG. 7 by the fact that the signal st to be synchronized consists of longer-lasting control pulses which represent a sequence of requirements and for the entire effective duration output pulses f1 'synchronous with the clock pulses trigger the determining clock system f1, as required by the exemplary embodiments according to FIGS. 2 and 3. In this case too, the resetting of the catch flip-flop FA-FF is delayed with respect to the end of the control signal st, so that when changing over to the clock pulses of the other clock system f2 according to the exemplary embodiment in FIG. 3, the next possible request pulse of the control signal st is suppressed, if necessary will occur if it occurs between the two time limits G1 and G2, as indicated by dashed lines at time X. In this case, too, special switching measures must be taken so that the synchronizing circuits SYN1 and SYN2 work properly.

Fig. 9 shows a first embodiment of such an additional synchronizing circuit, which differs from that of Fig. 6 essentially in that two simple synchronizing arrangements are provided in parallel to each other and via an upstream divider circuit, for. B. in the form of a flank-controlled flip-flop T-FF, alternately activated with each incoming request pulse st / f2, the signal outputs of both synchronization arrangements being combined via an OR gate 011.

10 shows an associated pulse diagram for pulse-shaped individual requests A to F in the clock pattern f2, which are to be synchronized into the clock pattern f1. The same applies to requests from continuous pulses according to Fig. 8. This pulse diagram further illustrates how, depending on the frequency response and the respective phase position of both clock rasters f1 and f2 in adaptation to the possible maximum data flow rate of the forwarding clock raster f2, the inflow into the buffer memory controlled by the synchronized control pulses f1 'is regulated independently. Thus, the first four successive request pulses A to D in the clock pattern f2, after the respective latching and delaying, lead directly to successive corresponding output pulses A 'to D' in the clock pattern f1, while between the output pulses D 'and E' there is another and dashed at time X. indicated output pulse is suppressed without a request is lost.

Fig. 11 shows another solution variant for the synchronizing circuits SYN1 and SYN2 to cope with requests that are too fast consecutive, in which the synchronizing flip-flop SYN-FF is preceded by two series-connected capture flip-flops FA-FF2 and FA-FF1, the first of which is immediately connected after forwarding a request to the subsequent catch flip-flop FA-FF1, it is reset again and is thus available for the next request, although the previous request may not yet have engaged and the actual catch flip-flop FA-FF1 is not yet free again. Delay elements VZ1 and VZ2 for the feedback of the output signals of the two catch flip-flops on their control inputs in the manner shown prevent the respective input signals from being blocked too early and the catch flip-flops from being able to reach defined states.

The mode of operation of this arrangement also results from the associated pulse diagram of FIG. 12. If the catch flip-flop FA-FF1 is free, a request received by the input flip-flop FA-FF2, for example pulse A and E, is immediately sent to the other catch flip-flop FA- FF1 forwarded and thus the input flip-flop released slightly delayed. If, on the other hand, the catch flip-flop FA-FF1 is still occupied, the output signal of the set input catch flip-flop FA-FF2 cannot be forwarded due to the still blocking of the AND gate U2 (FIG. 11) and the input catch flip-flop FA-FF2 remains set until a transfer the request to the following catch flip-flop FA-FF1 is possible - so with the request pulses B to D and F in the clock pattern f2. The corresponding output pulses A 'to E' of the control signal f1 'in turn follow isochronous with the clock pulses of the integration clock f1, whereby in order to adapt to the maximum data flow rate in the clock pattern f2, clock pulses of the clock pattern f1 for the control signal f1' may be suppressed, as at time X is indicated by the dashed impulse.

A first exemplary embodiment of a buffer memory PUF will now be described with reference to FIG. 13. This consists of four individual registers RO to R3, into which the supplied data words DAT are accepted with a write signal SS from a common data rail and from which they are forwarded with a read signal LS via a common data rail. If the registers RO to R3 are designed in such a way that the information content is only changed when the register is stored, the read signals LS correspond to the control signals for a selection circuit, for example a multiplexer, which connect the outputs of the respectively selected registers to the common output.

The takeover of the data words DAT delivered by the issuing system SYST1 and their forwarding to the receiving system SYST2 is controlled by the common buffer memory controller P-ST, namely the takeover depending on the strobe signals STR supplied with the data and the forwarding depending on the clock pulses of the clock pattern f2 im receiving system SYST2. The associated synchronization circuit SYN2 is full and the synchronization circuit SYN1 on the input side of the buffer memory PUF is only partially integrated in the control P-ST.

The structure of the control P-ST and the synchronization circuit SYN2 is divided into subcircuits of the same structure, one of which is provided for each register RO to R3. These subcircuits each have a trailing edge-controlled input or start flip-flop SO to S3, of which only one is set at a time and displays the respective register as an input address pointer. These flip-flops are therefore interconnected to form a kind of ring shift register, which is clocked by the strobe pulses STR, a pointer bit entered via one of the set inputs S circulating in a ring. To close the ring, an AND gate US is provided, the three inverted signal inputs of which are each connected to one of the direct signal outputs of the first three flip-flops SO to S2 in the ring, so that they can only be forwarded to the first flip-flop SO in the ring if the first three flip-flops SO to S2 are not set. One of the AND gates U10 to U13 is connected to the direct signal outputs of these flip-flops SO to S3, the further signal input of which is connected to the input for the strobe pulse STR, so that an incoming strobe pulse STR only in connection with one of the set flip-flops SO to S3 via one of the AND gates, e.g. B. U10, take effect and thus an input characterizing a data word DAT switching element, for. B. EINO, in the form of an RS flip-flop via the controlled AND gate, z. B. U10, set and can trigger the write signal for the selected register, that is R0.

The set outputs of the input switching elements EINO to EIN03 are each followed by one of the AND gates U20 to U23, which, instead of an address pointer working according to the FIFO principle for forwarding, identify the register with the data word that was first stored and thus to be forwarded again by each set output the input switching elements, e.g. B. EINO, which is the downstream input switching element, z. B. EIN1, assigned AND gate z. B. U21, blocks. Of the four outputs of these AND gates U20 to U23, only one can take effect at a time and initiate the forwarding of the temporarily stored data word DAT with the control signal dv as the read address in the (1-out n) code.

For this purpose, the control signal dv is each fed to one of the following synchronization flip-flops SYNO to SYN3, which are clocked by the clock pulses of the forwarding clock pattern f2 and, after the partial time t _SYN2 , which in the present case is equal to the clock period t ₂ , a subsequent output _{switching element} , for example AUSO, set t ₂ for the entire duration of a cycle period. At the same time, for example, via an associated AND gate briefly controlled by the clock pulses, e.g. B. U30, the associated input switching element, so EINO, reset.

The output signals of the output switching elements corresponding to the control signal wl then cause the outputs of the associated register, for. B. R0, on the forwarding data rail.

Each of the registers RO to R3 of the buffer memory PUF is also assigned one of the occupancy switching elements BELO to BEL3, which are designed as RS flip-flops and each of the set output of the associated input switching element, ie z. B. EINO, are set and thus the state of charge of the associated register, z. B. R0. They are therefore only reset at the end of the associated forwarding period, ie by a period t ₂ later than the input switching elements ON ..., which in turn takes place via one of the AND elements U40 to U43 in connection with a clock of the forwarding clock pattern f2. The resetting of the input switching elements ON ..., which occurs one clock period t ₂ earlier, ensures that the next control signal dv is incorporated into the clock pattern f2 in good time in order to enable a continuous data flow.

The synchronization circuit SYN2 required at the output of the buffer memory PUF is thus completely integrated in the output control of the buffer memory. Separate catch flip-flops are not required, since the input switches EINO to EIN3 connected upstream already fulfill their task. If longer part _times t _SYN2 than the selected clock period t _{2 are to be} observed, the synchronizing flip-flops SYNO to SYN3 would have to be replaced in a manner known per se by appropriate circuits, for example by a cascade of several synchronizing flip-flops, as is also the case, for example, with the synchronizing flip-flops, e.g. . B. SYNO, and the output switching elements, for. B. AUSO, form.

As already mentioned in connection with FIG. 2, the synchronization circuit SYN1 assigned to the input side is driven with a control signal st derived from the free state of at least one of the registers R0 to R3 in the buffer memory PUF. For this purpose, the set output signals of the occupancy switching elements BELO to BEL3 are inverted and combined via an OR gate 02 to form the signal st ', which acts as an already captured control signal st on a synchronization flip-flop SYN-FF, which is clocked with the clocks of the other clock system f1 and via one downstream AND gate U5 as shown in FIG. The supplies f1 'synchronized in the system SYST1.

So that the storage capacity of the buffer memory, which in the present case is limited to four memory sections, is sufficient, use was made - as already briefly indicated in connection with FIGS. 2 and 3 - of the instantaneous effect of the trailing edge of the control signal st '. That is, as soon as the buffer memory PUF is filled and the control signal st 'becomes zero, the synchronizing flip-flop SYN-FF is immediately reset via the inverted reset input R, so that two clock pulses of the clock system f1 are required, so that a request pulse f1' at the output again the synchronization circuit SYN1 appears, which will be explained later on in the associated pulse diagram.

In particular in connection with a data transmission system with continuous data, which forms the receiving system SYST2. flow with insufficient number of data words, DAT to maintain the data flow by inserting filler words, the set output signals of the output switching elements AUSO to AUS3 are inverted and combined via an AND gate U6, which supplies a signal FW to insert a filler word if no data word DAT is temporarily stored and is pending transmission.

In addition - if necessary - from the outputs of the AND gates U30 to U33 via an OR gate or - as indicated by dashed lines - from the outputs of the synchronization flip-flops SYNO to SYN3 and a subsequent AND, which is briefly released by the clock pulses of the clock system f2 Member U7 an output strobe signal STR 'corresponding to the input strobe signal STR can be derived.

FIG. 14 shows the associated pulse diagram, whereby, based on FIG. 4, it is again assumed that the strobe pulses STR lag the clock pulses in the clock pattern f1 and the synchronized request pulses f1 'by half a clock period t1. With the incoming strobe pulses STR, the individual start flip-flops SO to S3 take effect cyclically one after the other and set the input switching elements EINO to EIN3 connected downstream of them, which cyclically start the synchronization flip-flops SYNO to SYN3 via the AND elements U20 to U30. Of these, after a delay of one clock period t ₂ , the output switching elements AUSO to AUS3 are set for the duration of a clock period t ₂ , which mark the duration of the forwarding of a data word DAT with the read signal LS. Below these pulse sequences, the assignments of the individual registers RO to R3 with the successive data words A to K are specified, the forwarding period for each data word DAT being identified by LS and the non-occupied periods being hatched.

Each of the data words DAT is then immediately adopted in one of the registers RO to R3. The forwarding periods (LS) follow one another without interruption, so that there is a continuous data flow at the buffer output without the risk of any data loss due to the metastable states of the flip-flops involved due to signal intersections. At the same time, the data flow rate on the input side of the buffer memory PUF is automatically adapted to the maximum data flow rate on the output side. The latter takes place in the context of the synchronization circuit SYN1 through the inverted output signals of the assignment switching elements BELO to BEL3, the switching states of which are shown below the register lines RO to R3.

As long as not all occupancy switching elements BELO to BEL3 are set, there is still space in the buffer for receiving a data word and the control signal st 'indicates the free state, with the result that after the synchronization flip-flop SYN-FF is set, each clock pulse in the clock pattern f1 results in a request pulse f1 ' becomes. However, if, even if only for a short time, all registers are occupied, for example with the transfer of data word E, the synchronization flip-flop SYN-FF is immediately reset and the next clock pulse in the clock pattern f1 of the emitting system does not lead to a request pulse, to Example at times X and Y, since the synchronization flip-flop SYN-FF must first be set again. As a result, no strobe pulse STR can follow in the respectively started clock period t. A data word gap arises in the data inflow, which is identified in the top line by an sf. The buffer memory can never overflow.

15 shows a further, less complex exemplary embodiment of a buffer memory PUF with control P-ST together with the two synchronization circuits SYN1 and SYN2. This buffer memory also has four individual registers RO to R3, which, in contrast to the previous exemplary embodiment, are run through in succession in reverse order by the data words DAT supplied by the issuing system SYST1. The first three individual registers R3 to R1 form an asynchronous "pull-down buffer", in which the data words DAT are forwarded step by step in succession to the individual register that is currently free. The last individual register RO of the series circuit works as a synchronous or single-phase register for the receiving system SYST2 depending on the synchronizing circuit SYN2.

The recording and forwarding of the individual data words DAT is again carried out by the controller P-ST, which evaluates the strobe signal STR supplied in each case. Within this control P-St, each of the asynchronously operating registers R1 to R3 is a control switching element, e.g. B. in the form of an RS flip-flop K-FF1 to K-FF3, assigned, which is set when a data word is buffered in the associated single register. Each set input of the control switching elements K-FF1 to K-FF3 is one upstream of the AND gates U1 to U3, the inverted second signal input of which is connected to the set output of the associated control switching element via one of the delay elements VZ11 to VZ31, while from the output of these AND gates in addition to the set signal for the associated control switching element K-FF ... a reset signal delayed by one of the delay elements VZ22 to VZ32 for the respective upstream control switching element K-FF ... is tapped. The three control switching elements K-FF1 to K-FF3 thus form a series connection, which are set in succession by a strobe pulse STR and are reset each time the data word temporarily stored in the associated register is forwarded. The takeover clocks ÜT for the registers are identical to the setting signals for the associated control switching element K-FF ...

For safety reasons, the first AND gate U3 of this series circuit is preceded by an RS flip-flop, which is not always required, as a catch flip-flop FF-FA, via a delay element 42 connected to the output of the AND gate U3 and an AND gate 4 for blocking the reset, as long as the input strobe STR is still effective, can be reset.

The set outputs of all control switching elements K-FF1 to K-FF3 and the input flip-flop FA-FF are combined via an OR element 01, the output signal dv 'of which corresponds to the presence of temporarily stored data and already caught control signal dv, which is generated by the synchronization circuit SYN2 in the clock grid f2 of the receiving system SYST2 is to be synchronized and leads to the signal wl as a transfer clock ÜT for the synchronous register RO. In the present case, the synchronizing circuit consists solely of the synchronizing flip-flop SYN-FF1 and the downstream AND gate U5, since the upstream RS flip-flops already fulfill the function of the catching flip-flop and the delay time t _SYN2 in turn corresponds to the clock period t ₂ . The OR gate 01 ensures that the forwarding of buffered data words can take place continuously in the clock pattern of the receiving clock system f2, especially in the case of even longer synchronization times, without gaps in the data flow because the entire synchronization time in the last asynchronous register R1 of the series must be waited for . Another synchronizing flip-flop SYN-FF2 is connected in series with the synchronizing flip-flop SY-N-FF1, which is also clocked with the trailing edge of the clock pulses of the forwarding clock pattern f2 and which indicates whether a data word is being forwarded or not. In some applications, this can in turn be used to insert fill words into the data stream due to the FW signal in the absence of data words to be forwarded. In addition, an output strobe signal STR 'corresponding to the input strobe signal STR' can be derived from the forwarding signal w1, if necessary.

The control signal st for the control of the synchronization circuit SYN1 on the input side of the buffer memory is derived in an analogous manner to the previous exemplary embodiment according to FIG. 13 from the occupancy state of the buffer memory PUF, in the present case only the setting state of the first control switching element K-FF3 of the chain being decisive , whose set output signal is inverted and controls the synchronizing flip-flop SYN-FF3 of the synchronizing circuit SYN1 as the already captured control signal st '. In order to prevent a mere passage of the associated register R3 resetting the synchronization flip-flop SYN-FF3, the set output signal is also delayed by the delay elements VZ31 and VZ5 and also inverted with the undelayed set output signal via an OR element 02 combined to form the control signal st '. The delay is dimensioned such that the delayed signal only takes effect when the undelayed signal has normally subsided again and therefore a brief interruption of the undelayed signal is bridged by the delayed signal for a predetermined period of time. Only when the interruption of the undelayed signal has not yet ended after this period of time is the synchronization flip-flop SYN-FF3 reset and thus intervenes in the normal data flow control.

FIG. 16 shows the associated pulse diagram, which is constructed similarly to that of FIG. 14. Incoming strobe pulses STR set the catch flip-flop FA-FF and the subsequent control switching elements K-FF3 to K-FF1 if none of the registers R3 to R1 is occupied. Correspondingly, a supplied data word DAT, for example A, is successively forwarded successively via registers R3 and R2 into register R1, where it remains stored until it is transferred to the last register RO for forwarding after the part-time t _{SYN2 has snapped} in and expired. With the passing on of a data word DAT to the following register, the associated control switching elements, e.g. B. K-FF3 and K-FF2 reset again, so that the control switching elements are only set for a short time with a free subsequent register. With several successive data words e.g. B. A to E, the control switching elements successively go into a longer set state, with the result that after the transfer of the data word E, the control switching element K-FF3 is still set when the delayed output signal becomes effective via the delay element VZ5, so that Control signal st 'interrupted and the sync flip-flop SYN-FF3 is reset. As in the exemplary embodiment according to FIG. 13, the result is a suppression of the possible request pulse f1 'at the point in time X and thus a suppression of the strobe pulse STR in progress Clock cycle, which in turn is identified by an sf in the first line.

The two exemplary embodiments explained with reference to FIGS. 13 and 15 represent special cases in comparison to the solution variants explained with reference to FIGS. 1 to FIG. 1, which are particularly characterized by the at least partial integration of the synchronization circuits SYN1 and SYN2 in the control P-ST of the Buffer memory PUF, whereby in the exemplary embodiment according to FIG. 13 at the same time a duplication of the synchronization arrangements according to the arrangement of FIG. And in the exemplary embodiment according to FIG. 15 from a series connection of catch flip-flops according to the arrangement of FIG. 11 in the form of the series-connected control switching elements K- FF ... is used for the synchronization circuit SYN2. On the other hand, the instantaneous resetting of the synchronizing flip-flop SYN-FF in the synchronizing circuit SYN1 prevents a reservation of free registers when the buffer memory is full, which would otherwise also be necessary due to the delay of the trailing edge of the control signal st. This delay of the trailing edge can be omitted without hesitation, since the trailing edge of the control signal st 'is already generated synchronously with the clock pattern f1. On the other hand, the delay of the newly synchronized leading edge of the control signal st 'becomes obvious, since in the present case at T _{SYN =} t _1, up to two clock periods t ₁ can in the worst case elapse until the next data word, e.g. B. F or K is delivered. However, this reaction time is of no further importance if enough data words are still buffered so that the continuous flow of data at the output of the buffer memory is not endangered.

Fig. 17 finally shows, e.g. B. in accordance with US Pat. No. 3,680,051, the block diagram of a computer forming the issuing system SYST1 with central unit CPU, main memory MM and input / output unit IOP, which via a connected channel controller CHn with a transmission and reception control unit of a bidirectional transmission channel UE-K is connected as a receiving system SYST2 with an independent clock system f2, which for example establishes the connection to a further computer, not shown. The interface between the two different, asynchronously operating clock systems f1 and f2 are the arrangements for the transmission and reception path described above and designated here with S-SYN-ST and E-SYN-ST. The data words DAT supplied by the channel controller CHn are first written into a transmit buffer S-PUF on the basis of the control signals supplied and from there are fed to the fuse generator SI-G by the synchronization controller S-SYN-ST with filler word generator FW-G, which instead of the up to Parity protection PAR used at this point in the transmission path performs a block protection in a known manner within each data word DAT. The saved data blocks are then sent character by character to the transmitter SEN, and after a parallel / series conversion, for. B. modulated on an optical carrier and transmitted over the transmission channel UE-K.

Conversely, after the serial / parallel conversion, characters arriving in the transmission channel UE-K and demodulated in the receiver EMP are fed to the fuse control device SI-K, which forwards the data words with parity protection to the synchronization controller E-SYN-ST via a filler word suppression arrangement FW-U. From there, the data words DAT are passed in synchronism with the clock system f1 of the receiving computer system SYST1 to a reception buffer E-PUF, from which the channel controller CHn fetches them as required and makes them available to the microprocessor-controlled input / output plant IOP.

The formats of the data words DAT to be transmitted between the individual devices are indicated in the left part of FIG. 17. The data words are supplied, for example, with a width of 36 bits, 32 bits containing the actual information D and 4 bits used for parity protection PAR. On the basis of the control information supplied in parallel, 37 bits are used in the channel control CHn by prefixing a flag M, which may indicate that the associated information D on the receiving side must not be included in a streaming process, because a program interruption of the receiving input / output plant IOP is associated with it for example with block end markings etc.

The activation of the transmit buffer S-PUF or the receive buffer E-PUF in the data transmission path is of particular importance since, as the link to the computer, it takes into account the different control conditions of the computer and the transmission system, which essentially differ in that the transmission channel is continuous works, the computer, on the other hand, has a multitude of tasks to do and is therefore only temporarily available for the transmission channel, with data not only being delivered or fetched individually, but mainly in so-called streaming. This means that a predetermined number of data words DAT is passed on continuously during successive working cycles and thus at a higher transmission rate than that of the transmission channel UE-K. This requires, on the one hand, a close coupling of these buffer memories via the channel control CHn to the input / output unit IOP, in order to avoid time problems during synchronization, and, on the other hand, an adequate storage capacity.

The frequently used interchangeable buffers, which are filled and emptied alternately, are in many cases, e.g. B. because of the binding to a predetermined block length and because of the problems associated with the reversal, not particularly suitable. Single buffers are more advantageous Sufficient capacity with fixed alternating write and read cycles, whereby the buffer capacity in connection with the synchronous control can even be dimensioned lower than usual, since data can be saved again during input and the buffer memory only has to compensate for the difference between the source and processing data rate. In addition, additional tax and administrative information is less disruptive.

The block diagram of such a buffer memory, namely as a receive buffer E-PUF, is shown in FIG. 18. The individual memory sections 1 to 2 ^{n of} the reception buffer E-PUF are used for writing via a write address counter SAD-Z controlled by the strobe pulse STR ', with the write address register SAD-R and for reading via a read clock formed by the clock pulses of the receiving clock system f1 LT controlled read address counter LAD-Z controlled with the read address register LAD-R. A fill controller F-ST monitors the fill level of the buffer memory in a manner known per se by means of the write address SAD and the read address LAD, and derives the necessary control signals for the connected channel controller CHn. These are primarily the control signals PUF = 0 corresponding to SAD - LAD = 0 for «buffer empty PUF = 2 ⁿ corresponding to SAD - LAD = 2 ⁿ for« buffer full STREAMEN corresponding to SAD - LAD <DAD for «do not stream» .

In addition, the stored data words DAT are to be monitored for markings by the marker bit M, since these must not be included in a streaming process. Monitoring must therefore not only take place while reading, because then a streaming process could already have been initiated, but it must be carried out accordingly beforehand. For this purpose, an additional memory Z-SP is provided, in which the memory bits M of the data words to be stored are additionally written under the current write address SAD. On the other hand, they are read with a read address LAD-V which leads the current read address LAD by a distance address DAD corresponding to a streaming unit and which is formed from the read address contained in the read address register LAD-R and the distance address DAD by an adder ADD. The marker bit MV thus read in advance always appears so timely when reading that a streaming process currently in progress can in any case still be completed before the marking M appears at the output of the reception buffer E-PUF.

With each leading bit MV read in the filling control F-ST, a counting process is triggered, which includes a number of reading processes of the receive buffer E-PUF corresponding to the DAD. The streaming prohibition signal STREAMEN is only withdrawn again when this counting process has ended. Since several flag bits can occur within a possible streaming section, the counting process is restarted for each flag bit MV that has been read in advance.

The counting process can be controlled in a manner known per se by a correspondingly presettable counter which is preset with each leading bit MV read and is reset by one step with each reading process of the reception buffer E-PUF. As long as the counter is not in the zero position, the streaming prohibition signal STREAMEN appears.

On the other hand, since with a buffer filling SAD-LAD <DAD corresponding to PUF <DAD, no streaming process can take place anyway, and on the other hand, reading aloud with fault-free reading can lead to errors, in this case a flag M leads directly to triggering via the AND gate U50 the counting process, and the premature reading of the additional memory Z-SP is blocked via the AND gate 51.

The control signals PUF = 0 and STREAMEN are of primary importance for the subsequent reception side of the channel control CHn, so that data words DAT can be subtracted using STREAMEN using PUF = 0 or STREAMEN using the streaming method if PUF = 0.

When the buffer is used as the transmit buffer S-PUF, the dashed control signals PUF = 2 "and STREAMEN directed against the data flow are of primary importance for the transmit side of the channel control CHn in order to indicate that, in the event of an overflowing buffer, it is no longer allowed to transmit and In this case, the STREAMEN signal is triggered when there is just enough space available for a streaming packet, ie SAD - LAD = DAD, so that with PUF = 2 ⁿ with STREAMEN in the streaming procedure, with PUF = 2 "with STREAMEN only in single step procedure and with PUF = 2 ⁿ no more data words may be delivered.

In this case, the write clock ST is formed by the supplied strobe signal STR and the read clock LT by the clock pulses of the clock pattern f2 of the transmission system. The additional memory Z-SP shown in FIG. 18 including the associated control for the premature reading of the flag M can also be dispensed with.

Overall, the transmission device according to the invention can be very effectively included in the coupling of two computers.

Claims (21)

1. A device for transmitting data between two asynchronously controlled data processing systems (SYST1 and SYST2), with a buffer store (PUF) which comprises a plurality of storage sections each for the intermediate storage of a data word (DAT), and with two control devices, one of which, serving as input control unit, in synchronism with the clock signal (f1) of the data emitting system (SYST1), controls the transfer of a data word (DAT) into a storage section of the buffer store (PUF) which is available for the transfer, and the other of which, acting as output control unit, in synchronism with the clock signal (f2) of the data receiving system (SYST2), controls the forwarding of a data word (DAT) from a storage section of the buffer store (PUF), available for the output, to the data receiving system (SYST2), characterised in that a buffer store control unit (P-ST) is provided which monitors the level of fullness of the buffer store (PUF) and, when a data word (DAT) is intermediately stored, produces a corresponding control signal (dv) which is fed to a synchronising circuit (SYN2) which is assigned to the output end and which, avoiding logically non-defined intermediate states in the data- and control path, synchronises the control signal (dv) into the clock pulse pattern (f2) of the receiving system (SYST2) and thus results in a delayed (by means of w1) triggering of the forwarding of a data word (DAT), that a control signal (st), which is dependent upon the forwarding clock pulse pattern (f2), is produced for a synchronising circuit (SYN1) assigned to the input end and is likewise synchronised into the clock pulse pattern (f1) of the emitting system (SYST1), avoiding logically non-defined intermediate states in the data- and control path, and thus results in a delayed (by means of f1') triggering of the transfer of a data word (DAT) together with a strobe signal (STR) which controls the reception in the buffer store, and that the buffer store (PUF) includes at least three storage sections (e. g. registers RO to R2), namely one which makes available the data word (DAT) which is to be forwarded from the buffer store (PUF), one for the bridging of the synchronisation time (t_SYN2) prior to the forwarding, and one for the bridging of the input time (t_RAST2) of an intermediate storage request (by means of STR) into the clock pulse pattern (f2) of the receiving system (SYST2).

2. A data transmission device as claimed in claim 1, characterised in that the control signal (st) for the synchronising circuit (SYN1), which is assigned to the input end, is triggered in association with each clock pulse of the forwarding clock pulse pattern (f2).

3. A data transmission device as claimed in claim 2, characterised in that the control signal (st) in each case leads the clock pulse of the forwarding clock pulse pattern (f2) by the delay time (t_SYN2) governed by the synchronising circuit (SYN2) assigned to the output end.

4. A data transmission device as claimed in claim 3, characterised in that the delay time (t_DYN2) corresponds to a whole-numbered multiple of the clock pulse period time (t₂) of the forwarding clock pulse pattern (f2), and that where the delay time (t_SYN2) is greater than the clock pulse period time (t₂), the minimum number of storage sections (R...) in the buffer store (PUF) is correspondingly increased in order to facilitate continuous data flow at the output end.

5. A data transmission device as claimed in one of the claims 1 to 4, characterised in that the control signal (st) for the synchronising circuit (SYN1) which is assigned to the input end is derived from the existence of at least one free storage section (R...) of the buffer store (PUF) (signal frei), and that the control signal which has been synchronised-in releases those clock pulses of the clock pulse pattern (f1) of the data emitting system (SYST1), which occur within its active duration, as request signals for the consecutive transfer of data words (DAT).

6. A data transmission device as claimed in claim 5, characterised in that both the front- and the rear flank of the free signal (frei) are delayed by the synchronising circuit (SYN1) which is assigned to the input end, that the minimum number of storage sections (R...) of the buffer store (PUF) is increased by n individual registers in accordance with those clock pulses of the clock pulse pattern (f1) of the data emitting system (SYST1) which are still active during the delayed decay time, and that the free signal (frei) is produced only when at least (n + 1) individual registers of the buffer store are still free.

7. A data transmission device as claimed in claim 5, characterised in that only the front flank of the free signal (frei) is delayed by the synchronising circuit (SYN1) which is assigned to the input end, whereas the rear flank becomes momentarily active and suppresses following clock pulses of the clock pulse pattern (f1) of the data emitting system (SYST1) as request signals.

8. A data transmission device as claimed in one of the claims 2 to 4 in combination with claim 5, characterised in that directly upon the disappearance of the free signal (frei), the synchronising circuit (SYN1) which is assigned to the input end is switched over to the control signals (st) which are emitted in association with each clock pulse of the forwarding clock pulse pattern (f2).

9. A data transmission device as claimed in one of the claims 2 to 4, characterised in that the synchronising circuit (SYN2) which is assigned to the output end is not released until the minimum number of storage sections (R...) in the buffer store (PUF), which are required for a continuous data flow at the output end, is filled with data words (DAT).

10. A data transmission device as claimed in one of the claims 1 to 9, characterised in that the synchronising circuit (SYN1 and SYN2) comprises at least one intercept flip-flop (FA-FF) and at least one rear-flank-controlled synchronising flip-flop (SYN-FF), where the intercept flip-flop (FA-FF), as RS flip-flop, receives the control signal (st or dv) which is to be synchronised-in, and the subsequently connected synchronising flip-flop (SYN-FF) receives the output signal of the intercept flip-flop (FA-FF) with the relevant synchronising clock pulse (f1 or f2) which it forwards, delayed by the synchronising time (t_SYN1 or TSYNO, via an AND-gate (U1) as transmission clock signal (f1' or w1).

11. A data transmission device as claimed in claim 10, characterised in that in order to avoid the suppression of requests in the event of too rapid a succession of requests (st = f2), at least two synchronising units are provided each of which comprise an intercept flip-flop (SA-FF1, SA-FF2) and a synchronising flip-flop (SYN-FF1, SYN-FF2) with AND-gates (U31, U32) which are actuated in cyclic succession via a preceding control switching element (e. g. a rear-flank-controlled flip-flop T-FF), with each incoming control signal (st) which is to be synchronised.

12. A data transmission device as claimed in claim 10, characterised in that in order to avoid the suppression of requests in the event of too rapid a succession of requests (st = f2), at least two intercept flip-flops (FA-FF1 and FA-FF2) are provided which are connected in series via an AND-gate (U2), where the second signal input of each AND-gate (U2) of the series arrangement can be blocked via a delay element (VZ1) from the output of the following intercept flip-flop (FA-FF1), and the preceding intercept flip-flop (FA-FF2) can likewise be reset via a delay element (VZ2) from the output of the AND-gate (U2) of the series arrangement.

13. A data transmission device as claimed in one of the claims 10 to 12, characterised in that the intercept flip-flops (FA-FF) of the synchronising circuit (SYN1, SYN2) are at least in part an integral component of the control unit (P-ST) of the buffer store (PUF).

14. A data transmission device as claimed in one of the claims 1 to 13, characterised in that the registers (e. g. RO to R3) of the buffer store (PUF) form a series arrangement through which the data words (DAT) of the emitting system (SYST1) pass in stepped fashion, where the data word which is intermediately stored in the last individual register (RO) is forwarded to the receiving system (SYST2) in synchronism with the system clock pulse (f2) thereof,

that apart from that individual register (RO) of the series arrangement which forms the output end of the buffer store (PUF), each individual register (R3 to R1) is assigned a monitoring switching element (K-FF1 to K-FF3) which serves to display the state of seizure of the associated individual register (R3 to R1),

that these monitoring switching elements (K-FF1 to K-FF3), via preceding AND-gates (U2, U3, U4) which serve to block the setting inputs (S), likewise form a series arrangement, where the setting output of each monitoring switching element (e. g. K-FF1) is connected to the inverted. second signal input of the associated AND-gate (e. g. U2), that the transfer clock pulses (UT) for the input storage of a data word into the associated individual registers (R3 to R1) and the reset signals for the preceding monitoring switching elements (K-FF1 and K-FF2) are derived from the output of the following AND-gate (U2 to U4) in the series arrangement so that in dependence upon the incoming strobe signal (STR), the data words (DAT) are consecutively forwarded in stepped fashion from individual register to individual register directly to the free individual register (e. g. R1) which lies closest to the output end of the buffer store (PUF) and

that the individual register (RO) which forms the output end of the buffer store (PUF) is assigned, in place of the monitoring switching element, a rear-flank-controlled synchronising flip-flop (SYN-FF1) followed by an AND-gate (US) which. in dependence upon the preceding monitoring switching element (K-FF3), is clock controlled by the clock pulses of the system clock signal (f2) of the receiving system (SYST2) and releases the following AND-gate (US) in order to trigger release - delayed by the synchronising time (T_SYN2) - of the transfer clock pulse (UT) for the last individual register (RO) for the forwarding of a data word (DAT) and in order to reset the preceding monitoring switching element (K-FF3).

15. A data transmission device as claimed in claim 5, characterised in that the synchronising flip-flop (SYN-FF1) is preceded by an OR-gate (01), and that the outputs of all the preceding monitoring switching elements (K-FF1 to K-FF3) and of the input intercept flip-flop (FA-FF) are each connected to a signal input of the OR-gate (01).

16. A data transmission device as claimed in one of the claims 1 to 13, characterised in that the individual registers (e. g. RO to R3) of the buffer store (PUF) can be selectively actuated for the input and read-out of data words (DAT),

that each individual register (e. g. RO) is assigned a flip-flop (for example, SO) which is rear-flank-controlled by the strobe signal (STR) and is followed by an AND-gate (e. g. U10), where all the flip-flops (SO to S3) form a ring shift register in order to characterise the particular receiving individual register (R...), and the write signals (SS) are each obtained from the output of one of the AND-gates (U10 to U13) in dependence upon the set state of the flip-flops and upon the existence of the strobe signal (STR),

that the AND-gates (U10 to U13) are each followed by an RS-flip-flop as input intercept flip- flop (EINO to EIN3) in order to characterise the existence of read commands for the buffer store (PUF) and

that via a series operating output network unit (AND-gates U20 to U23), the outputs of the input intercept flip-flops (EINO to EIN3) activate, in the sequence in which they become operative, individually assigned synchronising circuits (e. g. SYNO, U30, AUSO) which, following the expiry of the necessary synchronising time (t_SYN2), in dependence upon the system clock signal (f2) of the receiving system (SYST2), supply the read signal (LS) for the associated individual register (e. g. RO) and a reset signal for the preceding intercept flip-flop (e. g. EINO), where the read signals (LS) are maintained (by flip-flops AUSO to AUS3) for the duration of one entire clock period (t₂) of the governing system clock signal (f2).

17. A data transmission device as claimed in claim 16, characterised in that for each individual register (RO to R3) there is provided an additional bistable switching element (RS-flip-flops BELO to BEL3) which characterises the state of seizure thereof and which is set on the response of the associated input intercept flip-flop (EINO to EIN3) and in contrast to the input intercept flip-flop is not reset until the end of the read duration (t₂), and that a control signal (st) which may possibly be required and which characterises the free state of at least one individual register (R...) in the buffer store (PUF) is derived via an OR-gate (02) from the signal outputs of the switching elements (BELO to BEL3) which indicate the state of seizure.

18. A data transmission device as claimed in one of the claims 14 to 17, in particular for the supply of a data transmission system which forms the receiving system, characterised in that in order to maintain a continuous data flow at the output of the buffer store (PUF) in the absence of data words (DAT), in place of the data words, filler words are gated into the data flow for the receiving system (SYST), and that the control signal (FW) for the gating in of the filler words is derived directly from the inverted signal of one of the switching elements (SYN-FF2 or AUSO to AUS3) which initiates the transmitting period (t2) for the data words.

19. A data transmission device as claimed in one of the claims 1 to 18, in particular in association with a computer as data emitting system, characterised in that for the synchronisation, the buffer store (PUF) is preceded by an elastic buffer store (S-PUF) with independent input and output control, where the output control is dependent upon the control of the buffer store for the synchronisation.

20. A data transmission device as claimed in claim 19, in particular for the coupling of two computer systems by an interposed transmission system which has transmitting and receiving devices connected by a transmission channel and which operates with a system clock signal (f2) which is independent of the system clock signals (f1) of the two computer systems, characterised in that

the series arrangement of the elastic buffer store (S-PUF) and buffer store for the synchronisation (S-SYN-ST) to the system clock signal (f2) of the transmission system prior to the transmitting device (SIG/SEN) at the transmitting end corresponds at the receiving end to a mirror- image arrangement of the series arrangement of buffer store (E-SYN-ST) for synchronisation to the system clock signal (f1) of the connected computer and the elastic buffer store (E-PUF) following the receiving device (EMP/SI-K),

that each clock pulse of the transmission clock pattern (f2), which does not coincide with a filler word, serving simultaneously as strobe signal (STR), causes incoming data words (DAT) to be directly transferred into the buffer store (E-SYN-ST) for synchronisation and

that in association with the synchronising circuit which is assigned to the output end of this buffer store (E-SYN-ST), a control signal (STR') is produced which is clock-synchronous with the receiving system clock signal (f2) and which causes the data word (DAT), which is awaiting forwarding, to be transferred in the clock cycle which has been initiated.

21. A data transmission device as claimed in claim 20, characterised in that those items of data (DW) which are supplied by the data emitting computer and which result in a programme interruption in the receiving computer are characterised by an additional marker bit (M) within the data word (DAT) which is to be transmitted, and data words characterised in this manner are individually forwarded, that in order to prevent data words (DAT) which are stored in the elastic buffer store (E-PUF) at the receiving end being forwarded in packeted fashion to the receiving computer when, within such a packet, one of the data words (DAT) is marked by an additional marker bit (M), when the data words characterised in this way are input into the elastic buffer store (E-PUF), an additional characteristic (MV) is stored in an additional store (Z-SP) of the elastic buffer store (E-PUF) under the same write address (SAD), that during each read process for the elastic buffer store (E-PUF) this additional store (Z-SP) is operated by a read address (LAD-V) which, in comparison to the currend read address (LAD) for the elastic buffer store (E-PUF), is increased by a distance address (DAD) characterising the packet length when at least one packet is stored, and that each read additional characteristic (MV) or each marker bit (M) input into the buffer store (E-PUF) when less than one packet is stored (PUF DAD), initiates a counting process with a number (e. g. 8) of counting steps which corresponds to the distance address (DAD), and during each counting process a blocking signal (STREAMEN) is produced in order to prevent the packeted call-up of the data words (DAT), stored in the elastic buffer store (E-PUF) by the receiving computer.

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