DE2657243C2 - Circuit arrangement for the transmission of control signals in centrally controlled telecommunications switching systems - Google Patents

Description

50

The invention relates to a circuit arrangement for the transmission of control signals between a central Control unit ("central unit") in a telecommunications switching system and lines on which control signals for telecommunication connections are transmitted ("Signaling lines"), where the signaling lines run over connection sets and where at least one temporary storage unit is provided, which is connected to the central unit and via a concentrator is connected to the connection sets.

This circuit arrangement is preferably intended for telephone switching systems, but it can can also be used in any other telecommunications equipment.

Telephone systems are connected to one another by cables. A line contains a bidirectional Transmission path for voice transport and a signaling path for exchanging information

60

65 drive signals before, during and after a conversation, the signaling usually takes place in each direction on its own path. The line is connected at both ends to signal generators, the generated signals of which, which form a signaling process, are transmitted to the outgoing signaling path. At both ends of the line, signal pickups are also connected to the incoming signaling path, which simulate the signaling process. Signal generators and signal receivers of one extension can be combined to form a terminal device called a connection set.

Telephone systems or exchanges are equipped with coupling, control and access means Internal, external, incoming and outgoing connections can be switched to the coupling means.

The control means in modern systems are in the form of a central unit and contain at least two processing units similar to suitably programmed general purpose computers. The means of access are then peripheral units of the computer: the Scanners that record data from the lines and the distributors that send commands over the lines to associated Send units and coupling means.

The signaling operations are numerous and varied. Using the example of an outgoing call, the from a subscriber of a local exchange to a subscriber of a long distance exchange are in the Local exchange after selecting a free line between the two offices, the following steps are necessary:

- Sending an occupancy code.

- Receiving the dial request, then dial.

- Receipt of the end-of-election character, which can have several meanings (subscriber free, subscriber busy, wrong dialing), then receiving the answer character.

- Possible reception of call counters.

- Sending and receiving end-of-call signals when one of the participants joins any Time to hang up.

The steps listed, i.e. signaling processes must be sent in the same direction almost at all times will.

In known electromechanical devices, a connection set is used which has means that can send and receive on command. The delays encountered at these facilities are seldom critical and the transmission of signaling processes between the central unit and Connection sets allow certain delays. However, these known devices are expensive and must also be available in many cases. In addition, these institutions lack any flexibility; they are only for set up a specific signaling system.

The circuit arrangement according to the invention has the task of generating control signals between a central Control unit in a telecommunication switching system and lines on which control signals for telecommunication connections are transmitted, to be transmitted, the transmission of the control signals taking place without time constraints can.

The object is achieved in that an intermediate storage device (F i g. 2, F i g. 5) a memory with signaling line, d. H. connection set-individual Contains memory locations in which a group of samples according to the signaling information

3 4

mation is buffered, and that the intermediate take place after the sampling method. Each sample data storage device (Fig. 2, Fig. 5) to automatically adjust the level of the transmission channel for the time, according to control with a clock, which is started at the beginning of which separates it from the next sample. There is signaling , and an access logic, the same advantages and disadvantages as when receiving,
which is connected to the central unit and the memory. Now, with reference to FIG. 2 is an exemplary embodiment, is equipped. This has the advantage that a system for the transmission of signaling can follow the transmission of sample values described without time constraints, which is the subject of the invention. The central unit is thus relieved and that is used for the transmission of signals. io JC 1 to JCn to a central unit UC. The system

In the following, the invention is based on in drawing works advantageously according to the scanning method, without de-

the embodiments shown in more detail have disadvantages,

wrote. It shows the connection sets JC 1 to JCn are with several

F i g. 1 Signals of a signaling process, lines CC ί to CCn connected. The system contains

FIG. 2 is a block diagram of a first embodiment, essentially a memory MER with several

game for the transmission of signaling processes memory locations er 1 to crn, whose indices the associated

of connection sets to a central unit, to specify the lines, and control means, of

F i g. 3 Contents of a line-specific memory disk, a receive logic LER, an access logic LAR,

zes to F i g. 2, a clock HCR and a scanner EXP to be

F i g. FIG. 4 is a flowchart of the processing of FIG. 20.

Fig. 2, The following describes how the spoke

Fig. 5, 6 and 7 to the Fig. 2, 3 and 4 homologation of individual sampling pulses of the line

Second embodiment for the transmission of Si- CC 1 in the memory location he 1 by means of scanner EXP

Signaling processes from a control center to the connection and the receive logic LER happens. For a group

clauses. 25 of samples that are stored in the memory location er 1

First, with reference to FIG. 1 an example of a signaling are brought and which come from the line CC 1,

sizing process and the precautions taken during such a process, these through access logic

occurring signals described. This signa- ΛΛ /? to transmit to the central UC,

The clock generator HGR generates periodic signals nc,

telephone line arise. The form of the transmitted Si 30 Im, ic for the receive logic LER. The signal is nc

gnals is designated with FSIG . The signaling path codes and designates a line. It changes his

leads first a low, then a high and da- value in order to sequence all lines CC 1 to CO?

after a low level again. to be named during the n-step receive cycle

The signaling includes those denoted by SIG. The signal Im occurs at the beginning of every step,

Period, the beginning of which with the pulse rise 35 to control the reading in the memory MER. The signal

coincides The displayed pulse has the nominal ic also occurs at the beginning of each step by one

pulse duration dt For reasons of tolerance, pulse interruption steps must also be controlled in the EXP scanner,

se, the duration of which is between df 1 and di 2, are permitted. The reception logic LER is controlled by the signals nc, Im

The reception of such a signal can be activated in analog and ic to complete a receiving step.

This can be done by the first change in level by the 40 you transfer the signals nc and Im back to the memory

Times di 1, df 2 and SIG are measured. After Ab- MER, which controls a reading step in the MER memory

During the time SIG , it is evaluated whether the received is to a memory location designated by the signal nc

Signal during the time df 1 to achieve continuously high Pe-, the content of which can be received on the connection

gel and whether it is continuously transmitted in the time after df 2 the capture logic LER. She retransmits

had a low level. Such a solution is also to 45 the signals nc and ic to the scanner EXP, where these

agile and expensive. Signals control an interrupt step. The level

A scanning method (REC of the received signal path of each line CC 1 to

in Fig. 1) can be applied. The signaling path CCn is constantly from the associated connection set

is observed at regular intervals so that EXP is transmitted to the scanner. The level of the through

Samples from short pulses are generated, whose Am- 50 signal nc named line is transmitted via conductor ecr in the

plitude reproduced the level of the signaling path in the scan / receive logic.

moment corresponds. It is advantageous that the ab- At the end of these two steps, done simultaneously

sample values from a control center can be transmitted, where can be, the content of the receive logic is LER

they are available with regard to group processing of storage space er 1, which, for example,

be saved. 55 se is intended for the line CC and also one

Only three to five consecutive sampling individual sampling impulses of the signaling from the values with a high level, followed by five to three with the same line CC !. As a result, the reception level leads to a low level, certain logical operations are sufficient for the unambiguous detection of the gik LER, the following signals process, whereby the tolerance is described in more detail below and which is possibly also taken into account. A disadvantage is that the 60, a modification of the space in it have \ read submission of samples to exact Zeitbedin- information on the result, is notably linked by the conditions, which pollutes the center. Incorporation of the individual sample into a

The transmission of such a signaling image group of samples. The Verarbeigangs may also with specific circuits exclusively carried tung clocked not be begeführt represented by: having substantially a generator 65 known means (for example, logic LER is controlled produces a pulse the duration of df and a weite- of high frequency pulses from a clock to the ren generator, which defines the period duration SIG . Same as next line).
F i g. 1 under ENV shows, the transmission can also The clock generator HGR then generates during the same

In the processing step, a signal ins that is intended to control the storage steps. After receiving the signal nc that is still present and the signal ins , the receiving logic transmits LER to the memory MER, offering the previously mentioned information modified on connection mer. This controls the storage in memory location er 1, which belongs to line CC 1, the logic LER having just processed a sample of the signaling.

The access logic LAR activates the control center UC in order to get to know the sampled values contained in the memory MER. It can thus read, for example, a group of sampled values contained in location er 1 of the memory MER , which a signaling process such as REC in FIG. 1 represent. Finally, the access logic LAR receives a read command from the control center UC which contains the number nc of the line CCl, whose memory location it 1 must be read.

During the same processing step, but outside of the time segments in which the signals Im and ins are emitted, the clock generator generates the successive signals Im ' and ins'. Like the signals im and ins , these signals are also commands that control reading and writing in the MER memory.

If these signals are present, the access logic LAR transmits the signal Im ' and the number nc in the direction of the memory MER. A read step takes place and the content of the storage space is output on the connection mer '. The access logic LAR transmits this information back to the central unit UC, in particular the abiast values it contains.

In the same way, the center f / C can output information for writing into a specific memory location for the purpose of restarting, which is described below. This operation is controlled by the access logic LAR - like reading - but using the signal ins'.

FIG. 2 additionally shows direct connections between the access logic LAR and the scanner EXP. These allow the control center UC to use the scanner EXP directly in order to find out the signaling status as instructed - in a departure from the automatic transmission of the signaling events, as described. In this case, the logic LAR receives a command from the central UC, which in particular contains a line number nc The clock generator generates a signal to homologous ic ic 'simultaneously with the signal'. It is transmitted to the scanner EXP at the same time as nc and the logic LAR then receives the status of the named signaling point and this information to the control center IJC via connection ecr'vikd. retransmitted.

The memory MER of this system and also the clock generator HCR and the scanner £% P are standard versions. The same applies to the LAR access logic, which is nothing more than an interface circuit, the function of which is merely to delay the information. Therefore, no more detailed description is given. The following explanations apply to the receive logic LER, whose mode of operation and structure are based on FIG. 3 and 4 will be described.

F i g. 3 shows the content of a memory location in the memory MER, while FIG. 4 shows a flow diagram of the operations carried out by the receive logic LER , the data of a line-specific memory cell and that of the signaling path being used at the same time.
According to FIG. 3, each memory location contains a 16-bit word, the bits of which are numbered from 0 to 15.

The two left bits indicate a phase display SQR , which makes the following four statements:

- SQR = 00 The line is blocked and the Zen

trale has ordered the systematic rejection of all signaling processes.

- SQR = 01 It becomes a signaling process

waiting, but nothing has been received yet.

- SQR = 10 A signaling process is emp

catch but the reception is not yet complete.

- SQR - 11 A signaling process is complete

dig has been received and should now be communicated to the control center.

The two bits of ranks 2 and 3 give a speed display VR which defines the frequency of the sampled values considered. Some signaling processes take longer than others. From Fig. 1 it can be seen that, after what has been said above, a much larger number of samples would be required for representation. The invention provides that the same number of samples is always used; in the case of longer signaling processes, only one of, for example, two, four or sixteen samples is taken into account.

The three bits in ranks 4 to 6 form a pointer PTR whose value (2 ³ = 8 different values) designates the rank of an individually processed sample in a group of samples of a signaling process and which is also used for storage in the correct memory location in the Zone ESR is used, as will be explained later.

The bit labeled EIR in ring 7 indicates the original value at the beginning of the waiting phase of a signaling process on the signaling path (specified by SQR = 01).

As long as the signaling path maintains this state, the waiting phase remains. A single one Sampling value, on the other hand, indicates a change in status and at the same time marks the beginning of reception of the Signaling and causes a phase change, which will be described in detail later.

The bits of ranks 8 to 15 finally form a zone ESR, which is transferred to store the individual samples of a received signaling process.

Now the exact functioning of the receive logic LS? on the basis of FIG. 2 to 4 described. The flow chart in FIG. Fig. 4 illustrates the operation of the logic LER in any step of any cycle and contains the answer for all possibilities encountered.

A processing step of the logic LER, which is initially in an idle state, begins when a state LAWl occurs. This state can simply be the beginning of a signal Im supplied by the clock HGR . As described above, the reading steps in the memory MER and the scanning steps are found of the sampler £ YF take place at the same time and generate a word in the memory MER on connection mer and an individual sample value from the previous signal on the signaling path of the associated line, which was output on connection ecr. These operations are named in the flowchart (FIG. 4) together with LECR . It is assumed that they represent the

Storage space er 1 and the line CCl concern.

When these operations have been completed, a first step of comparison is made between the information output by the clock and the display VT? executed. This step results in four independent values of the display VT? and four clock signals output during each cycle, a second during a second cycle, and so on, according to the intended speed. When the display shows VT? states that a sample should come to four and if the associated clock signal is absent, which is shown in FIG. 4 by the expression CKR Φ VT? is designated, then the work of the logic LER immediately goes to a stage 577? passed, whereby a waiting state occurs after the following processing step. The individual sample received is still not processed because it is part of the three out of four samples that do not need to be processed. But when the expected clock signal comes - this is indicated by the expression CKR = VR - then the operation of the logic takes a step in processing the sample.

A second comparison step between constant values and the SQE display is then carried out.

If the SQR indicator is 00 or 11 (SQR 00, 11) then the work is directed to the STR section. If SQR = 0, the line is blocked and the signals output are not taken into account. Likewise, the later signals at SQR = 11 are not taken into account after a signaling process has been completely received, as long as the control center has no knowledge of the signaling process (modified SQÄ display). In either of these cases, the received samples are not processed either. If the display shows one of the other two values (SQR = 01,10), then the next step is taken.

A third comparison step is done between constant values 01 and 10 and the SQR display. First, attention is paid to whether the 5 <? Ä display 01 has the value, which indicates a waiting situation during signaling, which can then be encountered.

The control center UC has stored this display in the memory because the line was occupied by a call and because in the course of this communication, which has been initiated so far, a point has been reached which allows a certain change of state to be expected on the signaling path of the receiving line. The speed display VT? has been selected by the LJC headquarters in anticipation of the Si ^CT nslisierun ^Gr svor ^cr änges.

A fourth comparison step is carried out between the display ElR and the received sample value £ 7? executed The EIR display corresponds to the status of the signaling path before the change in status was perceived. Insofar as the sampled values recorded by the signaling path indicate this state, the reception of the signaling process has not yet started. The sample is rejected because processing is routed directly to the STR area WlTd (ER = EIRJ.

If, on the other hand, the processed individual sample value indicates a state other than that indicated by the display EIR (ER = EIR) , then the beginning of the reception of the expected signaling process has occurred. The logic LER consequently goes to a processing step with the note \ Q - <- SQR . This operation changes the value of the display SQR of the information read in memory location er 1. This display, which had the value 01, is changed to the value 10. This value means that the signaling is in the receiving phase.

The processed sample value is then recorded by the display ESR , the position of the pointer PTR being taken into account. Then the information read in the memory location cri that the line

ίο CC 1 concerns, modified again. In this modification, one of the bits of the zone ESR is replaced by a bit derived from the sample ER. The rank of the bit of the zone ESR is thus offset and indicated by the pointer PTR. At the first sample of a signaling, the pointer has the position 000 and the sample takes place as a bit of rank 8 (FIG. 3).

Then the position of the pointer PTR is modified so that it designates the place in the zone ESR for the individual sample of the signaling. This operation is marked +1 - ► PTR and consists in adding a unit to the value of the PTR indicator.

Finally, a write-in step INCR is carried out in order to write the modified information into the memory location under consideration in the manner described. Ultimately, the LER logic stops working - the STR level has been reached.

In this way, the LER logic has modified the value of the display of the SQR phase on receipt of the first sample of the expected signaling, in such a way that the following samples are processed (subject to the effect of the display of the speed VR), ie stored in the memory location; the sampled value under consideration was stored in the memory location and the pointer PTR, which controls the storage of the sampled values, was advanced by one step.

The logic LER works for different lines and executes processing steps according to a line in the manner described in order to complete a cycle. The same cycles are repeated periodically. If the steps and the cycles are of constant duration, then each line is polled at regular intervals. Thus, the receiving logic, after having processed the line CCl in the manner described, processes it again after one cycle

The LECR operations take place. They output the memory word and a sample value when received.

so If the speed dictates the processing of every fourth sample, everything stops (CKR φ VR). The sample is not processed. The same applies to the two following cycles. In the fourth cycle, the state CKR = VR is finally reached, so that processing can begin with the first three branches past the branch with the note SQR = 10. As already said, the SQR display of the storage space now has the value 10.

An additional comparison between the value of the display PTR and a constant value 111 is carried out. If the pointer is not yet in its last position, as here, then the condition is PTR Φ 111. The processing returns to the operations described above in order to obtain the sample and store the progression of the pointer PTR.

After seven sampled values that were received during the signaling process have been stored in this way the pointer has its last position

9 10

Taken with the note 111. At the time it is possible to provide suitable means that the central

processing of the eighth sample value is allowed to intervene from the unification as soon as one or more

equal between the value of the display PTR and the groups of samples that have formed

Value 111 may form the condition with the note PTR = 111 in a queue,

issued. Then the logic LER completes a 5 The application example of the previously described

Operation marked 11 - ► SQR before dealing with the present invention relates to the transmission of

the normal storage of samples - signaling processes from the periphery in the direction

moves. tung headquarters. With reference to F i g. 5,6 and 7 is now shown

In this way, the samples of the signaling that the present invention can also be applied to the reverse

event that can be used in the line-specific memory to direction

place are saved until they are F i g. 5 shows that the resources required are entirely ana-

UC are required. It should be remembered that if there is a log, they are similar to those in the example described above.

Display SQR with the value 11, the second operation- Therefore, the description should be concise,

control the processing of the samples from the line The in F i g. The system shown in Figure 5 is intended for

prevents the transmission of signaling events between

can be seen In this way, the central unit UC and the lines CC \

until the central unit UC shows other displays in the to CCn, which are connected with connection sets / Cl to JCn

stores the storage space under consideration here; are either bound. It essentially contains a memory

by bringing the SQR display to 00 to display MEE with several memory locations ce 1 to cen, whose

reject other signaling or indicate the affiliation to the lines to the 20 indices.

Identification that a subsequent signaling and control means, one of which is transmission logic

Operation is expected. LEE, an access logic, a clock and an output

The processing sequence described above, which can be fully distinguished via DTR .

constantly from the flow chart in FIG. 4 is shown, the system enables storage of only simple logical or arithmetic sample values of a line CCl in a memory location links. Means for executing such links; individually are the samples and sequentially levies are in the field of data processing well sawn from the storage space via the transmission logic LEE known can according to the principle of the wired and transmits the issuer DTR to line VorLogik or according to the principle of the programmable precautions for a group of samples, which work a logic, for which a more detailed description 30 define the signaling process, are not required for transmission. It should be noted that for processing payments from the central processing unit into the memory locations, numerous alternative solutions are possible; the pre- the access logic LAE met,
The clock generator HGE, as shown in FIG. 2, also in a different order or also generated periodic signals on connection hge, which are executed in a timely manner. It was assumed that the reading of information from a memory location would enable a transmission step to read information from a memory location (addressing via connection is non-destructive, which means that storage is ade, information is transmitted to connection / nee) in order to check whether rejected individual samples have been bypassed a signaling process in the course of will. In the case of a different memory, the saving would be transferring occurs; in the affirmative, a sample is necessary, the thus happens that the operation rated 40 of the transmission and the issuer DTR conces- INCR in the flow chart (F i g. 4) behind stage STR comparable results, it is used for link set transmits (Adressielegt. tion via connection adt and sample value transmission

The same applies to the method as the central unit via connection ese), so that as a result of the content of the UC, the transmission of a group of sample values in the memory location is modified. The means for this purpose can be implemented, which can easily lead to a signaling process, as shown in FIG. 2 can be taken,
and which had formed in a memory location independently The access logic LAE activated controlled by the clock, alternative solutions possible. These metal donor HGE via the connection hge'die CPU Thode is applicable because the information in the storage UC protected to provide access to places of memory MEE to cherzelle lingers, as already mentioned, the have ade (addressing via connection 'and The information interval between two signaling processes is 50 mation transfer via connection mee ¹ ) ·, it can be uncritical. After receiving a signaling in this way the content of the storage locations for the process, the readiness to receive is noted much earlier and the emergency is restored in these storage locations than is necessary periodically reads the stored sample values of a signaling process, storing them, increasing their content in order to access the transmission of corresponding signals when the display SQR has the value 11, with causing.

the duration of the period is not the duration of the signaling. Between access logic LAE and issuer DTR

must correspond to the process - it can be required - depending on the type of system in FIG. 2 direct connections

wisely be extended. aded and sed are provided for the central processing unit UC

An improvement on this method is, for example, to give direct access to the connection records, so that resources in the system according to FIG. 2 signals do not have to periodically read all memory locations without delay and without the MEE memory. For this purpose, the memory MER passes through, controlled directly by the issuer, a register that holds for each storage medium.

cherstelle a 1-bit stage has This bit is set, Fig. 6 shows the content of a memory location in the display Speiwenn SQR is placed at 11. The Zen 65 rather MEE is associated with a line, it is then traleinheit queries the registry, which storage a 16-bit word of the same structure as the word in the provide a complete set of samples from F i g. 3. The bits of ranks 0 and 1 indicate a phase of signaling. It is also showing SQE , the four values of the following meaning-

can take:

- SQE = OO The line is blocked and must

no signaling process can be given.

- SQE = 01 A signaling process is being performed

sends; the signaling must be repeated.

- SQE = 10 A signaling process is being performed

sends; the signaling only needs to be done once.

- SQE = 11 A signaling process is complete

dig been sent.

The two bits of ranks 2 and 3 provide a speed display VE analogous to VR in FIG. 3. The three bits of ranks 4 to 6 form a pointer PTE analogous to pointer PTR in FIG. The bit of rank 7 is not used. The bits of ranks 8 to 15 form a zone ESE which is intended for storing the sampled values of a signaling process to be transmitted.

'n the system according to FIG. 5 only requires the logic LEE, the operational process of which is shown in the flowchart in FIG. 7, a detailed description.

In a processing step, which relates, for example, to the memory location ce 1 and the line CC 1, the logic LEE is started by the clock generator HGE ; this is in FIG. 7 marked with LME . A processing step with the note LECE activates the reading of the memory location ce 1. The speed indicator VE is compared with the clock signal CKE , not shown. If it is necessary to transmit a sample value of one of four cycles and if this is not necessary in the cycle in question, the processing according to condition CKE φ VE is passed to the output stage STE . In the opposite case, the value of the display SQE is checked.If the display has the value 00 (locked loop), no transmission is required and processing is directed to the STE stage.If the value 11 is present and a signaling process has been completely transmitted, it is also necessary no further transmission and processing is directed to stage STE .

If a signaling operation has to be transmitted, the indication SQE is equal to 01 or 10. The condition SQE = 01, 10 leads to an operation of the note FEE, which consists in occupying one of the bits from zone ESE corresponding to the value of the pointer PTE and this Bit on connection ese so that it forms an individual sample value of the signaling process in the course of the transmission. It may be that this is the first sample value of a signaling process, the read word being the one stored in memory location ce 1 by the central unit UC However, it can also be one of the next sample values.

The position of the pointer PTE is checked. If PTEφ is 111, ie that this is not the case with the last sample then processing is passed to an operation +1 - ► PTE which increases the value of this indication by one unit modified information stored in an INCE operation in memory location cc 1

In this way, seven samples are sent in seven cycles on line CCl, the intervals of which are determined by the speed indicator VE. At the eighth sample the pointer is in its last position PE = 111. If only a combination of the following signals, which is defined by a group of samples stored in zone ESE , has to be transmitted, then the display SQE has the value 10. This operation changes from condition SQE = 10 to a processing step with the note 11 - SQE steered. The SQE display takes a value of 11. Processing then proceeds to stage STE as before. Since the value of the display is SQE = 11, receive

ίο the line CC 1 no further samples of the signaling, since the condition SQE = 11 leads directly to stage STE . When the central unit UC reads the content of memory location ce 1, this means for the central unit that the signaling process has been transmitted.

! 5 The central unit can then generate a Give value.

The case remains with condition PTE = 111, where processing has just been directed to the evaluation phase and the display SQE is 01. If the condition SQE = 01, the operation 11 —► SQE is skipped. The pointer PTE moves to position 000 following operation +1 - ► PTE . Thus, the pointer PTE for sending is brought to position 000 after the transmission of the eighth sample value of the group stored in memory location ce 1, because the display SQE of the first sample value 01 has remained. In this way, the continuous transmission of a periodic signal is achieved in a simple manner, which is only interrupted by the intervention of the central unit UC to modify the content of the memory location ce I.

For this purpose 3 sheets of drawings

Claims (4)

Patent claims: 1. Circuit arrangement for the transmission of control signals between a central control unit ("central unit") in a telecommunications switching system and lines on which control signals for telecommunications connections are transmitted ("signaling lines"), the signaling lines running over connection sets and at least one buffer unit being provided which is connected to the central unit and via a concentrator to the connection sets, characterized in that the intermediate storage device (F i g. 2, F i g. 5) has a memory (MER, MEE) with signaling line, ie connection set-specific storage locations (er 1. .. cm, ce I ... cen) , in which a group of samples is temporarily stored according to the signaling information, and that the intermediate storage device (Fig.2, Fig.5) for automatic control with a clock (HGB, HGE), which is started at the beginning of the signaling, and a Z access logic (LAR, LAE), which is connected to the central unit (UC) and the memory (MER, MEE) , is equipped. 2. Circuit arrangement according to claim 1, characterized in that the memory locations (he 1 ... cm, ce I ... cen) enable access to a speed display (VR, VE) , whereby signaling processes of different lengths can always be displayed with the same number of samples. 3. Circuit arrangement according to claim 2, characterized in that the memory locations (er 1 ... cm, ce 1 ... cen ) allow access to a phase display (SQR, SQE) , whereby the transmission of individual samples can be blocked. 4. Circuit arrangement according to claim 3, characterized in that two intermediate storage devices (F i g. 2, F i g. 5) are provided, one (Fig.2) transmitting incoming and the other (Fig.5) outgoing signaling processes, and that the concentrator (ESP, DTR) is a scanner (EXP) in one case and a distributor (DTR) in the other.