EP0088755A1 - Circuit de conditionnement de signaux a compensation de la perte doppler - Google Patents

Circuit de conditionnement de signaux a compensation de la perte doppler

Info

Publication number
EP0088755A1
EP0088755A1 EP81902992A EP81902992A EP0088755A1 EP 0088755 A1 EP0088755 A1 EP 0088755A1 EP 81902992 A EP81902992 A EP 81902992A EP 81902992 A EP81902992 A EP 81902992A EP 0088755 A1 EP0088755 A1 EP 0088755A1
Authority
EP
European Patent Office
Prior art keywords
signal
input
output
dropout
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP81902992A
Other languages
German (de)
English (en)
Inventor
Jeffrey J. Riebschlager
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Caterpillar Inc
Original Assignee
Caterpillar Tractor Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Caterpillar Tractor Co filed Critical Caterpillar Tractor Co
Publication of EP0088755A1 publication Critical patent/EP0088755A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
    • G01S13/02—Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
    • G01S13/50—Systems of measurement based on relative movement of target
    • G01S13/58—Velocity or trajectory determination systems; Sense-of-movement determination systems
    • G01S13/585—Velocity or trajectory determination systems; Sense-of-movement determination systems processing the video signal in order to evaluate or display the velocity value
    • G01S13/586—Velocity or trajectory determination systems; Sense-of-movement determination systems processing the video signal in order to evaluate or display the velocity value using, or combined with, frequency tracking means

Definitions

  • This invention relates to circuits for providing dropout compensation and more particularly to circuits for providing dropout compensation for doppler shift measuring devices.
  • velocity detectors and certain other devices include an element for transmitting a signal, an element for receiving the signal, and an element for monitoring the frequency difference between the signal as transmitted and the signal as received. From this frequency difference, termed "doppler shift" in the art, the velocity of the transmitter can be determined relative to the receiver or to a reflecting surface. Since the measurement made by such devices is entirely dependent upon this doppler shift, it is important to ensure that the signal as received accurately represents a true doppler shift of the signal as transmitted. in certain applications this reflected signal can periodically become rather weak or entirely non-existent. For example, where the transmitter is a vehicle mounted ultrasonic signal generator and the ground is utilized as the reflector, the " attenuation of the signal from transmitter to receiver is typically several orders of magnitude.
  • any existing doppler effect type devices make no provision for dropout and, as a consequence, provide an erroneous output during the occurrence of this condition.
  • Other systems do incorporate dropout compensation circuits, but these circuits tend to render the system sluggish in response to changes in the magnitude of the doppler shift.
  • the present invention is directed to overcoming one or more of the problems as set forth above.
  • a signal conditioning circuit includes means for receiving a cyclical input signal. Means responsive to said input signal is provided for generating an output signal of a frequency substantially directly proportional to the cyclical input signal. Means is further provided for preventing dropout in the output signal for no more than a preselected period of time during the occurrence of dropout in the input signal and for substantially preventing dropout of said input signal from decreasing the frequency of the output signal during the existence of said dropout condition.
  • Several classes of electrical devices track cyclical signals for one purpose or another. Many of these devices, especially doppler shift detectors, suffer impaired performance due to the occasional absence of one or more periods of the input signal. This absence is known as "dropout".
  • Fig. 1 is a schematic circuit diagram of the best known embodiment of the present invention
  • Fig. 2 is a schematic circuit diagram of a second embodiment of the present invention.
  • the signal conditioning circuit 10 receives a cyclical input signal subject to dropout and generates from this input signal an output signal. During those periods in which the input signal is in a condition of dropout the output signal remains at a substantially constant frequency, this frequency being substantially equivalent to the frequency of the input signal at the time the dropout commenced.
  • the term “equivalent” what is meant is "equal to or varying from by a fixed constant of proportionality”.
  • the signal conditioning circuit 10 includes four major components.
  • the first of these is means 32 for generating a second signal normally * equivalent to the input signal.
  • the second of the prime components is means 66 for detecting dropout of the input signal.
  • This dropout detecting means 66 preferably receives two inputs which are, respectively, equivalent to the input signal and the second signal.
  • the dropout detecting means 66 assumes a condition of dropout detection in response to a fraction of a period of the second signal occurring without a corresponding fraction of a period of the input signal being detected.
  • the third of the major aspects of the signal conditioning circuit 10 is means 69 for freezing the frequency of the second signal in response to the occurrence of dropout in the input signal. This second signal freezing means 69 is controlled by the dropout detecting means 66. Further * included is means 63 for rendering the frequency of the second signal substantially equal to zero in response to the condition of dropout continuing for more than a preselected period of time.
  • an input 12 serves as a means for receiving a cyclical input signal.
  • This input signal can be either a pulse train or wave train, preferably a square wave train, and should be substantially free from noise.
  • Suitable electronics (not shown) , well known to those skilled in the art, can be provided for filtering noise from the input signal prior to applying the input signal to the signal conditioning circuit 10.
  • This input signal may represent the doppler shift of one wave train relative to another or any other cyclical signal subject to dropout.
  • the input 12 is connected to a first means 14 for multiplying pulses.
  • this first pulse multiplying means 14 is a first pulse doubler which converts waves or pulses of sufficiently great duration into two pulses, one of these two pulse occurring at each transition of the input signal.
  • the first pulse doubler 14 includes a first exclusive OR gate 16 and a first flip-flop 18, preferably a type D flip-flop.
  • a first input 20 of the exclusive OR gate 16 receives the input signal from the input 12.
  • a second input 22 of " the exclusive OR gate 16 is grounded through a .001 microfarad first capacitor 24 and also is connected through a 1.2 k ohm first resistor 26 to the Q output of the first flip-flop " 18.
  • the output 28 of the exclusive OR gate 16 which also serves as the output of the first pulse multiplying means 14, is connected to the clock CLK of the flip-flop 18.
  • the data input D and the Q output are connected one to the other, and the direct set and reset S,R are each grounded.
  • the input 12 is also connected to a signal input terminal 30 of a means 32 for generating a second signal of a frequency substantially proportional to the input signal.
  • the second signal is directly proportional to the input signal.
  • This second signal generating means 32 can be a phase-locked loop or the equivalent.
  • the second signal generating means 32 includes a phase comparator 34 and an oscillator 36 forming a phase-locked loop 37.
  • the oscillator 36 is preferably a voltage controlled oscillator.
  • the phase comparator 34 has first and second inputs 3.8,39 and an output 40.
  • the oscillator 36 has an input 42 and an output 44.
  • the signal input terminal 30 is connected to the first input 38 of the phase comparator 34.
  • a first circuit 46 connects the oscillator output 44 to the phase comparator second input 38.
  • a second circuit 48 connects 'the phase comparator output 40 to the oscillator input 42.
  • Th* 2 first circuit 46 includes a second type D flip-flop 50 which preferably is identical to the first flip-flop 18.
  • the clock CLK of the second flip-flop 50 is connected to the oscillator output 44.
  • the Q output of the second flip-flop 50 is connected to the second input 38 of the phase comparator 34.
  • the second flip-flop 50 serves as a means for dividing the frequency from input to output.
  • the factor of division is two. It is preferred that the factor of multiplication of the first pulse multiplying means 14 and the factor of division of the dividing means 50 be equal.
  • the second circuit 48 includes a first transmission gate 52 having a control terminal 54 and an input and output 56,58.
  • the first transmission gate 52 is closed in
  • the first transmission gate input 56 is connected to the phase comparator output 40 and the first transmission gate output 58 is connected through a 100 k ohm second resistor 60 to the oscillator input 42. As shown in Fig. 1, the oscillator input 42 is also connected, through a series connection of 47 microfarad second capacitor 62 and a 1.2 k ohm third resistor 64, to ground.
  • a second transmission gate 52' having an input 56', an output 58' and a control terminal 54' is connected by its input 56* to the ' .”oscillator input 42.
  • the output 58' of this second transmission gate 52' is grounded through a 100 k ohm fourth resistor 65 such that the charge on the second capacitor 62 can be bled off through the fourth resistor 65 in response to the second transmitting gate 52' being closed.
  • the first and second transmission gates 52,52' are identical and are each one-quarter of an MC 14066B manufactured by Motorola Semiconductor Products, Inc. of Austin, Texas.
  • this dropout detecting means 66 includes a shift register 67 such as, for example, an eight s ' tage MC14015B dual four bit static shift register manufactured by Motorola Semiconductor Products, Inc. of Austin, Texas. It must be emphasized that any shift register configured in a manner analogous to that described below can also be utilized as an element of the dropout detecting means 66.
  • the dropout detecting means 66 in conjunction with the first transmission gate 52, forms the nucleus of means 69 for substantially preventing the occurrence of dropout in the input signal from -commencing a change or aberration, such as rapid frequency decay, in the second signal.
  • the first output stage QI, of the shift register 67 is applied to a second input 70 of a second exclusive OR gate 72.
  • the first input 68 of the second exclusive OR gate 72 is supplied with a constant input +V.
  • the output 74 of the second exclusive OR gate 72 is applied to the control terminal 54 of the first gate 52.
  • the shift register 67, the second exclusive OR gate 72, and the first transmission gate 52 form a third circuit 73 for controlling the application of the phase comparator output 40 to the oscillator input 42.
  • This third circuit is the preferred form of the previously discussed means 69 for freezing the frequency of the second signal in response to dropout of the input signal.
  • This third circuit 73 has first and second controlling inputs 91,92 which are, respectively, the oscillator output 44 and the first pulse multiplying means output 28.
  • the seventh output stage 1 Q3 ⁇ of the shift register 67 is applied to the control terminal 54' of the second transmission gate 52*.
  • the second transmission gate 52' is used to terminate the generation of the second signal a preselected time following the initiation of dropout.
  • the shift register 67 and the second transmission gate 52' form the previously discussed means 63 for rendering the frequency of the second signal substantially equal to zero in response to the condition of dropout continuing for more than a preselected period of time.
  • the oscillator output 44 is also connected to a second means 14' for multiplying pulses.
  • this second pulse multiplying means 14' is a second pulse doubler having a third exclusive OR gate 16' and is otherwise identical in makeup to the first pulse doubler 14.
  • the output 28' of the third exclusive OR gate 16' of the second pulse multiplying means 14' is the signal conditioning circuit output 75.
  • the exclusive OR gates 16,16' of the two pulse doublers 14,14' and the second exclusive OR gate 72 can each be one-quarter of a MC 14070B, manufactured by Motorola Semiconductor.Products, Inc. of Austin, Texas.
  • the type D flip-flops 18,50 can each be one-half of a MC 14013B also manufactured by Motorola.
  • the phase-locked loop 37 can be a MC 14046B and the shift register can be a MC 14015B, both of which are also manufactured by Motorola.
  • a second embodiment of the signal conditioning circuit 10 is set forth in Fig. 2. This second embodiment has an input 12 connected to a first means 14 for multiplying pulses which, as shown in Fig. 2, can be identical to that of the preferred embodiment.
  • the input 12 is also connected to a signal input terminal 30 of a means 32 for generating a second
  • This second signal generating means 32 can be identical to the phase-locked loop 37 of the preferred embodiment.
  • the first circuit 46 of this embodiment is also preferably identical to that previously described.
  • the second circuit 48 of this embodiment differs from that of the first embodiment in that the first and second transmission gates 52,52' are deleted, these being replaced with closed circuits.
  • the second resistor 60 have a value of 510 k ohms
  • the third resistor 64 have a value of 1.2 "k ohms
  • the second capacitor 62 have a value of 10 microfarads.
  • the second embodiment further includes means
  • This dropout detecting means 66 of the second embodiment preferably includes a shift register 67 which preferably is composed of two flip-flops. These flip-flops can be identical to those used elsewhere in this embodiment. As shown, both shift register clock inputs CLK are connected , to the oscillator output 44. Both resets R are connected to the output of the first pulse doubler 14. The data input D of the first flip-flop is connected to a constant voltage source and the Q output of the first shift register flip-flop is connected to the data input D of -the second shift register flip-flop.
  • the shift register 67 has a first output terminal 71 which provides a dropout signal in response to said input signal being in a condition of dropout for a preselected period of time.
  • a signal selector 76 is provided for providing a single output signal at a signal selector output 77, this output being selected from one of the signal conditioning circuit input signal and the conditioned phase-locked loop signal from the Q output of the second flip-flop 50.
  • This signal selector 76 can, of course, assume numerous forms. Preferred is an arrangement of two AND gates 78,80, the outputs of each providing one of the two inputs to a fourth exclusive OR gate 82.
  • the inputs to the first AND gate 78 are the input signal from the signal conditioning circuit input 12 and the Q " output from the second flip-flop of the shift register.
  • the inputs to the second AND gate 80 are the Q output from the second flip-flop and the shift register output terminal 71.
  • the signal selector output 77 is applied to means 84 for multiplying the input and for achieving a cqnstant pulse width output.
  • This multiplying and constant pulse width obtaining means 84 preferably includes of a third and a fourth pulse multiplier
  • Each of these pulse multipliers includes means, preferably a precision monostable, for providing a consistent pulse width.
  • the second of these pulse multipliers 88 can be identical to the first 86 with the exception that the pulse width of the second should be significantly less, preferably by a factor of two, than that of the first. This can be achieved by substitution of the timing resistors in the monostables.
  • a buffer 90 can be included at the output of the multiplying and constant pulse width obtaining means 84. The output of this buffer 90 is the signal conditioning circuit output 75.
  • the first pulse multiplying means 14 produces a pulse at its output 28 for each transition of the doppler input as applied to the input 12. Since there are two transitions per cycle of the doppler input signal, two pulses are produced at the first pulse multiplying means output 28.
  • the input signal applied at input 12 is also applied to the signal input terminal 30, and, hence to the phase comparator first input 38 of the second signal generating means 32. Initially, however, there is no signal applied to the second input terminal 39 of the phase comparator 34. This establishes an imbalance between these inputs 38,39 resulting in the phase comparator 34 establishing an output of lo.gic high pulses. These logic high pulses charge the second capacitor 62.
  • phase comparator 34 This causes the voltage at the oscillator input 42 to rise and, consequently, produce an output of increasing frequency.
  • the logic , high pulses from the phase comparator 34 will continue to charge the second capacitor 62 until the frequency of the signal applied to the second phase comparator input 39 exceeds that of the first phase comparator input
  • phase comparator 34 will output logic low pulses causing the second capacitor 62 to discharge. " The output frequency of the oscillator 36 will then drop and the process will repeat until the phase-locked loop has managed to lock itself onto the phase and frequency of the doppler input signal applied at input 12. At this point the output of the oscillator 36 will be twice that of the doppler input signal. This factor of two difference is due to the divide by two effect of the second flip-flop 50.
  • the first pulse multiplying means 14 and the shift register 67 form a means 66 for detecting dropout. " With the oscillator output 44 being applied to both clocks CLK of the shift register 67, and the output 28 of the first pulse doubler 14 being applied to both resets R A , R_., the outputs of the shift register 67 are always low so long as there is no dropout in the input signal. In response to dropout, however, an output does occur. In the dropout situation, no reset signals are applied to the shift register, thus allowing the output stages QI, - Q3 token to sequentially store high signals.
  • the dropout of the input signal must occur for at least 3 1/2 periods of the signal to allow the seventh stage of the shift register 67, Q3B, to go to the logic high state.
  • the first stage QI, of the shift register 67 will, of course, go to the logic high state one-half of a phase following dropout of the inut signal.
  • the first transmission gate 52 of the second circuit 48 provides a highly advantageous aspect to the operation of the second signal generating means 32.
  • the second exclusive OR gate 72 applies a signal to the control terminal 54 of the first transmission gate 52, closing the transmission gate -52 and*, hence, closing the second circuit 48.
  • This permits the phase comparator output 40 to charge and discharge the second capacitor 62, which itself controls the oscillator 36.
  • the first stage QI, clocks high and the output of the second exclusive OR gate 72 terminates. Withdrawing the signal, which until then was applied to the control terminal 54 of the first transmission gate 52 disables this gate, opening the second circuit 48.
  • the second capacitor 62 can then discharge only through the oscillator input 42. As the Oscillator 36 has a very high input impedence, charge depletion of the second capacitor 62 will be negligible during dropout. This results in output of the phase locked loop 37 being initially frozen during dropout, thereby preventing the output frequency being "pulled down" by the phase comparator due to absence of the input signal,
  • the second signal generating means 32 not continue to provide an output indefinitely upon absence of the input signal.
  • This feature is provided by the second transmission gate 52' and the electronics associated with it.
  • the second transmission ga-te 52' is enabled when the seventh stage Q3-, of the shift register is clocked high. As previously stated, the seventh stage will clock high after 3 1/2 phases of input signal dropout.
  • the second capacitor 62 In response to the second transmission gate 52' being enabled, the second capacitor 62 will discharge through the fourth resistor 65 to ground.
  • the values of the resistors are such that the output of the phase-locked loop 37 will terminate about 2.5 seconds following the termination of the signal input at input 12. Of course, resumption of an input will open the second transmission gate 52 1 . In many applications dropouts rarely occur for more than two cycles.
  • the output of the second signal generating means 32 is taken directly from the oscillator output 44 and hence is twice that of the input doppler signal.
  • OMPI applies a further multiplication Of two yielding a total multiplication of four for the dropout compensating circuit 10 as a whole.
  • the output signal is at all times taken from and is directly proportional to the oscillator output 44.
  • the phase-locked loop 37 tracks the input signal with great accuracy and in the dropout situation the output of the second signal generating means 32 is frozen at the frequency of the input signal at the time immediately preceeding the dropout.
  • the operation of the second embodiment of the dropout compens-ating circuit differs somewhat from that of the preferred embodiment.
  • the first and second transmission gates 52,52* of the preferred embodiment do not exist in the second embodiment.
  • the output of the phase comparator 34 decreases during dropout due to the absence of the input signal.
  • this embodiment does not- include the second transmission gate 52' of the preferred embodiment, the phase-locked loop 37 will not continuously provide an output once the input signal has been removed. This is due to the fact that the phase comparator 34 controls the second capacitor 62 even in the dropout situation. Hence after a sufficiently great time the output will go to zero, matching the absence of input.
  • the second embodiment also includes a signal selector 76.
  • This signal selector 76 applies only one of the input signal and the oscillator output signal to the signal conditioning circuit output 75.
  • the NOT Q output of the shift register 67 is in a logic high condition.
  • the first AND gate 78 will provide an output for each existing cycle of the input signal.
  • the second of the inputs to the first AND gate 78 remains low and the first AND gate 78 will provide no output to the exclusive OR gate 82.
  • the second AND gate 80 in response to the input signal being in a dropout-free condition the Q output of the shift register 67' is in a logic low condition and the second AND gate 80 can provide no output. In a dropout condition, however, the Q output of the shift register 67 attains a logic high state and the output of the second AND gate 80 will follow the Q output of the second flip-flop 50.
  • he second embodiment of the signal conditioning circuit 10 provides an output proportional to the input signal when the input signal is free from dropout and provides an output proportional to the phase-locked loop output in response to the input being in a dropout condition.

Abstract

Un circuit de conditionnement de signaux à compensation de perte (10) est spécialement approprié au conditionnement de signaux utilisés dans des appareils de contrôle de la variation de fréquence due à l'effet Doppler. Le circuit (10) comprend une boucle à verrouillage de phase (32) sensible à un signal d'entrée en (30) pour générer un second signal en (44) d'une fréquence sensiblement directment proportionnelle au signal d'entrée. Ce circuit (10) produit une sortie sur la ligne (75) qui poursuit l'entrée en (12) avec une grande précision et sans les absences occasionnelles d'une ou plusieurs périodes des signaux d'entrée, phénomène connu sous le nom de perte par affaiblissement des signaux (dropout).
EP81902992A 1981-09-24 1981-09-24 Circuit de conditionnement de signaux a compensation de la perte doppler Withdrawn EP0088755A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1981/001300 WO1983001120A1 (fr) 1981-09-24 1981-09-24 Circuit de conditionnement de signaux a compensation de la perte doppler

Publications (1)

Publication Number Publication Date
EP0088755A1 true EP0088755A1 (fr) 1983-09-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP81902992A Withdrawn EP0088755A1 (fr) 1981-09-24 1981-09-24 Circuit de conditionnement de signaux a compensation de la perte doppler

Country Status (6)

Country Link
EP (1) EP0088755A1 (fr)
JP (1) JPS58501519A (fr)
BR (1) BR8109043A (fr)
IT (1) IT1190998B (fr)
WO (1) WO1983001120A1 (fr)
ZA (1) ZA824408B (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4914638A (en) * 1984-02-28 1990-04-03 Applied Design Laboratories, Inc. Doppler effect speedometer
US4713665A (en) * 1984-05-14 1987-12-15 Deere & Company Ground speed sensor
AU575396B2 (en) * 1984-05-14 1988-07-28 Deere & Company Ground speed sensor
US4728954A (en) * 1984-12-20 1988-03-01 Deere & Company Ground velocity sensor with drop-out detection
FR2624976B1 (fr) * 1987-12-18 1990-10-12 Peugeot Dispositif de mesure de la vitesse d'un vehicule
DE69406477T2 (de) * 1993-03-01 1998-03-19 Nippon Telegraph & Telephone Phasenregelkreis mit Abtast- und Halteschaltung

Family Cites Families (7)

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Publication number Priority date Publication date Assignee Title
US4020490A (en) * 1974-11-20 1977-04-26 Decatur Electronics, Inc. Traffic radar and apparatus therefor
US4052722A (en) * 1975-09-15 1977-10-04 Decatur Electronics, Inc. Traffic radar and apparatus therefor
US4021681A (en) * 1976-01-22 1977-05-03 Chrysler Corporation Resonant sensor using a phase locked loop detector
CH609464A5 (fr) * 1977-02-16 1979-02-28 Siemens Ag Albis
US4186397A (en) * 1977-09-06 1980-01-29 Board Of Regents For Education Of The State Of Rhode Island Short range precision navigation and tracking system and method therefor
US4185246A (en) * 1978-02-27 1980-01-22 Schlumberger Technology Corporation Circuit for reducing transients by precharging capacitors
US4276548A (en) * 1979-06-04 1981-06-30 Solfan Systems, Inc. Microwave speed meter

Non-Patent Citations (1)

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Title
See references of WO8301120A1 *

Also Published As

Publication number Publication date
WO1983001120A1 (fr) 1983-03-31
IT8223218A0 (it) 1982-09-13
BR8109043A (pt) 1983-11-08
IT1190998B (it) 1988-02-24
JPS58501519A (ja) 1983-09-08
ZA824408B (en) 1983-04-27

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