EP0085593A1 - Device to read and write to a page memory of a CRT terminal - Google Patents

Abstract

This device for reading and writing to the page memory (1) of a cathode-screen terminal, in which access to the page memory occurs periodically in time with an internal clock signal (E) and comprises successively in the course of a single period of the internal clock signal (E) an emplacement reserved for reading and an emplacement reserved for writing, this device comprising means (16) for ensuring two readings of the page memory (1) in the course of a single emplacement reserved for reading, this allowing the number of characters displayed on the cathode screen to be doubled. Application to cathode-screen terminals. <IMAGE>

Description

The present invention relates to a device for reading and writing the page memory of a terminal with a cathode screen.

The data to be displayed on the cathode screen of a terminal are stored, before their visualization on the screen, in a random access memory, called page memory, after having been previously recorded therein, either remotely by a computer in the context of '' a remote processing type application, either locally by an operator who enters this data using a keyboard associated with the screen.

The writing of the data in the page memory is managed by a microprocessor which in particular determines the address for writing the data in this memory.

The reading of the data in the page memory is managed by a display controller which in particular determines the address for reading the data in this memory.

The fundamental display unit on the screen, corresponding to the point of impact of the electron beam on this screen, is called point.

A rectangle of lm points, including 1 points arranged in the vertical direction and m points arranged in the horizontal direction, determines a display cell, which allows the visualization of a letter, a number, or any other symbol, by proper control of the color of the different points of this cell.

The m consecutive points of a display cell, arranged horizontally, form a character.

The data stored at an address of the page memory generally corresponds to a character. Since the screen is scanned horizontally, the consecutive characters located on the same row of the screen are read in sequence.

Access to the page memory takes place periodically at the rate of an internal clock signal and any access to the page memory comprises a space reserved for reading followed by a space reserved for writing. The space reserved for reading is used systematically, so as to ensure a permanent refreshment data displayed on the screen. The space reserved for writing is used only when new data received must replace the data previously stored.

In most terminals known so far, the display is done at the rate of forty characters per row and the time allocated to reading and writing a character in the page memory is fixed equal to the time of microprocessor cycle.

According to German patent application No. 3 022 118, there is also known a device for reading and writing the page memory making it possible to display eighty characters per row without - increasing the time allocated for reading and when writing page memory.

The subject of the present invention is a device for reading and writing the page memory making it possible to view either eighty or forty characters per row, by virtue of a simple control logic and having the same hardware structure in both cases. .

According to the invention, the device for reading and writing the page memory of a cathode-screen terminal, in which the accesses to the page memory are carried out periodically at the rate of an internal clock signal and successively comprise, during the same period of the internal clock signal, a space reserved for reading and a space reserved for writing, this device comprises means for ensuring two successive readings or a single reading of the page memory during the same space reserved for reading, depending on whether you want to multiply or not, by two the number of characters displayed on the cathode screen.

• la figure 1 est un schéma de principe de la mémoire de page et de son dispositif de lecture et d'écriture ;
• la figure 2 est un schéma détaillé de la logique de commande faisant partie du dispositif de lecture et d'écriture ;
• la figure 3 est un diagramme des temps destiné à illustrer le fonctionnement de la logique de commande représentée à la figure 2.

The objects and characteristics of the present invention will appear more clearly on reading the following description of an exemplary embodiment, said description being made in relation to the attached drawings, in which:

• Figure 1 is a block diagram of the page memory and its reading and writing device;
• Figure 2 is a detailed diagram of the control logic being part of the reading and writing device;
• FIG. 3 is a timing diagram intended to illustrate the operation of the control logic represented in FIG. 2.

In Figure 1 there is shown a page memory 1 fitted to a cathode screen terminal. This page memory 1 is in fact broken down into two memories, a memory 2, called character memory, containing the characters to be displayed on the screen, and a memory 3, called attribute memory, containing the attributes of these characters, that is, information about how these characters should be displayed, for example with or without underlining, with or without blinking, etc., so as to better attract the attention of the operator.

Memories 2 and 3, which are read-only memories, contain twice as much data as in the case where the display is made only at the rate of forty characters per row.

By way of example, in the case where the display is made at the rate of twenty-five rows of eighty characters, the memories 2 and 3 have a capacity of 2K words. As an example also, a character is coded on eight binary elements and an attribute on four binary elements, the memory 2 then having a capacity of 2K words of eight binary elements and the memory 3 a capacity of 2K words of four binary elements .

The data inputs of memories 2 and 3 are connected, via a routing circuit 4, to the data bus 5 of a microprocessor 6 fitted to the terminal.

The microprocessor 6 being a microprocessor with words of eight binary elements, of the type EF 6809 from EFCIS, the routing circuit 4 is necessary to route the output data of the microprocessor either to the character memory 2, or to the memory of attributes 3.

The switching circuit 4 is also necessary to prevent the data read from being transmitted to the microprocessor via the data bus 5 during the page memory read operations.

The routing circuit 4 comprises a first set 7 of eight doors with three-state outputs mounted in a first direction, shown schematically using a single door with three-state outputs 8 mounted in this first direction, and eight doors with three-state outputs, mounted in a second direction, shown schematically using a single door with three-state outputs 9, mounted in this second direction.

The doors 8 are each provided with a data input connected to one of the eight data wires constituting the data bus 5, and an output connected to one of the eight data inputs of the character memory 2 via a data bus 10.

The doors 9 are each provided with a data input constituting the data bus 10, and an output connected to one of the eight data wires constituting the data bus 5.

The routing circuit also includes a second set 12 of doors with three-state outputs, itself comprising eight doors with three-state outputs mounted in a first direction, represented diagrammatically by a single door 13, and eight doors with three-state outputs mounted in a second direction, represented schematically using a single door 14. Each of the doors 13 is provided with a data input connected to one of four wires taken from among the eight wires constituting the data bus 5, and an output connected to one of the four data inputs of the attribute memory 3 via a four-wire data bus 15. Each of the doors 14 is provided with a data input connected to one of four wires constituting the data bus 15 and an output connected to one of four wires taken from the eight wires constituting the data bus 5 (the same wires as for the entrances to doors 13). Each of the sets 7 and 12 is provided with a validation input which receives an R / W signal for selection of reading from the page memory, supplied by the microprocessor 6, and with a control input connected respectively to a first and to a second output of a control logic 16, respectively supplying signals CS ₀ and CS _I for switching control.

The address inputs of memories 2 and 3 are connected to the outputs of a multiplexer 17 provided with first data inputs connected to an address bus 18 of the microprocessor 6 and of second data inputs connected to first outputs, called outputs addresses, a controller display 19. The display controller 19 is constituted for example by the reference integrated circuit EF6845 (EFCIS).

The multiplexer 17 is also provided with a control input connected to a third output of the control logic 16, providing a signal MUX for selecting the address of the page memory.

The memories 2 and 3 are also provided with a read-write selection input connected respectively to a fourth and to a fifth outputs of the control logic 16, respectively supplying signals (R / W) ₀ and (R / W ) for reading / writing selection of the page memory.

In the context of the example embodiment described, where the memories 2 and 3 have a capacity of 2K words, twelve binary elements are necessary for the addressing of these memories. This is why the address outputs of the display controller 19 provide twelve binary elements MA ₀ to MA ₁₁ , used for reading the page memory. The address bus 18 likewise supplies twelve binary elements, A ₁ to A _{12 '} used for writing the page memory.

In the context of the exemplary embodiment described, where the microprocessor 6 is a word microprocessor of eight binary elements, the address bus 18 provides an additional binary element A ₀ indicating whether the data to be written in the page memory is a character, in which case it is the set of three-state doors which must be validated, or an attribute, in which case it is the set 12 of three-state doors which must be validated.

The display controller 19 is provided with a clock input which receives a clock signal HC, called a character clock, of frequency equal to the frequency of the characters on the screen, supplied by a sixth output of the control logic. 16.

The display controller 19 is also provided with outputs providing HSYNC and VSYNC signals intended to ensure the horizontal and vertical synchronization of the cathode screen.

The display controller 19 is also provided with outputs providing a signal RA of the read-only memory of a character generator 21.

The character generator 21 is moreover provided with first data inputs connected to the data bus 10 (itself connected to the outputs of the character memory 2), by means of a set 22 of eight flip-flops of type D represented schematically using a single scale.

The character generator 21 is also provided with second data inputs connected to the data bus 15 (itself connected to the outputs of the attribute memory 3) as well as to two outputs of the display controller 19, providing as the memory attribute information about how the data is displayed on the screen. This connection is also made by a set 22 ′ of six flip-flops of type D, represented schematically using a single flip-flop.

The clock input of flip-flops D22 and 22 'receives a STROBE signal supplied by a seventh output of the control logic 16.

The character generator 21 is also provided with a data loading control input which receives an LD / SH signal supplied by an eighth output of the control logic 16.

The character generator 21 is also provided with a clock input which receives a clock signal HP, called first point clock signal, of frequency equal to the frequency of the points on the cathode screen, supplied by a ninth output of the control logic 16. The output of the character generator 21 provides a VIDEO signal used for display on the cathode screen.

We will now describe the control logic 16 represented in FIG. 2.

The control logic 16 comprises a shift register 22 "of eight binary elements, provided with a data input which receives a clock signal E which is the clock signal E, of period equal to the cycle time of the microprocessor , supplied by the microprocessor 6, inverted by means of an inverter 23, and a clock input which receives a second dot clock clock signal supplied by a clock 23 '.

The shift register 22 "is provided with eight outputs providing signals A ₁ , _B1 , ... _Hl identical to the clock signal E but shifted respectively in time with respect to the clock signal E by one, two, ... eight periods of the dot clock clock signal.

By way of example, the frequency of the point clock clock signal HP is equal to 18.432 MHz, or to 9.216 MHz depending on whether a line has eighty or forty characters, (the frequency of the clock signal hp then being equal at 18.432 MHz), the frequency of the clock signal character HC is equal to 1.8432 MHz or 0.9216 MHz, depending on whether a line has eighty or forty characters, and the frequency of the clock signal E is equal to 0.9216 MHz (the ratio n between the frequencies nF and F of the signals hp and E being in this case equal to 20).

The control logic 16 also includes a counter 24 with four binary elements whose data loading inputs are set to logic level zero, whose clock input receives the point clock signal hp. The counter loading control input 24 is connected to the output of a NAND gate 25 itself provided with a first input connected to the output F of the shift register 22 "and a second input connected to the output G of the shift register 22 "via an inverter 26.

The counter 24 is provided with four outputs providing signals A ₂ , B _{2 ′} C ₂ and D ₂ of frequencies respectively equal to the frequency of the clock signal point hp divided by two, four, eight and sixteen.

The control logic 16 also includes a NAND gate 28 provided with a first input which receives the signal H ₁ , and a second input which is connected to the output of an AND gate 29 itself provided with two inputs which receive the signals B ₂ and C ₂ . The control logic 16 also includes a flip-flop D 29 ′, the input D of which is brought to the logic level "one", the clock input of which is connected to the output of the NAND gate 28 via d an inverter 30, whose reset input receives the clock signal E and whose output Q provides the signal MUX.

The output Q of the flip-flop D 29 ′ is connected to a first input of two NAND gates 31 and 32, the AND gate 31 also receiving on a second input the binary element A0 supplied by the microprocessor 6 and accompanying the address write in the page memory, and the NAND gate 32 also receiving on a second input the binary element A _O inverted by means of an inverter 33.

The outputs of the NON AND gates 31 and 32 respectively provide the signals CS ₀ and CS ₁ applied respectively to the validation inputs for sets of doors with three-state outputs 7 and 12.

The control logic 16 also comprises two NAND gates 34 and 35 each provided with a first input which receives the R / W signal for reading / writing selection from the page memory by the microprocessor 6, inverted by means of a inverter 36, signal R / W inverted being noted R / W. The NON AND gates 34 and 35 are moreover provided with a second input connected respectively to the outputs of the NON AND gates 31 and 32 by means of inverters 37 and 38. The outputs of the NOT AND gates 34 and 35 provide the signals (R / W) ₀ and (R / W) applied respectively to the read-write selection input of page memory 2 and attribute memory 3.

The page memory read-write device according to the invention makes it possible to display the data stored in the page memory either at the rate of forty characters per row or at the rate of eighty characters per row.

Consequently, certain signals supplied by the control logic are obtained on the outputs of multiplexers which receive two categories of signals, some intended for the case where the display is done at the rate of forty characters per row the others in the case where the display is done at the rate of eighty characters per row.

Thus the signal STROBE for controlling the flip-flops D 22 and 22 'is obtained at the output of a multiplexer 39 which receives on a first input (corresponding to forty characters) the signal C ₂ and on a second input (corresponding to eighty characters ) the output signal of a NAND gate 40. The NAND gate 40 has a first input connected to the output of the NAND gate 28 and a second input connected to the output of a NAND gate AND 41 itself provided with two inputs which receive the signals A and D _{2 respectively} .

Similarly, the character clock signal HC is obtained at the output of a multiplexer 42 which receives on a first input (corresponding to forty characters) the signal E _l and on a second input (corres laying out eighty characters) signal C ₂ .

Likewise the signal LD / SH for controlling the loading of the character generator 21 is obtained at the output of a multiplexer 43 which receives on a first input (corresponding to forty characters) the signal LD / SH ₄₀ output from the inverter 30 and on a second input (corresponding to eighty characters) an LD / signal SH ₈₀ obtained on the counter output 24.

Likewise finally, the point clock signal HP is obtained at the output of a multiplexer 44 which receives a first input (corresponding to forty characters), the signal A ₂ and on a second input (corresponding to eighty characters) the signal point clock clock with frequency 18.432 MHz.

The multiplexers 39, 42, 43 and 44 are controlled by a signal S 40/80 which can take two different logic levels depending on the number of characters per row that the operator wishes to display.

The operation of the page memory read-write device shown in FIGS. 1 and 2 is now described in relation to FIG. 3.

In the first line of FIG. 3, a period of the clock signal E provided by the microprocessor 6 is shown, and in the second line the reverse clock signal E . Signal E has a logic level 1 during the first half period and a logic level 0 during the second half period.

In the third line of FIG. 3, the point clock signal hp is shown.

The following lines show the signals A to H ₁ output from the shift register 22 ". These signals are identical to the signal E and are offset in time with respect to this signal respectively by one, two, ... eight periods of the clock signal point hp The following line shows the signal LD for commanding the loading of the counter 24 obtained at the output of the NAND gate 25.

The signal LD has a logic level "one" only during the seventh period of the clock signal point hp occurring during the first half-period of the clock signal É, which allows synchronization nize the subsequent passages by the value "zero" of the counter 24 during each seventh period of the clock signal point hp occurring during each first half period of the clock signal E.

The following lines show the signals A2, B2, C ₂ and D ₂ from the output of the counter 24.

According to the form of the signals B ₂ , C ₂ and H ₁ , the signal (LD / SH ) Output ₄₀ of the inverter 30 has a level "one" only during the fourth period of the clock signal point hp within each second half-period of the clock signal E.

The circuit formed by the NAND gates 31, 32, 34 and 35 and by the inverters 33, 36, 37 and 38 therefore selects the page memory for writing only during the fourth period of the point clock signal hp at the inside each second half-period of the clock signal E. The rest of the time, and in particular during each first half-period of the clock signal E and during the first three periods of the clock signal dot hp inside of each second half-period of the clock signal E, the page memory is selected for reading.

As the data is stored in the page memory at the rate of one character per memory address, it is necessary in the case of eighty characters per row to address the page memory twice to two successive addresses, when of each read or write operation. In the case of forty characters per line, only one address is necessary. As the page memory read addresses are supplied by the display controller at the rate of the character clock signal, it is therefore necessary to generate two character clock signals, one (HC ₄₀ ) for forty characters, the other (HC ₈₀ ) for the case of eighty characters. Thus the signal HC ₄₀ , equal to the signal E ₁ , has an active edge during the fifth period of the clock signal inside each first half-period of the clock signal E. And the signal HC ₈₀ , equal at signal C ₂ , has a first and a second active edge respectively during the first period of the clock signal point hp within each first half-period of the clock signal E and during the first period of clock dot hp inside every second half signal period clock E .

Due to the relatively low working speed of the character generator 21 in relation to the time of access to the page memory, it is necessary to interpose flip-flops D 22 and 22 'forming a buffer register, between the outputs of the page memory and the data inputs of the character generator 21. The STROBE signal which constitutes the clock signal of these D flip-flops is therefore different depending on whether the display is made at the rate of forty (STROBE ₄₀ ) or four- twenty (STROBE ₈₀ ) characters per row.

The signal STROBE ₄₀ , which is equal to the signal C ₂ , has an active edge after the active edge of the signal HC _{40 '} and for example, in the context of the example embodiment described, during the first period of the signal clock point hp during each second half-period of the clock signal E, the difference between the active edges of the signals HC ₄₀ and STROBE ₄₀ being at least equal to the access time for reading the page memory increased by access time to the memories of the display controller 19.

The signal STROBE ₈₀ which is the output signal of the NAND gate 40 has a first active edge after the first active edge of the signal HC _{80 '} and for example, within the framework of the example of embodiment described, during the fifth period of the clock signal point hp within each first half-period of the clock signal É. The STROBE ₈₀ signal has a second active edge after the second active edge of the HC ₈₀ signal, and for example, within the framework of the example embodiment described, during the third period of the clock signal dot hp inside. of each second half-period of the clock signal É. The difference between the active edges of the HC ₈₀ and STROBE ₈₀ signals is at least equal to the read access time of the page memory.

The data temporarily stored in flip-flops D 22 and 22 'are taken into account by the character generator 21 during the active edges of the LD / SH signal which is also different depending on whether the display is made at the rate of forty characters per line. (LD / SH ₄₀ ) or at the rate of eighty characters per line (LD / SH ₈₀ ).

The LD / SH signal ₄₀ which is the output signal from the inverter 30 has an active edge after the active edge of the STROBE ₄₀ signal and for example, in the context of the example embodiment described, during the fourth period of the point clock signal hp within each second half-period of the clock signal E, the difference between the active edges of the STROBE ₄₀ and _L D / SH ₄₀ signals being at least equal to the delay time of the flip-flops 22 and 22 '.

The LD / signal SH _{80 '} which is the signal supplied by the counter output 24, has a first active edge after the first active edge of the STROBE ₈₀ signal and for example, in the context of the example embodiment described, during the sixth period of the clock signal point hp within the first half-period of the clock signal E. The signal LD / SH ₈₀ has a second active edge after the second active edge of the STROBE ₈₀ signal and for example, in the context of the example embodiment described, during the sixth period of the point clock signal hp within the second half -period of clock signal E.

Reading of the page memory by the display controller is thus done periodically at each microprocessor cycle, so as to allow the cathode screen to be refreshed at the rate of scanning of this screen. On the other hand, the writing of the page memory by the microprocessor is only done in the event that data is to be modified in the page memory, so that a single writing operation per microprocessor cycle is sufficient, the case where data would have to be renewed at each cycle being possible but unrealistic because the speed of the data received is limited by the transmission speed.

Claims (5)

1. Device for reading and writing the page memory (1) of a cathode-screen terminal, in which the accesses to the page memory are carried out periodically at the rate of an internal clock signal (E ) and successively comprise, during the same period, the internal clock signal (E), a space reserved for reading and a space reserved for writing, characterized in that it comprises means (16) for ensuring two successive readings or a single reading of the page memory (1) in the same space reserved for reading, depending on whether one wants to multiply by two, or not, the number of characters displayed on the cathode screen . 2. Device according to claim 1, comprising a clock providing the internal clock signal, of frequency F, and a point clock signal (hp) of frequency nF, the point being the fundamental display unit on the cathode-ray screen, characterized in that the means (16) for ensuring two successive readings, or only one reading, of the page memory in the same space reserved for reading comprise a counter (24) of the number of periods of the clock signal point (hp) of frequency nF within each period of the internal clock signal, and a circuit for detecting the value ¥ + m of this counter (with 1 <m <

), the passage of the counter through this value corresponding to the selection in writing of the page memory, the page memory being selected for reading during the preceding periods of the point clock signal (hp) of frequency nF. 3. Device according to claims 1 and 2, wherein the read addresses of the page memory (1) are generated by a display controller (19), at a rate equal to the frequency of a character clock signal (HC), a character consisting of consecutive points located on the same row of the cathode screen, and the data corresponding to the display of the different characters being stored at the different addresses of the page memory (1), characterized in that 'it comprises a character clock signal generator, which provides a first character clock signal (HC,' having two active edges respectively when the counter (24) passes by the values p (with 1 <p <

) and Q (with q> p and q <

+ m), and a second character clock signal (HC ₄₀ ) having a single active edge when the counter (24) passes by the value a (with 1 <a <

+ m), the choice between the first and the second character clock signal depending on the number of characters to be displayed on the screen. 4. Device according to claims 1, 2 and 3, wherein the data read from the page memory (1) are previously converted, before their visualization, into a code compatible with their visualization on the cathode screen, by a generator. characters (21), and in which a buffer register (22,22 ') is provided between the outputs of the page memory (1) and the data inputs of the character generator (21), characterized in that the buffer register (22, 221 is activated during the passage of the counter (24) either by the values p + r and q + r (r periods of the point clock signal (hp) of frequency nF being necessary to perform read access to the page memory), either by the value a + r, depending on whether or not you want to double the number of characters displayed on the screen. 5. Device according to claim 4, characterized in that the character generator (21) is loaded by the data obtained at the output of the buffer register (22, 22 ') during the passage of the counter (24) either by the values p + r + s and q + r + s (s periods of the point clock signal (hp) of frequency nF corresponding to the delay time of the buffer register (22, 22 ')), either by the value a + r + s, depending on whether or not you want to double the number of characters displayed on the screen.

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