Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04W—WIRELESS COMMUNICATION NETWORKS
  • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
  • H04W88/02—Terminal devices
  • H04W88/022—Selective call receivers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/0079—Receiver details
  • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Definitions

• This invention relates to a radio receiver (pager) decoding system and a pager arranged to deploy said system.
• pager radio receiver
• One system producing a code format for use in wide area radio paging is outlined in Appendix A of A Standard Code for Radicpaging (A. report of the studies of the British Post Office Code Standardisation Advisory Group (POCSAG) 1578/1979.
• a radio receiver (pager ) decoding system arranged to receive a transmission signal that comprises a periodically recurring synchronization codeword separating first, second and subsequent batches of codewords in a plurality of frames, characterised in that the system has means for decoding after the receipt of an erroneous synchronization codeword or the loss thereof at its immediate specific decoding frame by virtue of the known time in the transmission between an obtained synchronization codeword immediately before the erroneous or lost synchronization codeword and said specific decoding frame immediately following said erroneous or lost synchronization codeword.
• decode operations are terminated after two consecutive erroneous synchronization codewords are received or lost and are not taken-up again until a synchronization codeword is correctly received.
• Figure 2 is a diagram s imilar to that of Figure 1 but showing a signal format with the receipt of an erroneous or the loss of a synchronization codeword (SC) and the ability of the system of the invention to decode.
• SC synchronization codeword
• Figure 3 is a block diagram showing an embodiment of a pager for incorporation of the system of the present invention.
• Figure 4 is a flow diagram of operations to be performed by one decoding circuit.
• Figure 5 is a detail flow diagram relating to a part of Figure 4.
• Figure 6 is a schematic.
• Figure 1 is shown the well known POCSAG signal format. in which a transmission comprises a preamble followed by batches of complete codewords, each batch beginning with a synchronisation codeword (SC).
• SC synchronisation codeword
• Each transmission starts with a preamble to permit a pager to attain bit synchronization and to prepare it to acquire word synchronization.
• the preamble is a pattern of reversals, 101010 ... repeated for a period of at least 576 bits, i.e. the duration of a batch plus a codeword.
• any batch codewords are transmitted comprising a synchronization codeword followed by 8 frames each containing 2 codewords. The frames are numbered 0 to 7 and the pager population is similarly
• Each pager is allocated to one of the 8 frames according to the 3 least significant bits (1sb) of its 21 bit identity and will only examine address codewords in that frame. Therefore each pager's address codewords must only be transmitted in the frame that is allocated to those codewords.
• Message codewords for any receiver may be transmitted in any frame but will follow, directly, the associated address codeword.
• a message may consist of any number of codewords transmitted consecutively and may embrace one or more batches but the synchronization codeword must not be displaced by message codewords.
• Message termination is indicated by the next address codeword or idle codeword. In any frame an idle codeword will be transmitted whenever there is no address codeword or message codeword to be transmitted.
• Preamble (P) commences and is followed by synchronization codeword SC and SC 2 , SC 4 ,
• SC 5 , SC 6 ; SC 3 and SC 7 are erroneous or lost owing to impulsive noise, but decoding is still achieved in the batch follcwir. ⁇ SC 3 , and SC 7 since both the respective decode frames are at predetermined time distance Z from SC 2 and SC 6 .
• a block diagram of a pager unit includes a decoding circuit.
• the radio pager comprises a receiver unit 10 having a binary detector 12, which is responsive to receiver 10 and is also responsive to a data enable signal from a microprocessor unit 20 over line 11 and which transmits received pulses to unit 20 over line 13.
• Unit 20 in one embodiment of the invention is an MC 146805 8-bit microprocessor by Motorola.
• an identity ROM read only memory
• program ROM program ROM
• support I.C. 26 The identity ROM 22 is programmed, using fusable links, for example, with the unique identity number of the specific pager.
• the identity number has two separate parts (1) a base identity code
• Each pager in the pager population is assigned one of eight possible frame numbers within a batch.
• the identity ROM 22 is plug-interchangeable.
• Each pager can respond to four different paging addresses and accordingly generates four distinguishable alerting tones.
• the four different paging addresses are calculated by the unit 20 utilising the base identity code contained in the identity ROM 22, as will be described in greater detail below.
• the program ROM 24 contains the computer program which controls the operation of the unit 20 to carry out the desired decoding functions of the decoding circuit.
• the portion of the computer program which specifically pertains to the decoding system of the present invention is attached hereto in source code form as given in
• the support I.C. 26 is a general purpose support circuit which, in the context of the present invention, performs three functions. First, it generates and regulates the secondary supply for the unit 20, the identity ROM 22, and the program
• ROM 24 contains a timer circuit known as the "deadman timer" (DMT), whose function is to reset the unit 20 after a predetermined interval in the event that a specific instruction either is not received or remains in the instruction register for an excessive period.
• DMT deadman timer
• Deadman timer is to prevent the decoder circuit from being held up in a lengthy software loop.
• the support I.C. 26 tests the primary power supply level on command and returns an indication of its condition.
• unit 20 generates the paging alert signals over line 27 to audio frequency amplifier 23 and ultimately transducer 30.
• a power supply switch 36 is responsive to an enable signal from unit 20 over line 35. When the power supply switch 36 is enabled, the receiver power suppiy is connected to receiver 10 and to binary detector 12 over line 37. Battery 40 provides the primary power supply.
• Switch 3S is a user-operated on/off switch.
• Switch 32 is a "cancel" switch, the closure of which cuts short a sounding paging alert.
• Switch 34 is a switch used to make a selection between "normal mode" and "memory mode”.
• the pager In “memory mode" upon receipt of a paging request the pager does not generate the paging alert, but it stores the page request in a memory allocated for such purpose in the unit 20.
• switch 34 When switch 34 is switched over to the "normal mode", or when the "cancel" switch 32 is depressed at any time, any page requests stored in memory are sequentially read out and their corresponding audible alerts (each uniquely distinguishable) are generated to the pager user.
• Word synchronization 2 checks the number of errors in the received synchronization codeword and if less than or equal to the error criterion clears the excess error flag and returns (122) (F) to decode. If the number of errors is greater than the prescribed error criterion then the flag is checked to see if it is already set (123). If clear the flag is then set (124) and the routine returns to decode. If the flag is already set (Y)(123), indicating that the previous synchronization word was received with excessive errors, the routine returns to the bit synchronization and transmission squelch routine (108) without decoding. Thus decode operations are terminated after two consecutive erroneous synchronization codewords have been received.
• the system of the invention gives decoding after the erroneous receipt or loss of one synchronization codeword (SC) such as SC 3 or SC 7 for example ( Figure 2) but will not give decoding if the noise and the loss extends to a second consecutive synchronization codeword and will then revert to the acceptance of the next synchronization codeword (SC) that is obtained correctly, this is shown schematically in Figure 6.
• SC 1 is correct and decode occurs at d 1 .
• SC 3 is lost and there are too many erronious synchronization codewords to give a decode at X.
• SC 4 is correct and decode occurs at d 3 .

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Mobile Radio Communication Systems (AREA)

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• 1981
  • 1981-06-16 GB GB8118532A patent/GB2100486B/en not_active Expired
• 1982
  • 1982-05-28 EP EP19820901529 patent/EP0080467A1/de not_active Ceased
  • 1982-05-28 JP JP50160982A patent/JPS58501487A/ja active Pending
  • 1982-05-28 WO PCT/GB1982/000160 patent/WO1982004514A1/en not_active Application Discontinuation

Non-Patent Citations (1)

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