EP0078634B1 - Koppelfeld zum Gebrauch in einem Zeitmultiplex-Vermittlungssystem - Google Patents

Koppelfeld zum Gebrauch in einem Zeitmultiplex-Vermittlungssystem Download PDF

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Publication number
EP0078634B1
EP0078634B1 EP82305585A EP82305585A EP0078634B1 EP 0078634 B1 EP0078634 B1 EP 0078634B1 EP 82305585 A EP82305585 A EP 82305585A EP 82305585 A EP82305585 A EP 82305585A EP 0078634 B1 EP0078634 B1 EP 0078634B1
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Prior art keywords
storage means
bus
incoming
buses
data
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French (fr)
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EP0078634A1 (de
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Ernst August Munter
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Nortel Networks Ltd
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Northern Telecom Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/08—Intermediate station arrangements, e.g. for branching, for tapping-off
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/08—Time only switching

Definitions

  • the present invention relates generally to telecommunication switching systems or the like and more particularly to a switching network for use with PCM (pulse code modulation) signals in a TDM (time division multiplex) environment.
  • PCM pulse code modulation
  • a switching system is provided in conventional telephone systems for interconnecting transmission paths between subscribers.
  • the switching systems are commonly based upon either a space-time-space configuration or upon a time-space-time configuration.
  • U.S. patent 4,123,624 dated October 31, 1978 by R. Gagnier et al and U.S. patent 3,851,105 dated November 26, 1974 to A. Regnier et al depict examples of time-space-time switching systems.
  • time-space-time switching In a time-space-time switching system, switching is accomplished by first switching a given channel in time, then switching it in space, and finally, once again switching it in time; hence the name time-space-time representing a time- switch, a space-switch, and a time-switch.
  • a time-space-time switch functions to switch a channel from one assigned timeslot in an incoming bus to one assigned timeslot in an outgoing bus. This concept is well known in the art of switching.
  • a space-time-space switch is similar in operation to the time-space-time switch except of course for the fact that it has two stages of space switching and only one stage of time switching.
  • Network blocking refers to the inability of a switching system to provide a connection between two idle endpoints. In other words, two subscribers cannot be connected together by the switching system because all available paths through the network (of the switching system) are in use.
  • Present multistage switching networks e.g. time-space-time switches
  • a single stage timeswitch is inherently non-blocking, but the number of channels that can be served a single timeswitch is limited by the speed of the memory devices employed.
  • One object of the present invention is to provide a method and a circuit by which a relatively large (e.g. 2048 channels) non-blocking switching network may be constructed.
  • a switching network is considered to be comprised of a switching module (which performs the actual switching chores) and a control module to control the operation of the switching module.
  • incoming channels on two incoming buses are switched to outgoing channels on two outgoing buses (each having 512 channels).
  • Two storage devices each having a capacity of 1024 words of ten bits each, are employed.
  • the data from a first incoming bus is applied to a first storage device and the data from a second incoming bus is applied to a second storage device.
  • a first outgoing bus is receiving data from the first storage device and a second outgoing bus is receiving data from the second storage device.
  • the buses are switched so that the data from the first incoming bus is applied to the second storage device and the data from the second incoming bus is applied to the first storage device.
  • the first outgoing bus is receiving data from the second storage device and the second outgoing bus is receiving data from the first storage device.
  • the buses are switched back to their original connections (i.e. as for the first frame).
  • the buses are switched to the connections described for the second frame, and etc., for subsequent frames.
  • the switching network of the present invention has certain characteristics of both a time-switch and of a space-switch. Since it switches the channels in time it clearly has the elements of a time-switch. Because of this time-switching function of the present invention, it can find application, for example, as the time switches 0 to 7 depicted in Figure 2 of the aforementioned U.S. patent 4,123,624. Additionally, since the switching network also switches in space, it can be considered as performing the function of a time-space-time switch or alternately of a space-time-space switch. Because of this broad nature of the switching network of the present invention, it will be referred to solely as a switching network.
  • the present invention relates to a switching network for use in a TDM (time division multiplex) system for switching digital signals carried in timeslots on N incoming buses to timeslots on M outgoing buses, wherein N and M are positive integers, Na2, and M 2: 2, the network being characterised by: a plurality of storage means, the plurality of storage means being divided into N first groupings of N/n storage means each, each first grouping sequentially and cyclically being responsive to n incoming buses, one incoming bus at a time, wherein n is a positive integer, n is a factor of N, and 2sn n 5 N; and each group of n outgoing buses selectively responsive to one of M/n second groupings of the storage means, each second grouping comprising N storage means comprising no more than one storage means from each of the first groupings.
  • TDM time division multiplex
  • Modifications or variation of the switching network referred to in the preceding paragraph can include a) the switching network wherein n equals three; b) the switching network wherein N equals M; c) the switching network wherein N equals three, six or nine.
  • the present invention further provides a switching network for use in a TDM (time division multiplex) system for switching digital signals carried in timeslots on four incoming buses to timeslots on four outgoing buses, said network characterised by:
  • the present invention also provides a method for use in a TDM (time division multiplex) system for switching digital signals carried in timeslots on N incoming buses to timeslots on M outgoing buses, wherein N and M are positive integers, N ? 2, and M > 2, the method being characterised by: sequentially and cyclically storing the data from each incoming bus, of each group of n incoming buses, in n first storage groups, each of N/n storage means, wherein n is a positive integer, 2 5 n 5 N, and n is a factor of N; sequentially and cyclically connecting each outgoing bus, of each group of n outgoing buses, to n second storage groups, each of N/n storage means, wherein each second storage group results from a re-organization of the first storage groups and comprises no more than one storage means from each of the first storage groups, wherein each second storage group comprises storage means responsive to different groups of n incoming buses, and wherein each outgoing bus has access to at least one storage means from each of the first groups.
  • FIG 1 is a simplified symbolic representation of a known time-space-time switching network 51 (also referred to as a three stage switching network).
  • Network 51 comprises a time switch 52, a space switch 53, and a time switch 54, interconnected as depicted in Figure 1.
  • a single bus 56 having 256 channels is depicted entering time switch 52. Assume that the channel under consideration on bus 56 is assigned to time slot 1 as depicted by the shaded area in time switch 52.
  • Time switch 52 serves to switch channels between time slots, and in the example illustrated in Figure 1, has switched the channel of interest from incoming time slot 1 to internal time slot 15 of space switch 53.
  • incoming time slot 1 arrives, the information contained therein is stored until the internal time slot 15 arrives; thus we have time switching.
  • internal timeslot 15 arrives it carries the information through an assigned crosspoint in space switch 53.
  • This assigned crosspoint interconnects an incoming TDM bus 56 with an outgoing TDM bus 57 (note that in this simplified example there is depicted only one incoming TDM bus, i.e. 56, and there is depicted only one outgoing TDM bus, i.e. 57).
  • the crosspoint (in switch 53) is assigned only for the duration of the sample (i.e. for one timeslot), and for the other 255 timeslots of the frame, switch 53 can be assigned other crosspoints.
  • the information is output from space switch 53 in timeslot 15, the same timeslot on which it was entered.
  • the information is then applied (still of timeslot 15) to space switch 54 where it is stored until timeslot 2 arrives to carry the signal further.
  • This sequence of time-space-time switching is repeated once each frame for our signal on incoming timeslot 1 (note: one frame contains 256 timeslots in this example).
  • FIG. 2 is a simplified block diagram of a typical known time switch 60.
  • the incoming channels (512 in number) are applied to data memory 61 via TDM bus 62.
  • bus 62 carries each PCM sample (from the 512 channels) in parallel, in a sequential fashion, at the rate of one PCM sample approximately every 200 nanoseconds (note: the actual duration needed for writing is 100 nanoseconds).
  • data memory 61 comprises three RAMs (random access memory) such as Intel's model no. 2148, capable of storing 512 binary words, each word having up to ten bits.
  • the outgoing channels are read from data memory 61 and are applied to outgoing TDM bus 63, in parallel, at the rate of one PCM sample approximately every 200 nanoseconds.
  • incoming channel counter 64 basically keeps track of which channels are being received at any given instant and produces an address appropriate for each channel, such that when a given channel is received by data memory 61 it is stored in memory 61 at the address given by counter 64.
  • data memory 61 has 512 memory locations, one for each channel.
  • the incoming PCM data on TDM bus 62 are written sequentially into storage locations in data memory 61 under control of incoming channel counter 64.
  • a specific PCM sample is stored in data memory 61 at an address corresponding to the incoming channel number is designated by counter 64.
  • counter 64 is simply a sequential counter, counting in increasing order from 0 to 511 in step with the incoming channels, and then repeating its count over and over again.
  • Connection memory 66 (e.g. Intel RAMs, model no. 2148) contains a set of incoming channel addresses. The function of memory 66 is to send a read address (via bus 68) to data memory 61, at the appropriate time (determined by outgoing channel counter 67) to cause a PCM sample stored in data memory 61 to be read out on bus 63. Connection memory 66 achieves this as follows.
  • Process controller 71 produces the address for channel 501 on address bus 72 and simultaneously provides on data bus 73 the address for channel 400, to be stored as data in memory 66 at the location specified by address bus 72. Subsequently, when the read address corresponding to channel 501 is applied to connection memory 66, from outgoing channel counter 67, via read address bus 74, the data output on data output 76 (applied to the read address bus 68 of data memory 61) is in fact the address for data memory 61 corresponding to the location wherein channel 400 from input bus 62 has been stored.
  • connection memory 66 addresses connection memory 66 with the address for channel 501
  • connection memory 66 produces the address of channel 400 on data output 76 and in turn applies it to the read address input for data memory 61 and the PCM word from channel 400, stored in memory 61 is applied to TDM bus 63 during channel 501.
  • any incoming PCM sample can be selected by appropriately loading connection memory 66 from processor 71.
  • FIG. 3 depicts one preferred embodiment of the present invention; i.e. switching network 80 comprised of switching module 90 and control module 89. The components thereof are interconnected as depicted in Figure 3 and attention is directed thereto.
  • coming bus 91 carries 512 channels sequentially, in parallel, and applies them to either data memory 81 or data memory 82, depending upon the status of switches 83 and 84.
  • incoming bus 92 carries 512 channels sequentially, in parallel, and applies them to either data memory 81 or data memory 82, depending upon the status of switches 83 and 84.
  • the channels on bus 91 will be referred to as “Group-A” channels and those on bus 92 will be referred to as “Group-B” channels.
  • the channels on bus 93 will be referred to as “Group-W” channels and those on bus 94 as “Group-X" channels.
  • Switches 83 and 84 are depicted as simple mechanical single pole double throw (SPDT) switches in order not to unnecessarily complicate the description. In actual practice, switches 83 and 84 are preferably static solid-state switches (e.g. model no. 74S257). Note that data memory 81 (e.g. three Intel model no. 2148) can store 1024 binary words of ten bits each; memory 82 has the same capacity as memory 81.
  • SPDT single pole double throw
  • switches 85 and 86 function to connect the outputs of data memories 81 and 82 to outgoing buses 93 and 94.
  • Switches 85 and 86 are also preferably static solid-state switches (e.g. model no. 74S257).
  • the object of switching network 80 is to be able to switch any one of the 512 channels appearing either on bus 91 or 92 to any one of the 512 channels appearing either on bus 93 or 94. The principle behind how switching network 80 accomplishes this is as follows.
  • each switch 83, 84, 85, 86, 87, and 88 has both a first position (indicated by a solid arrow) and a second position (indicated by a dashed line).
  • Buses 91 and 92 have their respective frames in phase; i.e. when a new frame starts on bus 91 a new frame is also starting on bus 92.
  • buses 93 and 94 have their respective frames in phase with one another and also in phase with the frames appearing on buses 91 and 92.
  • in-phase operation of the switches is used in the preferred embodiment of the invention if necessary, or advantageous, it is of course possible to delay the outgoing bus frames with respect to the incoming buses. This could be accomplished by using separate counters (i.e. counter 96 would be replaced by two counters; one counter for memories 81 and 82 and one counter for connection memories 98 and 99) or by inserting a fixed delay on address bus 109.
  • a single counter 96 is used.
  • All the switches 83, 84, 85, 86, 87 and 88 are operated substantially in unison so that for a first frame the switches are all in their first position (indicated by the solid arrow) and for the next frame they are all in their second position (indicated by the dashed line) and for the next frame they are all in their first position, etc.
  • every alternate frame hereinafter referred to as even frames for convenience
  • every inbetween frame hereinafter referred to as odd frames, for convenience
  • the control of switches 83 to 88 inclusive is accomplished by the one-bit from odd-even frame indicator 97 on lead 105.
  • PCM data received on bus 91 during an even frame is stored in data memory 81 (indicated in Figure 3 as A even).
  • PCM data received on bus 92 during an even frame is stored in data memory 82 (indicated in Figure 3 as B even).
  • data from bus 91 is stored in data memory 82 (indicated as A odd) and data from bus 92 is stored in data memory 81 (indicated as B odd).
  • PCM data on outgoing bus 93 is read from data memory 81. Recall that data memory 81 contains data originating from bus 91 in even frames and from bus 92 in odd frames (i.e. A even and B odd). Also during even frames, PCM data on outgoing bus 94 is read from data memory 82 containing data originating from bus 92 in even frames and from bus 91 in odd frames (i.e. A odd and B even).
  • switches 83, 84, 85, 86, 87 and 88 are in their second (dashed) position.
  • PCM data on outgoing bus 93 is read from data memory 82 (i.e. A odd and B even).
  • PCM data on outgoing bus 94 is read from data memory 81 containing data originating from bus 91 in even frames and from bus 92 in odd frames (i.e. A even and B odd).
  • bus 93 has access to any of the input channels on buses 91 and 92.
  • bus 94 has access to any of the input channels on buses 91 and 92.
  • a channel on bus 91 is to be connected to a channel on bus 93.
  • an even frame bus 93 is connected to data memory 81 via switch 85 to access data that was received from bus 91 during even frames (i.e. A even and thus the channel in question).
  • an odd frame bus 93 is connected to data memory 82, via switch 85, to access data that was received from bus 91 during odd frames (i.e. A odd and thus the channel in question).
  • bus 93 is connected to data memory 81, via switch 85, to access data that was received from bus 92 during the previous odd frame (i.e. B odd and thus the channel in question).
  • bus 93 is connected to data memory 82, via switch 85, to access data that was received from bus 92 during the previous even frame (i.e. B even and thus the channel in question). Consequently, bus 93 has access to any one of the 512 channels received on bus 91 and to any one of the 512 channels received on bus 92.
  • bus 94 has access to any one of the 512 channels received on bus 91 and to any one of the 512 channels received on bus 92.
  • control module 89 of switching network 80 will now be described. It should be noted that the control module 89 of switching network 80 is not unlike the control portion of time switch 60 depicted in Figure 2. Control module 89 of network 80, however, does have the addition of an odd-even frame indicator 97, exclusive-OR gates 102 and 103, switches 87 and 88, and two connection memories 98 and 99 in lieu of only one. Additionally, only a single channel counter 96 is used, to provide both write addresses to data memories 81 and 82, and read addresses to connection memories 98 and 99 (note: in Figure 2, channel counters 64 and 67 could be replaced by a single counter for certain applications). Process controller 101 completes the major components of control module 89.
  • channel counter 96 along with the output of odd-even frame indicator 97 (a one bit counter) provide a ten-bit write address, on address bus 106, for data memories 81 and 82.
  • Counter 96 and indicator 97 are constructed from Texas Instruments model no. 74S163 counters. Each one of memories 81 and 82 is written sequentially as the data appears on its respective data input DI.
  • the address at which the data is stored is of course defined by the binary address from both counter 96 and indicator 97 applied, via address bus 106, to the respective write address input WA.
  • a specific PCM sample, from a given channel is stored in either data memory 81 or 82 at an address corresponding to the incoming channel number (note that the most significant bit of the write address for memories 81 and 82 is the bit from indicator 97).
  • connection memory 98 produces on its data output terminals 111 a ten-bit address indicative of which channel on either bus 91 or 92 (as stored in data memories 81 and 82) is to be connected to the current channel on bus 93.
  • the address on bus 107 (during an even frame) addresses a storage location in memory 81 containing data from a specific channel from either bus 91 or 92 which data is then read and applied to data output DO of memory 81 (during an even frame).
  • connection memory 99 produces, on its data output terminals 112, a ten-bit address indicative of which channel on either bus 91 or 92 (as stored in data memory 82) is to be connected to the current channel on bus 94.
  • the address on bus 108 (during an even frame) addresses a storage location in memory 82 containing data from a specific channel originating from either bus 91 or 92, which data is then read and applied to data output DO of memory 82.
  • the write addresses for both data memories 81 and 82 have as their most significant bit the output of odd-even frame indicator 97. Consequently, during even frames, the channels from bus 91 are stored in the one-half of data memory 81 with addresses beginning with logic 0 (i.e. the "lower” half). Likewise, during even frames, the channels from bus 92 are stored in the one-half of data memory 82 with addresses beginning with logic 0 (i.e. the "lower” half).
  • the output of indicator 97 is a logic 1, and consequently the addresses of all the channels received during odd frames begin with a logic 1.
  • the channels from bus 91, during odd frames, are stored in the one-half of data memory 82 with addresses beginning with logic 1 (i.e. the "upper” half).
  • the channels from bus 92 are stored in the one-half of data memory 81 with addresses beginning with logic 1 (i.e. the "upper” half).
  • Exclusive-OR gates 102 and 103 are employed as controlled inverters. During even frames, the output of odd-even frame indicator 97 is a logic 0. Consequently, exclusive-OR gate 102 allows the logic bit applied to its other input (i.e. the most significant bit, MSB, from terminal 111) to be passed unchanged.
  • MSB most significant bit
  • connection memory 98 address only one-half of the locations in data memory 81 (i.e. there are 1024 locations in memory 81 but only 512 addresses stored in memory 98). More specifically, the data in connection memory 98 specify and select the sources (from any of the 1024 input channels on buses 91 and 92) for the 512 output channels appearing on bus 93.
  • the most significant bit from data output terminal 111 is inverted by exclusive-OR gate 102 and consequently the address applied to read address terminal RA on data memory 82 (via switch 87) is not the binary data as it appears on terminal 111. Rather, the most significant bit is inverted; if the data in memory 98 addressed the "lower” half of data memory 81 during an even frame it will now address the "upper” half of data memory 82 during an odd frame. Similarly, if the data in memory 98 addressed the "upper" half of data memory 81 during an even frame it will now address the "lower” half of data memory 82 during an odd frame.
  • Process controller 101 functions in an analogous manner to process controller 71 of Figure 2.
  • Write address bus 113 from processor 101, defines a location in connection memory 98 (or memory 99) corresponding to a channel on bus 93 (or bus 94).
  • Processor 101 via data bus 114, stores in memory 98 (or memory 99), as data, the addresses of the channels (i.e. from buses 91 and 92) to be connected to bus 93 (or bus 94). These addresses are of course the addresses of locations in data memories 81 and 82 into which the data, carried by channels in buses 91 and 92, have been stored.
  • outgoing bus 93 can convey data from up to 512 channels originating from the 1024 channels on both bus 91 and 92.
  • outgoing bus 94 can convey data from up to 512 channels originating from the 1024 channels on both bus 91 and 92.
  • Figure 4 depicts another embodiment of the present invention (i.e. switching network 115 corprised of switching module 125 and control module 120) arranged to interconnect four incoming buses 116, 117, 118, and 119 (of 512 channels each) with four outgoing buses 121, 122, 123, and 124 (of 512 channels each).
  • switching network 115 corprised of switching module 125 and control module 120 arranged to interconnect four incoming buses 116, 117, 118, and 119 (of 512 channels each) with four outgoing buses 121, 122, 123, and 124 (of 512 channels each).
  • Switch 126 applies the data from incoming bus 116 to both data memories 136 and 137 during even frames (indicated by the solid arrow in switch 126). During odd frames switch 126 applies the data from incoming bus 117 to both data memories 136 and 137 (indicated by the dashed connection in switch 126). Switch 127 applies the data from incoming bus 117 to both data memories 138 and 139 during even frames. During odd frames switch 127 applies data from incoming bus 116 to both data memories 138 and 139. Note that data memories 136, 137, 138, 139, 140, 141, 142, and 143 are constructed from Intel model 2148 CAM modules.
  • switch 128 applies the data from incoming bus 118 to both data memories 140 and 141 during even frames.
  • Switch 129 applies the data from incoming bus 119 to both data memories 142 and 143 during even frames.
  • switch 129 applies the data from incoming bus 118 to both data memories 142 and 143 while switch 128 applies the data from incoming bus 119 to both memories 140 and 141.
  • Switch 130 connects outgoing bus 121 to both memories 136 and 140 during even frames and to both memories 138 and 142 during odd frames.
  • Switch 131 connects outgoing bus 122 to both memories 138 and 142 during even frames and to both memories 136 and 140 during odd frames.
  • Switch 132 connects outgoing bus 123 to both memories 137 and 141 during even frames and to both memories 139 and 143 during odd frames.
  • Switch 133 connects outgoing bus 124 to both memories 139 and 143 during even frames and to both memories 137 and 141 during odd frames.
  • any one of the 2,048 input channels of buses 116, 117, 118, or 119 of switching network 115 can be switched to any one of the 2,048 output channels of buses 121, 122, 123, or 124.
  • each switched connection takes an independent, time multiplexed path through switching network 115, thus ensuring non-blocking.
  • the control module 120 of switching network 115 is similar to that of the Figure 3 control module 89 except that it is now expanded to have capacity to control the additonal memories.
  • Channel counter 144 is the same as counter 96 ( Figure 3) and odd-even frame indicator 145 is the same as indicator 97 ( Figure 3).
  • connection memories 146, 147, 148 and 149 are now four connection memories 146, 147, 148 and 149, one for each of the outgoing buses 121, 122, 123, and 124, respectively.
  • Each connection memory 146,147,148 and 149 has the capacity to store 512 binary words, each word having eleven bits.
  • each memory 146, 147, 148, and 149 is applied to one of gating circuits 151, 152, 153, or 154, as controlled by switches 156, 157, 158, and 159, as depicted in Figure 4.
  • connection memory 146 is connected to gating circuit 151 via switch 156.
  • the nine least significant bits of the eleven bit binary word received from the data output DO of connection memory 146 are passed unchanged by gating circuit 151.
  • the second most significant bit is applied to exclusive-OR gate 151a in an analogous manner as was the most significant bit in the Figure 3 embodiment.
  • the most significant bit is applied to decoder 151b (consisting of a single inverter).
  • One output of decoder 151b is applied to the enable input EN1 of data memory 136 to selectively enable it for a read operation, and the other output of decoder 151b is applied to the enable input EN5 of data memory 140 to selectively enable it for a read operation.
  • decoder 151b functions to enable either data memory 136 or data memory 140 at one time (but not both simultaneously) for a read operation, the address of which is provided by the one bit from exclusive-OR gate 151a together with the nine bits obtained directly from connection memory 146 (during an even frame).
  • gating circuit 152 provides enable signals (for inputs EN3 and EN7) and a ten bit read address to both data memories 138 and 142.
  • Gating circuit 153 provides enable signals (for inputs EN2 and EN6) and a ten bit read address to both data memories 137 and 141.
  • Gating circuit 154 provides enable signals (for inputs EN4 and EN8) and a ten bit read address to both data memories 139 and 143. Note that the write addresses for all the data memories 136 to 143 inclusive are provided by the ten bits provided by channel counter 144 and odd-even frame indicator 145.
  • the process controller (not shown) for connection memories 146, 147, 148, and 149 is not depicted in the interest of not unduly complicating the description. It would work in an analogous manner to process controller 101 of Figure 3.
  • FIG. 5 is a simplified block diagram of a further embodiment of the present invention (i.e. switching network 160, of which only the switching module 185 is depicted), depicting the application of the present invention to six incoming buses 161 to 166 inclusive (512 channels each) and six outgoing buses 167 to 172 inclusive (512 channels each).
  • Eighteen data memories, 186 to 203 inclusive are employed.
  • Data memories 186, 187, and 188 are responsive to data on incoming bus 161 during even frames and to data on incoming bus 162 during odd frames.
  • Data memories 189, 190 and 191 are responsive to data on incoming bus 162 during even frames and to data on incoming bus 161 during odd frames.
  • Data memories 192, 193, and 194 are responsive to data on incoming bus 163 during even frames and to data on incoming bus 164 during odd frames.
  • Data memories 195,196, and 197 are responsive to data on incoming bus 164 during even frames and to data on incoming bus 163 during odd frames.
  • Data memories 198, 199, and 200 are responsive to data on incoming bus 165 during even frames and to data on incoming bus 166 during odd frames.
  • Data memories 201, 202, and 203 are responsive to data on incoming bus 166 during even frames and to data on incoming bus 165 during odd frames.
  • the control philsophy is the same as in Figures 3 and 4 and has not been shown in Figure 5 in order to not unduly complicate the Figure.
  • Switches 173 to 184 inclusive are identical to switches 126 to 133 inclusive of Figure 4 and function in an analogous manner.

Claims (19)

1. Ein Schaltnetzwerk (115) zum Gebrauch bei einem TDM-(TIME DIVISION MULTIPLEX = Zeit- multiplex-)System zum Schalten von in Zeitfenstern an N ankommenden Busen (116, 117, 118, 119) enthaltenen Signalen an Zeitfenster an M abgehenden Busen (121, 122, 123, 124), wobei N und M positive ganze Zahlen sind, N 2: 2 und M ≥ 2, wobei das Netzwerk gekennzeichnet ist durch: eine Vielzahl von Speichermitteln (136 bis 143), wobei die Vielzahl von Speichermitteln unterteilt ist in N erste Gruppierungen (136, 137; 138, 139; 140, 141; 142, 143) von jeweils N/n Speichermitteln, jede erste Gruppierung sequentiell und zyklisch auf n ankommende Buse (116, 117; 118,119) reagiert, jeweils einen ankommenden Bus zu einem Zeitpunkt, wobei n eine positive ganze Zahl, n ein Teiler von N und 2 ≤ n ≤ N ist, und jede Gruppe (121, 122; 123, 124) von n abgehenden Busen, selektiv reagierend auf eine von M/n zweiten Gruppierungen (136, 138, 140, 142; 137, 139, 141, 143) der Speichermittel, wobei jede zweite Gruppierung N Speichermittel umfaßt und nicht mehr als ein Speichermittel von jeder der ersten Gruppierungen enthält.
2. Das Schaltnetzwerk nach Anspruch 1, bei dem n gleich zwei ist.
3. Das Schaltnetzwerk nach Anspruch 1, bei dem n gleich drei ist.
4. Das Schaltnetzwerk nach Anspruch 2, bei dem N = M.
5. Das Schaltnetzwerk nach Anspruch 3, wobei N = M.
6. Das schaltnetzwerk nach Anspruch 4, bei dem N gleich zwei, vier oder sechs ist.
7. Das Schaltnetzwerk nach Anspruch 5, bei dem N gleich drei, sechs oder neun ist.
8. Ein Schaltnetzwerk (115) zum Gebrauch in einem TDM-(Zeitmultiplex-)System zum Schalten von in Zeitfenstern an vier ankommenden Busen (116,117,118,119) enthaltenen Digitalsignalen an Zeitfenster an vier abgehenden Busen (121, 122, 123, 124), wobei das Netzwerk charakterisiert ist durch: erste, zweite, dritte, vierte, fünfte, sechste, siebte und achte Speichermittel (136 bis 143), wobei a) die ersten und zweiten Speichermittel (136, 137) selektiv auf Signale ansprechen, die an den ersten und zweiten ankommenden Busen (116, 117) erscheinen, b) die dritten und vierten Speichermittel (138, 139) selektiv auf Signale ansprechen, die an den ersten und zweiten ankommenden Busen (116, 117) erscheinen, c) die fünften und sechsten Speichermittel (140, 141) selektiv auf Signale ansprechen, die an den dritten und vierten ankommenden Busen (118, 119) erscheinen, und d) die siebten und achten Speichermittel (142, 143) selektiv auf Signale ansprechen, die an den dritten und vierten ankommenden Busen (118, 119) erscheinen;
der erste abgehende Bus (121) wahlweise auf Signale anspricht, die entweder in dem ersten und fünften Speichermittel (136 140) oder dem dritten und siebten Speichermittel (138, 142), gespeichert sind;
der zweite abgehende Bus (122) selektiv auf Signale reagiert, die entweder in dem dritten end siebten Speichermittel (138, 142) oder dem ersten und fünften Speichermittel (136, 140) gespeichert sind;
der dritte abgehende Bus (123) selektiv auf Signale reagiert, die entweder in dem zweiten und sechsten Speichermittel (137, 141 ) oder dem vierten und achten Speichermittel (139, 143) gespeichert sind; und
der vierte abgehende Bus (124) selektiv auf Signale anspricht, die entweder in dem vierten und achten Speichermittel (139, 143) oder dem zweiten und sechsten Speichermittel (137, 141) gespeichert sind.
9. Das Schaltnetzwerk nach Anspruch 8, bei dem jedes der Speichermittel die Kapazität zum Speichern mindestens zweier vollständiger Datenrahmen besitzt.
10. Schaltnetzwerk nach Anspruch 8 oder 9, bei dem ein Speichermittel nur auf einen ankommenden Bus pro Rahmen anspricht und bei dem ein abgehender Bus nur auf ein Paar von Speichermitteln pro Rahmen anspricht.
11. Das Schaltnetzwerk nach Anspruch 8, bei dem die ersten und zweiten Speichermittel (136, 137) auf Signale alternativ von den ersten und zweiten ankommenden Busen (116, 117) ansprechen und die dritten und vierten Speichermittel (138, 139) auf Signale alternativ von den ersten und zweiten ankommenden Busen (116, 117) so ansprechen, daß die ersten und zweiten Speichermittel (136, 137) nicht gleichzeitig auf den gleichen ankommenden Bus ansprechen wie die dritten und vierten Speichermittel (138, 139); und bei dem die fünften und sechsten Speichermittel (140, 141) auf Signale alternativ von den dritten und vierten ankommenden Busen (118, 119) ansprechen und die siebten und achten Speichermittel (142, 143) auf Signale alternativ von den dritten und vierten ankommenden Busen (118, 119) so ansprechen, daß die fünften und sechsten Speichermittel (140, 141) nicht gleichzeitig auf den gleichen ankommenden Bus ansprechen wie die siebten und achten Speichermittel (142, 143).
12. Das Schaltnetzwerk nach Anspruch 11, bei dem das Alternieren mit der Rate einmal pro Datenrahmen an den ankommenden Busen auftritt.
13. Ein Verfahren zum Gebrauch bei einem TDM-(Zeitmultiplex-)System zum Schalten von in Zeitfenster an N ankommenden Busen (116, 117, 118, 119) enthaltenen Digtalsignalen an Zeitfenster an M abgehenden Busen (121, 122, 123, 124), wobei N und M positive ganze Zahlen sind, N ≥ 2 und M 2: 2 ist, wobei das Verfahren gekennzeichnet ist durch:
sequentielles und zyklisches Speichern der Daten von jedem ankommenden Bus jeder Gruppe (116, 117 oder 118, 119) von n ankommenden Busen in n ersten Speichergruppen von jeweils N/ n Speichermitteln, wobei n eine positive ganze Zahl, 2 ≤ n ≤ N und n ein Teiler von N ist,
sequentielles und zyklisches Verbinden jedes abgehenden Bus aus jeder Gruppe (121, 122 oder 123, 124) von n abgehenden Busen mit n zweiten Speichergruppen von jeweils N/n Speichermitteln, wobei jede der zweiten Speichergruppen sich aus einer Umorganisation der ersten Speichergruppen ergibt und nicht mehr als ein Speichermittel von jeder der ersten Speichergruppen enthält, wobei jede der zweiten Speichergruppen ein auf verschiedene Gruppen von n ankommenden Busen reagierendes Speichermittel enthält und wobei jeder abgehende Bus Zugriff zu mindestens einem Speichermittel aus jeder der ersten Gruppen besitzt.
14. Das Verfahren nach Anspruch 13, bei dem N = M.
15. Das Verfahren nach Anspruch 14, wobei N gleich vier und n gleich zwei ist.
16. Das Verfahren nach Anspruch 14, bei dem N gleich sechs und n gleich zwei ist.
17. Das Verfahren nach Anspruch 14, bei dem N gleich zwei und n gleich zwei ist.
18. Das Verfahren nach Anspruch 14, bei dem N gleich drei und n gleich drei ist.
19. Das Verfahren nach Anspruch 13, 14 oder 15, bei dem jedes der Speichermittel die Kapazität zum Speichern von mindestens n vollen Datenrahmen besitzt.
EP82305585A 1981-11-05 1982-10-20 Koppelfeld zum Gebrauch in einem Zeitmultiplex-Vermittlungssystem Expired EP0078634B1 (de)

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AT82305585T ATE15575T1 (de) 1981-11-05 1982-10-20 Koppelfeld zum gebrauch in einem zeitmultiplexvermittlungssystem.

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CA000389563A CA1173944A (en) 1981-11-05 1981-11-05 Switching network for use in a time division multiplex system
CA389563 1981-11-05

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EP0078634B1 true EP0078634B1 (de) 1985-09-11

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JP (1) JPS5885693A (de)
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DE3541662A1 (de) * 1985-11-26 1987-05-27 Philips Patentverwaltung Vermittlungsanlage
GB9105922D0 (en) * 1991-03-20 1991-05-08 Plessey Telecomm Time switch speech store module

Citations (1)

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Publication number Priority date Publication date Assignee Title
US3851105A (en) * 1971-10-12 1974-11-26 Int Standard Electric Corp Time division switching network employing space division stages

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Publication number Priority date Publication date Assignee Title
DE2602561C3 (de) * 1976-01-23 1978-11-02 Siemens Ag, 1000 Berlin Und 8000 Muenchen Zeitmultiplexkoppelfeld
DE2602570C3 (de) * 1976-01-23 1980-04-24 Siemens Ag, 1000 Berlin Und 8000 Muenchen Zeitmultiplexkoppelfeld
CA1065977A (en) * 1977-05-09 1979-11-06 Real Gagnier Switching network for a pcm tdm system
WO1980000211A1 (en) * 1978-06-30 1980-02-07 Waddleton N Multiplex time division switching network unit of the"time-time"type
FR2462835A1 (fr) * 1979-07-27 1981-02-13 Thomson Csf Materiel Telephoni Reseau de connexion pour autocommutateur a transmission en multiplexage dans le temps
IT1128291B (it) * 1980-05-13 1986-05-28 Cselt Centro Studi Lab Telecom Matrice elementare di commutazione pcm
EP0062295B1 (de) * 1981-04-03 1985-07-10 COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL S.A. dite: Digitales Koppelfeld

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Publication number Priority date Publication date Assignee Title
US3851105A (en) * 1971-10-12 1974-11-26 Int Standard Electric Corp Time division switching network employing space division stages

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KR880002195B1 (en) 1988-10-17
ATE15575T1 (de) 1985-09-15
EP0078634A1 (de) 1983-05-11
CA1173944A (en) 1984-09-04
KR840002784A (ko) 1984-07-16
DE3266218D1 (en) 1985-10-17
JPH0336359B2 (de) 1991-05-31
JPS5885693A (ja) 1983-05-23

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