Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
  • H01P1/00—Auxiliary devices
  • H01P1/30—Auxiliary devices for compensation of, or protection against, temperature or moisture effects ; for improving power handling capability
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
  • H01P9/00—Delay lines of the waveguide type
  • H01P9/006—Meander lines

Definitions

• the temperature stable delay line according to this invention has important application for satellite communications, and particularly for on-board satel lite regenerative repeaters employing differentially coherent quaternary phase shift keying (DQPSK) detection directly at the up-link carrier frequency.
• DQPSK differentially coherent quaternary phase shift keying
• Such a demodulator detecting a 120 x 10 6 bit per second signal requires a 16.7 nanosecond delay element, and the delayed reference phase must be maintained within 3° over the variable operating environmental conditions. Therefore, the delay stability at higher microwave frequencies of approximately 14 GHz an extremely stable delay circuit is required.
• This large temperature coefficient is due to the thermal linear expansion coefficient ( ⁇ l ) and the dielectric temperature coefficient ( ⁇ ⁇ ) of the fused silica substrate.
• the values of the coefficients for this substrate are .5 x 10 -6 parts per degree C. and 10 x 10 -6 parts degree C, respectively.
• a temperature compensated design scheme was subsequently devised for the above described MIC filter design.
• the temperature compensated MIC filter delay circuit disclosed by this reference can only be used for a fixed band center frequency, narrow band width application.
• the temperature compensated design technique disclosed by the reference is the result of a rather complicated heuristic approach.
• the temperature compensated MIC delay line of the present invention is of simple design, and has broad band application and nearly perfect temperature compensation.
• the circuit consists only of a plurality of cascaded microstrip transmission lines, and is compact, lightweight and highly reliable because no active components are involved.
• the design technique for producing such delay lines is simple, being based only on the physical properties of the substrate materials.
• the delay line of the present invention is composed of cascade connected substrates, for example, a high dielectric barium tetratitanate ceramic microstrip connected to a short sapphire single crystal A1 2 O 3 microstrip section which is in turn connected to a further dielectric substrate of barium tetratitanate.
• Another object of this invention is to provide a delay line circuit which consists only of cascaded passive microstrip transmissiou lines.
• a still further object of this invention is to provide a temperature compensated MIC delay circuit which will conform to conventional forms of manufacture, be of simple construction and easy to use so as to provide a device which will be economically feasible, long lasting, and trouble free in operation.
• Figure 1 is a schematic representation of the temperature compensated delay line of the present invention, illustrating two cascade coonected MIC substrates;
• Figure 2 is a perspective view of one embodiment of the invention haviug three cascaded substrates integrated into a 16 nanosecond microstrip delay line assembly;
• Figure 3 is a graphical representation of the measured group delay versus the frequency response of the substrate illustrated in Figure 2;
• Figure 4 is a further graphical representation of the measured temperature stability characteristic of the delay line illustrated in Figure 2.
• the numeral 10 generally designates the temperature stable microwave integrated circuit delay line of the present invention.
• the device includes two separate dielectric substrates 12 and 14 which are made, for example, of barium tetratitanate and sapphire, respectively.
• the substrates are cascade connected within a substrate carrier 16, which is provided at its ends with input and output leads or connectors 18 and 20.
• a primary feature of the invention is that the temperature compensated MIC is designed by taking into account the thermal properties of the MIC substrate materials.
• the transmission phase temperature coefficient of an MIC line is primarily determined by two factors: the linear thermal expansion coefficient, and the dielectric temperature coefficient of the substrate.
• the dielectric temperature coefficient is negative and has a value of -26.6 x 10 -6 parts per degree C.
• the linear expansion coefficient is positive and is equal to 9.4 x 10 -6 parts per degree C.
• the resulting transmission phase temperature coefficient is 3.9 x 10 -6 parts per degree C. at 14 GHz.
• the dielectric temperature coefficient is 141 x 10 -6 parts per degree C.
• the linear thermal expansion coefficient is 6.7 x 10 -6 parts per degree C.
• the transmission phase temperature coefficient in the sapphire microstrip measures -80.1 x 10 -6 parts per degree C. at 14 GHz.
• phase change in the barium tetratitanate microstrip can be almost completely offset by that in a short sapphire microstrip section when the two are cascade connected, and when line lengths are chosen by the following design equations and criteria.
• the transmission phase temperature coefficient ( ⁇ ⁇ ) of an MIC line may be determined by the linear thermal expansion coefficient ( ⁇ l ) and the dielectric temperature coefficient ( ⁇ ⁇ ) as follows:
• ⁇ ⁇ -( ⁇ l + 1 ⁇ 2 ⁇ ⁇ ) + ... (1)
• T A equal transmission delay in MIC substrate A
• T B equal transmission delay in MIC substrate
• Subscripts A and B on the various coefficients indicate the corresponding values for substrates A and B, respectively.
• microstrip line length on each substrate is denoted by l i . and is determined from the required group delay as shown in the following equation:
• l i microstrip line length on the i sub-strate
• T i transmission group delay on the i th substrate
• V gi the group velocity on the i substrate microstrip, this value being computed from the effective dielectric constant including the frequency dependent microstrip dispersion teem and the additional correction term ⁇ (f).
• This correction term can either be theoretically computed or experimentally derived. For example, from measurements on 26 ohm BaTi 4 O 9 microstrips, ⁇ (f) was determined to be 0.077 at 14.25 GHz. Thus, the group delay is 7.7% higher than the corresponding phase delay at 14.25 GHz, which is in agreement with the theoretically predicted value.
• the assembly of a temperature compensated delay line of 16 nanoseconds consists of a 15.93 nanosecond BaTi 4 O 9 microstrip and a 0.77 nanosecond sapphire microstrip.
• the line impedance of the BaTi 4 O 9 substrate is 26 ohms at the strip width to substrate thickness ratio of 1:1 because the conductor loss in the higher impedanceline is excessive on the 0.015 inch thick substrate.
• the barium tetratitanate microstrip was photoetched on two 0.015 inch by 2.0 inch by 2.0 inch size substrates 22 and 24.
• the strip line 28 is disposed in a serpentine-like manner upon the substrate and has a total length of 34.60 inches.
• the sapphire substrate 26 Between the two barium tetratitanate substrates is provided the sapphire substrate 26.
• the microstrip on the sapphire substrate is a 3.34 inch long 50 ohm line section, and the substrate dimensions are 0.015 inch by 0.50 inch by 2.0 inches. Simple ⁇ /4-line transformer sections were used for impedance matching at the design frequency band.
• the spacing between the conductor strips on the barium tetratitanate is 13.2 times the substrate thickness in order to avoid any coupling effects among the folded, serpentine-like lines.
• the substrates are conductively bonded to a stainless steel housing or substrate carrier 30, and the ends of the microstrips are conductively connected to wave launchers 32 at either end of the carrier.
• These wave launchers are provided with a center conductor tap of 0.007 inches in width, and the outer section of the connector is provided with an outer diameter of .090 inches.
• the line interconnections may be made by thermal compression bonding of gold ribbons, and additional electrical shielding may be provided along the substrate interfaces with thin conductor shims integrated into the upper lid (not shown) of the housing or carrier assembly. Tests have been conducted on the delay line assembly of Figure 2, and the results of these tests are seen in Figures 3 and 4.
• Figure 3 plots the measured group delay versus frequency characteristic of the delay line assembly.
• the average group delay in the 13.5 to 15.25 GHz frequency band has been plotted, the plot being indicated in dashed line.
• the average group delay in the 14.0 to 14.5 GHz band has been calculated at 16.8 ⁇ 0.1 nanoseconds.
• the figure further illustrates the nearly flat broad band frequency response of the delay line. Also plotted in this figure are the calibration lines at 5 nanosecond intervals beginning at zero.
• test data of the delay temperature characteristic is depicted for a temperature variation of approximately 130 degrees F.
• a modified "pi-point" method was used for the precision measurement of the temperature stability, which is made with the high accuracy of frequency measurements.
• the technique according to the present invention provides excellent temperature compensated delay performance in an MIC circuit. Further improved thermal stability can be obtained when further temperature coefficient terms (such as the quadratic and higher order terms) in the two substrates are taken into account in the design procedure.
• the transmission loss through the delay line assembly was 23.6 dB at 14.25 GHz.
• the loss in the circuit is primarily due to the conductor loss of the microstrip lines. This loss can be reduced with wider strip widths either by lower line impedance at a fixed substrate thickness or by increased substrate thickness at a constant impedance level.
• the respective substrates used in the delay line apparatus are not limited to the barium tetratitanate and sapphire substrates which are disclosed, as long as the physical properties of the respective substrates are such that they are of opposite sign in their transmission phase temperature coefficient.
• the design procedure remain the same, although the physical dimensions and other characteristics of the substrates may vary.
• such a delay line apparatus may be constructed of any number of substrates, and it is not intended by this disclosure to limit the number of substrates so cascaded to merely two or three. It is intended to cover in the appended claims all such variations and modifications as fall within the true spirit and scope of the invention.

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• 1981
  • 1981-04-27 EP EP19810901261 patent/EP0050657A4/de not_active Withdrawn
  • 1981-04-27 WO PCT/US1981/000543 patent/WO1981003087A1/en unknown
  • 1981-04-27 JP JP50163881A patent/JPS57500538A/ja active Pending

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