Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
  • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
  • H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
  • H02H3/093—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current with timing means
  • H02H3/0935—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current with timing means the timing being determined by numerical means
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
  • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
  • H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
  • H02H3/10—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current additionally responsive to some other abnormal electrical conditions
  • H02H3/105—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current additionally responsive to some other abnormal electrical conditions responsive to excess current and fault current to earth

Definitions

• This invention relates to overcurrent protection devices such as circuit breakers.
• thermal circuit breakers are designed so that their thermal properties cause a given relationship between the overcurrent level and the time taken for the breaker to trip.
• a relatively long time - may be several seconds - is required whereas when the current becomes greatly in excess of the rated current much faster tripping occurs - perhaps in a few milliseconds.
• the shape of the current - time curve is of considerable importance particularly when a multi-tier protection system is being designed, to ensure that the circuit breaker connected nearest the particular load trips first so that loads in which no overcurrent condition exists are not disconnected unnecessarily.
• the current-time curves of the devices in different tiers of the system have different shapes it becomes difficult for the designer to ensure that proper tripping occurs at all overcurrent levels.
• an overcurrent protection device in accordance with the invention comprises current sensing means for producing an electrical signal related to the current in a conductor, an electronic circuit connected to receive said electrical signal, and output means connected to be controlled by said electronic circuit so as to interrupt the current in said conductor when such current has exceeded a set value for a time dependent on the margin by which the current exceeds the set value, characterised in that said electronic circuit includes a read-only memory programmed with data determining the current - time characteristic.
• an overcurrent protection device in accordance with the invention comprises current sensing means for producing an electrical signal related to the current in a conductor, an electronic circuit connected to receive said electrical signal, and output means connected to be controlled by said electronic circuit so as to interrupt the current in said conductor when the current in said conductor exceeds a set value for a time dependent on the margin by which the current exceeds the set value, characterised by current - time characteristic selection means settable to determine a plurality of points on the curren time characteristic curve, said electronic circuit operating to interpolate between said points.
• the electronic circuit preferably includes a microprocessor device which carries out the interpolation function referred to above.
• the microprocessor memory may be pre-programmed with the co-ordinates of said points on a multiplicity of different characteristic curves, the selector means acting to select which of the pre-programmed curves is to be use
• the selector means may comprise an array of switches which can be separately and independently set to designate the co-ordinates of the points. In either of these cases the end-user of the device can himself select the co-ordinates.
• the selector means may comprise a permanent wired connection array which determines the co-ordinates of the points, the end user then having no control, but having an assured current-time characteristic built into his device.
• FIG. 1 is a diagram of an example of an overcurrent protection device in accordance with the invention.
• Figures 2, 3 and 4 are diagrams showing three alternative forms of a characteristic curve selector forming part of the device of Figure 1,
• Figure 5 is the flow chart of a main programme used in a microprocessor in the device of Figure 1,
• Figures 6 and 7 are flow charts of two sub-routines used in tne programme
• Figure 8 is a more detailed flow chart of a part of the programme illustrated by Figure 5 .
• Figure 9 is the flow chart of a modified version of the part of the programme illustrated by Figure 8.
• the device shown includes a set of current transformers having secondary windings 10, 11, 12 and 13 magnetically linked to the phase conductors 14, 15 and 16 the neutral conductor 17 of a three phase supply to a circuit to be protected.
• One end of the neutral winding 13 is grounded and this winding has a load resistor l8 connected across it.
• Bach of the three phase windings 10, 11, 12 has one of its ends earthed via an associated one of three load resistors 19, 20 and 21 and its other end connected to the other end of the neutral winding 13. It will be appreciated that this arrangement is such that the voltage across the resistors 19, 20, 21 will be propor tional to the current in the three phases and, provided there is no earth leakage, the voltage across the resistor 18 will be zero. Increasing earth leakage causes an increasing voltage across the resistor 18.
• the three resistors 19, 20 and 21 are connected to a circuit for producing a signal corresponding in magnitude to the amplitude of the current in that phase which is carrying the heaviest current.
• This circuit includes three comparators 22, 23 and 24 which have their non-inverting inputs connected to the "live" ends of the resistors 19, 20, 21 and their inverting inputs connected together and to the output of the circuit.
• Three diodes 25, 26, 27 have their anodes connected to the. outputs of respective ones of the comparators 22, 23 and 24.
• a resistor 29 is connected across the capacitor 28.
• a diode 30 has its anode connected to the cathodes of diodes 25, 26, 27 and its cathode connected to one side of a capacitor 31, a resistor 32 being connected across the diode 30. The other side of the capacitor 31 is grounded.
• the voltage appearing at any time is proportional to the amplitude of the maximum phase current in the conductors 14, 15, l6 the resistor 29 and capacitor 28 and the resistor 32 with capacitor 31 acting to filter out high frequency changes in the current signals.
• the diode 30 enables rapid changes in the current to be followed.
• the voltage on resistor 18 is applied to a similar circuit comprising a comparator 33 , a diode 34 , a capacitor 35 a resistor 36 , a further diode 37 a further resistor 38 and a further capacitor 39.
• the signals on capacitors 31 and 39 are applied to the non-inverting inputs of two further comparators 40 and
• a micro-processor circuit 41 providing two inputs to a micro-processor circuit 42.
• An 8-bit digital output from the circuit 42 is supplied to a digital-to-analog converter 43 which supplies an analog output which is applied to the inverting inputs of the comparators 40, 4l.
• Part of the microprocessor circuit soft ⁇ ware is designed to vary the eight-bit output referred to bring the analog output of the converter 43 as close as possible to the signals on capacitors 31 and 39 at different stages of the programme, under the control of the outputs of the comparators so as to convert these signals into digital form within the circuit 42.
• the microprocessor circuit 42 is used to compare the "current" data it receives with threshold level data stored in its memory and to output to a digital timer 44, a digital signal indicating the length of time for which the current can be allowed to persist.
• This digital signal which is used to load a counter incorporated in the timer 44 is calculated by the circuit 42 as a function of the margin by which the current exceeds the threshold as will be hereinafter explained.
• the timer 44 provides an output signal when it has counted out the time interval corresponding to the digital signal with which it is loaded and this output signal is applied to an INTERRUPT terminal IRQ of the circuit 42. When such an output signal is received by the circuit
• circuit 42 whilst an overcurrent condition still exists the circuit 42 produces a trip signal which is applied via a buffer amplifier 45 to a trip relay 45 which opens contact 47 controlling the conductors 14 , 15 and l6.
• the circuit 32 The relationship between the overcurrent margin and the time delay between this margin being detected and tripping occurring is controlled as mentioned above by the circuit 32.
• the read only memory of the circuit 32 is programmed with data defining the co-ordinates in a current-time plane of 32 points on each of sixteen different current time characteristic curves.
• the 32 points are equally spaced on the digital "current" axis, but preferab ly, as shown, the digital-to-analog converter 43, is provided with a feedback circuit to give it a non-linear conver sion characteristic, such that a digital step on the current axis represents a relatively small change in actual currrnt at low current, but a relatively large change in current at high current.
• a characteristic selector 48 which provides a four-bit input to circuit 42.
• selector 48 is shown in Figure 2 and includes four independent two-way switches 48a, 48b, 48c and 48d, each of which is connected to select a "1" or a "0" for each bit. Resistors and capacitors are associated with the switches as shown in ensure that changing over of the switches does not create spurious pulse signals at the circuit 42 input.
• FIG. 3 An alternative selector 148 is shown in Figure 3, in which a socket 148a is arranged to receive any one of sixteen different plug-in connector boards l4Sb to provide the appropriate 4-bit word.
• the board 148b may be provided as shown with a pictorial representation of the characteristic defined by the board.
• the selector may be four pole - 16-way switch connected to provide a directly coded binary output.
• selector 48, 148 or 248 provides a 4-bit code determining the address of the 32 points stored in the ROM.
• FIG. 5 the microprocessor software is illustrated by a flow sheet.
• a reset entry input to the programme occurs when the trip relay is reset and as shown this reset entry causes the IRQ vector to be set to point to the trip routine, i.e. ensures that if an output is received from timer 44 during an overcurrent (or earth fault) condition this interrupt signal initiates the TRIP subroutine shown in Figure 6.
• the IRQ facility is reset and disabled, so that any output from the timer 44 until an IRQ enable condition has been established will have no effect.
• the signal on capacitor 31 is converted into a digital signal as already mentioned and stored in a register in circuit 42.
• the signal on capacitor 39 is converted and stored in another register and in the next programme interval a comparison between these stored signals and the respective stored threshold levels is carried out. If neither comparison results in an overcurrent or earth fault condition being found to be present the loop back to the reset and disable IRQ step is initiated and this loop persists until an overcurrent or earth fault condition is found to exist.
• the trip time initially set in the timer is the maximum its counter can hold and counting was starred when the enable IRQ flag was set.
• this "adjusted" trip time calculation involves inputting the current count in the timer, dividing by the trip time last calculated (on the first cycle the initial maximum time ) and multiplying by the newly calculated trip time appropriate for the last input current signals.
• the new trip time is now stored (to be used in the above "adjusted” trip time calculation as the old trip time on the next programme cycle) and the current level data is also stored.
• the "adjusted” trip time is loaded into the timer.
• the current signals form capacitors 31 and 39 are input again and a determination is then made as to whether the current signals have changed from the stored levels by more than x % (e .g.2.5%). If no such change has occurred a loop is created to repeat the inputting of the current signals and if the currents are constant this loop persists until the timer 44 produces its output and causes the TRIP sub-routine to be entered.
• the IRQ vector is set to point to the RECOVERY routine ( Figure 7 ) so that when tne timer 44 times out this RECOVERY routine will be entered instead of the TRIP routine, Next the timer 44 is loaded with its maximum count and the current signals are then input yet again. If tne current signals are still below the threshold, a loop is established in which the current signals are repeated input and compared with the thresholds until the maximum time (8 minutes) has expired when the timer 44 output will cause the RECOVERY routine to be entered.
• the old time is loaded with the maximum delay and calculation is carried out and the result (8 minutes - timer contents + a fixed compensation delay) is loaded into the timer.
• the IRQ vector is set to point to the TRIP routine and the programme returns to the ENABLE IRQ point.
• the TRIP routine consists simply of outputting a TRIP signal to the buffer 45 and latching this programme step.
• the RECOVERY routine consists of setting the IRQ vector to point to the TRIP routine and then returning immediately to the reset and disable IRQ point in the programme (the timer then stopping with its contents at maximum).
• Figure 8 is a flow sheet showing the "calculate new trip time " programme steps in more detail. As shown these steps include inputting the curve data from the selector, multiplying by a set value and adding a constant to arrive at. the ROM addresses of the appropriate 32 point co-ordinates in the ROM. A register, is then loaded with the actual current signal and a divide by 8 calculation is made and the result of this and the remainder are both stored. The result is used to select the point in the ROM to represent the stored "current" co-ordinate below the actual current and the resulting time data T L is loaded into a register. Then the time data T H from the next ROM location is loaded into another register. The new trip time T is then calculated from
• the programme described ensures that interpolation between the stored fixed points on the characteristic curves is carried, out in the time calculation stage.
• the "adjusted" trip time calculation ensures that when the current is changing the new trip time is effectively shortened in proportion to the amount of the already expired portion of the previous trip time. This corresponds approximately to the thermal behaviour of a conventional thermal circuit breaker in which the trip time for a given overcurrent condition will depend on the immediately pre-existing current condition, i.e. if the current rises to 1.5 x threshold tripping will occur more quickly if the current was previously 1.25 x threshold than it would if the current was previously less than the threshold.
• circuits and all the components used in the above described embodiment can be common to a wide range of devices only the current transformers being changed to determine the actual thresholds.
• the technique of storing in the ROM of the co-ordinates of fixed points on the characteristic curves is not employed.
• the selector means is a more complicated switch array, or even a keyboard, which is or are used to input to the circuit 32 the co-ordinates of a number of points (e.g. 6 points) on the desired curve, each point being individually set independently of the others.
• the ROM would include a log look-up table and an anti-log look-up table may also be included, or alternatively a programme could be employed to obtain anti-log values from the log look-up table.
• Figure 9 shows the modified "calculated new trip time" programme steps used in this modified form of the invention. As shown these include inputting all the time curve coordinate data to a register, inputting the input current and storing the log of this. Finding the co-ordinates of the specified points above and below this log value and us ing these to calculate the slope of the characteristic between these points, calculating T in terms of the actual current, one co-ordinate and the slope and then outputting the anti-log of T .

Landscapes

• Emergency Protection Circuit Devices (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=10511631

Family Applications (1)

Country Status (4)

Families Citing this family (16)

Family Cites Families (3)

• 1981
  • 1981-02-23 JP JP50064681A patent/JPS57500313A/ja active Pending
  • 1981-02-23 WO PCT/GB1981/000026 patent/WO1981002496A1/en not_active Application Discontinuation
  • 1981-02-23 EP EP19810900439 patent/EP0047749A1/de not_active Withdrawn
  • 1981-10-21 DK DK465381A patent/DK465381A/da not_active Application Discontinuation

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events