Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
  • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
  • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
  • H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
  • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
  • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
  • H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle

Definitions

• This invention relates generally to the electronic signal processing art and in particular to an improved frequency synthesizer using multiple dual modulus pre- scalers.
• an improved frequency synthesizer which is capable of operating at very high frequencies a a result of using two dual modulus prescalers as part of the loop dividing function.
• a reference signal is applied to a first input of a phas comparator.
• This reference signal is then compared to a signal applied to second input of the phase comparator and a control signal representative of the phase differ ⁇ ence between the two signals is generated.
• This control signal is then applied to a signal controlled oscillator which produces an oscillator signal of frequency f in response to the control signal.
• the controlled oscil ⁇ lator signal of frequency f is then applied to a pro ⁇ grammable frequency divider for frequency dividing the controlled oscillator signal by a divisor N .
• the programmable divider includes a first prescaler for frequency dividing the controlled oscillator signal by one of two predetermined integer divisors, M and M 1 . Th output of the first prescaling means is then counted in counter circuit so that an output signal is generated when the counter has counted a given number of signal pulses C.
• the output of the first prescale is applied to a second prescaler for frequency dividing by one of two predetermined integer divisors P and P' .
• Fig. 2 is a schematic diagram of the loop divider 200 shown in Fig. 1.
• a signal of frequency f from the control oscillator 120 (See Fig. 1) is applied to the input 130 of a dual modulus prescaler 132 with moduli M and M' where M 1 is equal to M + 1 in the prefer ⁇ red embodiment.
• the input 195 of the gate 194 and the gate 196 will be disabled since the low from the output 190 is applied to the input 197 of the AND gate 196.
• the signal from the Q output 172 applied to the input 193 of the AND gate 194 will be gated through to the CLK B input 214 of the B counter 210.
• the output 189 of the NAND gate 188 is coupled to the SET A input 222 of the A counter 220. Since the output 189 of the gate 188 was high, the SET A input 222 will also be high which will cause the A counter to reset.
• This low on the output 190 is also applied to the SET B input 216 of the B counter 210 which allows the B counter 210 to be decremented by the signal on the CLK B input 214.
• the input 195 of the AND gate 194 will be low thus disabling the AND gate 194, and the input 197 of the AND gate 196 will be high thus enabling the AND gate 196.
• the result of this is that the signal from the Q output 172 of the prescaler 170 is now gated through the AND gate 196 and applied to the C K A input 224 of the A counter 220. Simultaneously, the same signal from the prescaler output 172 is blocked by the disabled AND gate 194 so that no signal is applied to th CLK B input 214 of the B counter 210.
• the high on the output 190 of the NAND gate 192 is applied t the SET B input 216 of the B counter 210. This causes the B counter to be reset.
• the lov; on the output 189 of the NAND gate 188 is also applied to the SET A input 222 of the A counter 220, which allows the A counter 220 to be decremented by the signal on the CLK A input 224. This results in the B counter 210 being set while the A counter 220 is decrementing.
• a high signal is generated on its ZERO A output 226 which is applied to the input 181 of the NAND gate 182.
• This signal together with the signal from the ⁇ Q output'174 applied to the input 183 of NAND .gate 182 fro the control logic input 178, results in a signal applied to the input 187 of the NAND gate 188 causing the flip- flop composed of NAND gates 188 and 192 to change to the opposite state.
• the B counter 210 will begin to decrement and the A counter 220 will be reset in the same manner as described previ ⁇ ously.
• the signal which occurs on the SET B input 216 of the B counter 210 is also coupled via the feedback line 199 to the enable input 175 of the dual modulus prescaler 170. Whenever a transition occurs at the enable input 175, the modulus of the prescaler 170 will be changed. In the preferred embodiment of the divider, the prescale 170 will have a modulus of P during the B count and a modulus of P + 1 during the A count.
• the signal on the feedback line 199 is also coupled to the output 230. Thus, the signal on the output 190 of the NAND gate 192 is coupled to the output 230.
• the divide ratio can be incremented by one by the process of reprograrnming the value of B to be reduced by one and reprograrnming the value of A to be increased by one, resulting in the net increase in the divide ratio N of one.

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• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

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• 1980
  • 1980-02-13 US US06/121,333 patent/US4316151A/en not_active Expired - Lifetime
• 1981
  • 1981-01-05 WO PCT/US1981/000010 patent/WO1981002371A1/fr not_active Application Discontinuation
  • 1981-01-05 EP EP19810900769 patent/EP0045799A4/fr not_active Withdrawn
  • 1981-01-05 BR BR8106699A patent/BR8106699A/pt unknown
  • 1981-01-05 JP JP56501129A patent/JPH0255976B2/ja not_active Expired
  • 1981-01-12 CA CA000368265A patent/CA1150371A/fr not_active Expired

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