EP0026959A1 - Système pour générer des signaux digitaux correspondant à des fonctions sélectionnées - Google Patents

Système pour générer des signaux digitaux correspondant à des fonctions sélectionnées Download PDF

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Publication number
EP0026959A1
EP0026959A1 EP80200951A EP80200951A EP0026959A1 EP 0026959 A1 EP0026959 A1 EP 0026959A1 EP 80200951 A EP80200951 A EP 80200951A EP 80200951 A EP80200951 A EP 80200951A EP 0026959 A1 EP0026959 A1 EP 0026959A1
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EP
European Patent Office
Prior art keywords
bit
bits
point
signals
rolling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP80200951A
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German (de)
English (en)
Inventor
André Jules Joseph Oosterlinck
Herman Benedictus Van Den Berghe
Jozef Gerard Maria De Roo
Jean Alois Rachel Norbert Van Daele
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Katholieke Universiteit Leuven
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Katholieke Universiteit Leuven
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from NL7907452A external-priority patent/NL7907452A/nl
Priority claimed from NL8002507A external-priority patent/NL8002507A/nl
Application filed by Katholieke Universiteit Leuven filed Critical Katholieke Universiteit Leuven
Publication of EP0026959A1 publication Critical patent/EP0026959A1/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/20—Function-generator circuits, e.g. circle generators line or curve smoothing circuits

Definitions

  • the invention relates to a system for generating digital signals corresponding to functions of a selectable number of variables, said functions corresponding to a selectable analytical relation and being of the type that can be described in a discrete form by a differential-relation or a simultaneous system of differential-relations and at least one boundary- condition or initial condition.
  • the invention aims to offering a solution for the disadvantages mentioned of the prior art and thereto provides a system of the type described in the preamble, said system according to the invention being characterized by:
  • the system according to the invention is able to generate functions, e.g. corresponding with straight lines circles, parabolic curves, or trigonometric functions, logarithmic functions, exponential functions, Bessel- functions, line-figures in multi-dimensional spaces, e.g. helixes, planes, conic sections, spheres, solids of revo- being a factor 10 to 100 tires as high as can be obtained with the known prior art systems.
  • functions e.g. corresponding with straight lines circles, parabolic curves, or trigonometric functions, logarithmic functions, exponential functions, Bessel- functions, line-figures in multi-dimensional spaces, e.g. helixes, planes, conic sections, spheres, solids of revo- being a factor 10 to 100 tires as high as can be obtained with the known prior art systems.
  • the system according to the invention is suited for performing the most diverging arithmetical and other mathematical operations, e.g.: multiplying; squaring; generating of functions of the most various kinds; integration; determining logarithms; determining inverse functions; determining for a given function of a value or values of one variable corresponding to a selected value of other variables determining conic section; designing nomographs; performing coordinate transformations; etc.
  • displaying a function on a graphic display e.g. a picture- screen or a x-y-plotter
  • use as function-generator for universal application controlling tool machinery, such as drilling machines and fret-saw-machines; performing calculations for designing e.g. integrated circuits.
  • a system according to the invention being suited for generating digital signals corresponding to curves may be characterized by second comparing means for, after forming a new part of said function, successively comparing, in the direction from the least significant bit (LSB) to the most significant bit (MSB), bits of equal significance of said signals each corresponding to one variable, the output signals of said second comparing means in case of detection of the first unchanged bits-group being fed to said rolling-point determining means for changing a previously determined rolling-point.
  • the rolled part will in general be smaller now. In this way by integration of the difference-equation or of the system of simultaneous difference equations a curve can be generated. Previously found points are according to the described procedure dynamically being accounted for.
  • the invention further relates to a system for subjecting selectable curves to selectable transformations.
  • Such a system is known in various implementations
  • an optic system comprising lenses, mirrors and the like, which the aid of which magnifications and reductions, rotations, translations, dilatations and combinations thereof, e.g. direction-dependent rescaling, can be accomplished.
  • Such a prior art system is mechanically complicated, it has a limited flexibility as optical systems most often offer a limited area of configurations having - acceptable picture qualities, and it is vulnerable and therefore not fully reliable.
  • the invention has at its purpose to provide an electronic curves- transformation system having a processing speed which is substantially larger than the speed of the prior art systems.
  • a further purpose of the invention is to provide an electronic transformation system that is also adapted to function at high speed in more dimensions.
  • the attention is drawn for instance to potential application in industrial robots, or manipulators in which e.g. use is made of a number independent elements each having three degrees of freedom of translation and three degrees of freedom of rotation.
  • the invention provides a system of the type set out in the preamble, said system comprising
  • Fig. 1 shows a two-dimensional points-grid as a part of the discretized x-y-plane. Both coordinates can only assume values corresponding with the natural numbers 0, ...., N.
  • the point A indicated as. example has the coordinates (x A' y A ).
  • Fig. 2 shows in which way points indicated with three crosses (x), corresponding with a part of a discrete graph, can be used for forming a further part of said graph connected thereto.
  • the grid points are indicated with (.).
  • the position of the rolling is determined by a bits-group, which for this two-dimensional case consists of two bits and thus may be referred to as a "bit-couple", i.e. a characterizing of determining quantity (Dx i , Dy i ), consisting of two binary numbers. It will be appreciated that four bit-couples and thus also four rolling points are possible.
  • Fig. 3 shows these four possibilities under the assumption that the first bit gives a movement in downward direction for the value "1" and for the value "0" no movement in downward direction and the second bit for the value "1" a movement in the right hand direction and for the value "0" no movement in the right hand direction.
  • the bit-couples are formed on basis of the binary BCD-presentation of the characteristic numbers Dx and Dy to be described in more detail later. Of these binary numbers from the most significant bit (MSB) through the least significant bit (LSB) the bits of equal significance are couple-wise combined.
  • bit-couple gives a weight to the selected direction.
  • the direction-couple serves for the incrementing or decrementing of the x-and y- registers.
  • the "sign" changes at the moment on which the register values pass zero.
  • the resolution is determined by the bit-resolution as obviously using more bits the discretized curve forms a better approximation of the analoge curve to be simulated, so that at a greater bit-resolution the procedure penetrates deeper to the less significant bits, so that also the information contained in these bits is used.
  • Fig. 6 shows the manner in which the arc of a circle can be generated.
  • the difference-equation corresponding therewith has the form:
  • the linear transformation can further be applied for performing multiplication or division.
  • E.g. fig. 7 shows For multiplication the following relation holds: For division:
  • the system according to the invention is adapted to integrate a general system of differential-relations.
  • the procedure is a selection of bits-groups (equally significant bits of the binary coded numbers DX, DY, DZ, ..) which represent the position of rolling-points in a n-dimensional space.
  • bits-groups as well as the bits-groups themselves may change. This is caused by the differential-relations being evaluated on certain moments through the functions F, G, H, ....
  • a possible strategy is: the functions F, G, H, ... only being evaluated in the rolling points and the normal order of the bits-group selection being reset to that particular bits-group of which all more significant bits-groups have remained unchanged after the evaluation.
  • This interruption and resetting of the normal procedure of bits-group selection causes a forming by rolling off of line-parts having variable lengths. These line-parts also have variable directions; however, they continuously overlap one another,so that a continuous curve is being generated.
  • Fig. 8A shows schematically a Dx-register 1 and a Dy-register 2, both registers being of the BCD-type. According to fig. 8A these registers are arranged such that bits with equal significances are positioned on the same horizontal positions; the MSB takes the ultimate left-hand position and the LSB takes the ultimate righthand position.
  • the numbers under the Dy-register 2 indicate the order numbers of the bit-couples (Dx 0 , Dy 0 ), (Dx 1 , Dy 1 ), etc., respectively.
  • Fig. 8B shows the order number of the selected bit-couple (0,1,2,3,4,5, etc.), in dependance of the time, i.e. the successive moments on which a bit-couple is selected.
  • the point 1 is a symmetry-point for the line between 0 and 2.
  • the point 3 is a symmetry-point for the line between 0 and 6.
  • the point 7 is a symmetry-point for the line between 1 and 14.
  • the point 15 is a symmetry-point for the line between 0 and 30.
  • Fig. 9 shows the schematic diagram of a system adapted for generating signals corresponding with straight curves.
  • bit-couple selection unit or checking unit 3 the bit-couple selection unit or checking unit 3; a data unit 4, of which the Dx-register 1 and the Dy-register 2 forms part; and an input/output-unit 5.
  • a clock signal applied through an input 6 controls a digital 9-bits counter 7.
  • This counter is of the common binary BCD-type; the respective counting values at the multiple output are presented in table I.
  • the multiple output of the counter 9 is connected with a bit-couple selection means 8 in which for each condition of the counter one of the nine possible bit-couples is selected (see table 1) and is applied to two 9-bits registers, namely the registers 1 and 2 mentioned already,comprising the increments/decrements Dx and Dy in BCD-code.
  • These registers 1 and 2 can at the beginning of the procedure (or of the 512-step cycle) be loaded with the decrements Dx and Dy, namely through the inputs 9 and 10.
  • this bit-couple (Dx i , Dy i ) is from the outputs of the data-unit 4 fed to an interpretation- module 11 forming part of the input/output unit 5 and in which said bit-couple is combined with a direction-couple applied through two inputs 12, 13 for forming control.
  • signals for two registers 14, 15 comprising the absolute x-position and the absolute y-position,respectively. In the beginning of the cycle these two registers comprise the beginning position of the line to be constructed and at the end of the cycle they comprise the final position.
  • the intermediate points can now be delivered through the outputs 16, 17 for memorizing in a memory, for graphic display or direct read-out for the case the system is used as a function generator.
  • Fig. 10 the clock signal z applied to the input 6 controls a coupled series of elementary dividers-by-two or bistable flip-flops 58-66. These dividers form together a 9-bits binary counter. As indicated in table 1 each counting position corresponds with one single bit-couple selection S.. This selection takes place with the aid of a circuit of binary'logics and results in 9 bit-couple selection signals S 0 ,....,S 8 . Thus e.g. the line S 3 is activated (i.e. the bit-couple 3 is selected) at the counting position 0000111 or 7.
  • Fig. 11 the decrements Dx and Dy are considered to be present in two 8-bits registers, comprising mono-stable flip-flops, the read-in operation taking place under the influence of a LOAD-signal applied to an input 68.
  • the outputs of these flip-flops all comprise buffers, 71 - 79 and 80 - 88 respectively, controllable by S i , so that at a bit-couple selection S i the bit-couple Dx i , Dy i appears at two outputs 69 and 70.
  • this bit-couple determines, together with a direction-couple Sx, Sy, how the absolute (x, y)-position of the point to be constructed is to be adapted.
  • Sx, Sy a direction-couple
  • two 9-bits binary up/down-counters 56, 57 are used which can be loaded with the starting position (x (0) ), (y (0) ).
  • the absolute position (x, y) can at any moment be read out from these up/down-counters and further be processed, used or memorized.
  • Fig. 13 shows an other embodiment of the bit-couple selection unit which is indicated by the reference 3 in fig. 9.
  • the bit-couple selection unit 18 according to this embodiment is able to perform the same operations as the bit-couple selection unit 3 according to fi g . 9 and 10 using a substantially lesser number of parts.
  • the bit-couple selection unit 18 comprises a programmable logic unit 19 and a series of 8 bistable flip-flops 20, 21, 22, 23, 24, 25, 26, 27.
  • a clock signal z l applied to an input 28 serves for controlling the unit 18.
  • Table III shows in terms of a program the operations of the programmable logic unit 19.
  • the truth-table can be interpreted as follows.
  • the sequence of the bit-couple selection is invariable, as is presented in fig. 8B and table I.
  • the selection of a certain bit-couple i has effect that one and only one condition-quantity, namely Q i , is changed (i.e. from the value "1" to the value "0” or from the value "0” to the value "1"), so that the condition-vector travels through a Gray-code-sequence.
  • this Gray-code is defined as a code in which during the counting never more than one bit at the time changes.
  • bit-couple S 8 does not necessarily have to be fed back.
  • the bit-couple S 8 does not necessarily have to be fed back.
  • the presented 8 bistable flip-flop 20 through 27 and the programmable logic unit 19 having 8 inputs. 8 product terms and 8 outputs.
  • the important advantage of this circuit in relation to the previous embodiment is that the rate with which straight lines can be generated is almost ten times as high: using this circuit the frequency of the clock signal z can be raised up to 10 MHz.
  • Fig. 14 shows the extension of the straight-lines generator as discussed to form a curves-generator. Analogous to the circuit according to fig. 9 in the circuit according to fig. 14 three units can be discriminated: a checking-unit 29, a data-unit 30 and an input/output 31.
  • the checking-unit 29 consists of a module 32 comprising 8 bistable flip-flops and a programmable logic unit 33.
  • the outputs of the flip-flop-module 32 are connected with a number of the inputs of the programmable logic unit 33.
  • the outputs of the unit 33 deliver bit-couple selection signals S i which at the one side select the wanted bit-couples, in the same way as according to fig. 11, and which at the other side deliver the control signals from the flip-flop-module 32 (compare figure 13).
  • the bit-couple selection which is fixedly programmed in the programmable logic unit 33 is determined by the condition of the signals at the inputs.
  • the outputs of a comparator-module 34 to be discussed later forming part of the data-unit 30 are connected with a second set of inputs of the programmable unit 33.
  • This second set of inputs forming an extension relative to the straight-lines generator discussed earlier effect that the regular sequence of the bit-couples selection, as it occured during the generation of straight lines (see e.g. figure 8B ans table I), is interrupted and reset in time. This interrupting and resetting of the normal sequence has to occur at each moment the previously selected bit-couples have changed up to that rolling-point that corresponds with an unchanged bit-couple, as has been discussed before. Referring to the truth table in table II it can be verified , which new condition-vector is associated with a corresponding unchanged bit-couple.
  • Fig. 15 shows a more detailed schematic diagram of the checking unit 29.
  • the attention is drawn to the analogy with the circuit according to fig. 13.
  • the programmable logic unit 33 not only comprises the inputs Q 0 ⁇ Q 7 , connected with the flip-flop module 32, but also 9 additional inputs C 0 ⁇ C 7 and 34, and, apart from the outputs R 1 ⁇ R 8 , an additional output L 0 .
  • the 'interrupting and the resetting in time of the sequence of the bit-couple selection then always takes place during the time interval, in which the bit-couple 0 is selected.
  • bit-couple signal So is not dependent upon an output signal of the programmable unit.33 but exclusively of the clock pulse signal z l , devided by 2, namely z 0 ,which also is applied to said output 34.
  • the other bit-couple selection signals S 1 ⁇ S 8 are during said interval disabled by NAND-gates 35, 36, 37, 38, 39, 40, 41, 42, as now several outputs of the programmable logic unit 33 (in correspondance with the bit-couple selection signals) can be activated.
  • the normal sequence e.g. for forming a straight line
  • one and only one output R i of bit-couple selection signals S i is activated.
  • the resetting in time more than one condition-variable Q i has to be changed as e.g. is indicated in table IV
  • Table V shows the program of the programmable logic unit 33. Particular features of the unit 33 are: 9 outputs, 17 inputs, 4 product terms.
  • This unit 30 comprises a Dx-register 43 and a Dy-register 44 of which the nine bit-couples with controllable buffers can be selected and transmitted to the input/output 31 drawn in detail in fig. 11. Further a comparator-module 34 is present serving for generating the important input-variables C 0 ⁇ C 7 for the programmable unit 33. The schematic diagram of this comparator-module 34 is drawn in detail in fig. 16.
  • Dx- and Dy-registers 43, 44 can be loaded with (F(x,y,z,) and (G(x,y,z,) respectively, not only at the beginning of a generation cycle but now also during each clock-period, namely on a moment after comparing the bit-couples Dx i , Dy i and F., G i .
  • This unit comprises to 9-bits up/downcounters 45, 46 which score the absolute x- y- values, as is the case in the circuit according to fig. 12.
  • Control signals are at one hand formed by the selected bit-couple and at the other hand by the direction-couple.
  • the up/down counters 46, 47 are obviously also loadable with a initial position (x (0), y (0) ) by means of the inputs 47, 48, respectively. At any moment the absolute position (x ,y) can be delivered through the x-output 49 and the y-output 50.
  • the absolute x, y-position is, together with a third value, memorized in a z-register 51, loadable through a loading input 52, applied to a calculating unit 53, which is adapted to transform the number x, y and z (each comprising 9 bits) to two numbers of 9 bits F (x,y,z,) and G (x,y,z,), which are available on the lines indicated with 54, 55.
  • the function to be performed by the calculating unit 53 can be adjusted through control inputs 56.
  • the calculating unit 53 transforms information from the registers x,y,z to the registers F, G.
  • the z-register 51 forms the connection with other simular modules in solving difference equations of higher orders.
  • the input/output unit 31 further comprises an interpretation module 89 in which a bit-couple applied to two inputs 90, 91 is combined with a direction-couple applied through two inputs 92, 93 to form control signals for the up/down counter 45, 46.
  • Fig. 18 shows a schematic diagram of a universal curves generator.
  • Three main blocks 101, 102, 103 can be distinguished.
  • the first part 101 serves for controlling and contains condition-counters 104 and the priorty- logic 105.
  • the second part 102 of the data-part contains the differential registers DX, DY, DZ ... 106 and the bits-groupselectors 107.
  • the third part 103 serves for input/output, namely the programming of the differential-relations 108 F,G,H.... and the solution- counters 109 X, Y, Z, ...The whole system is synchronously clocked.
  • the processor is controlled by a typically sequential machine having memory-elements and combinatorial logics, external inputs and external outputs.
  • the new condition (a) is determined by the old condition (b),the old differential-registers DX, DY, DZ... (c) and the differential-relations F, G, H, ... (d). Each moment a new rolling-point is being selected, DX, DY, DZ, ... are being evaluated by F, G, H, ...
  • the priority logics generate the index i of the bits-group (e) to be selected.
  • the fitting-bits-groups (f) are fed into the binary counters X, Y, Z, ... which are clocked into that direction, that is determined by SX, SY, SZ, ... (g).
  • a prototype of the present processor is developed. It is a curves generator including three differential-relations and consists of about 40 SSI and MSI TTL IC's (nc arithmetic modules). As acordal processor the module generates 2,5 x 10 points per second ( a new X,Y,Z, each 400 ns) which is directly written into a video - memory and read out to be presented on a TV-monitor.
  • a three dimensional points-grid X,Y,Z is taken as a base, the coordinates of said grid being the integers running from 0 through N.
  • a curve in said points grid can be described by elementary displacement-bits (DX., DY . , DZ i ) and direction-bits (SX, SY, SZ).
  • the displacement-bits indicate, whether the curve displaces according to the related coordinate axis in the direction indicated by the direction-bits.
  • This elementary dis- placemnets can e.g. correspond with the output signals of the system described in the foregoing, for generating digital signals corresponding to selectable functions or "function-generator". They also can be directly based an other relative code (relative i.e.: from point to point) of a curve or a contour (e.g. Freeman-code).
  • a transformation of the present type can be formulated in terms of matrix-multiplication, in which from a starting vector (X 0 , Y 0 , Z 0 ) by multiplication with a transformationmatrix a transformed vector (X , Y , Z ) is determined: For instance for a certain two-dimensional dilatation transformation the following relation holds:
  • Tnus according to the invention it is possible to avoid the nine multiplications, which are normally necessary, through ordinary accumulations. Further no systematic errors can occur. Thus a closed contour remains closed, even after transformation.
  • Fig. 19 shows and E and O, respectively, as to examples of letter-symbols which can in a word-processor be described with a single contour and a combination of an inner contour and an outer contour, respectively,
  • Fig. 20a shows a square as an example of an original curve to be transformed by the transformationsystem according to the invention.
  • Fig. 21 shows a very simplified block-schematic diagram of system according to the invention.
  • This system comprises a memory block 110, the inputs of which are connected with the inputs of a block of adding registers 111.
  • the addresses for the memory block 110 are fed thereto through address inputs 112 and consist of the displacement-bits DX., DY i , DZ. and the direction bits-SX, SY, SZ.
  • the below table shows the 64 data-words having orders 0 through 63, which are stored in 64 memory-positions of the memory-block together with the 64 potential addresses in the form of the potential combinations of the direction-bits.It will be appreciated that each address- word is uniqually related with one data-word and that the 64 data-words comprise all possibilities.
  • the read-out new displacements in the form of the data + dX i , dY i , dZ i are continiously accumulated by the adding registers 111.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Generation (AREA)
EP80200951A 1979-10-08 1980-10-08 Système pour générer des signaux digitaux correspondant à des fonctions sélectionnées Withdrawn EP0026959A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
NL7907452 1979-10-08
NL7907452A NL7907452A (nl) 1979-10-08 1979-10-08 Stelsel voor het genereren van met te kiezen funkties corresponderende digitale signalen.
NL8002507A NL8002507A (nl) 1980-04-29 1980-04-29 Elektronisch transformatiestelsel.
NL8002507 1980-04-29

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EP0026959A1 true EP0026959A1 (fr) 1981-04-15

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7242403B2 (en) 2004-09-20 2007-07-10 Timothy Phelan Graphical display of multiple related variables
CN107621701A (zh) * 2017-09-07 2018-01-23 苏州大学 产生双指数贝塞尔高斯光束的方法及系统

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 18, No. 5, October 1975, New York, USA, GARDNER: "Modification of BRESENHAM's algorithm for displays", pages 1595-1596 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7242403B2 (en) 2004-09-20 2007-07-10 Timothy Phelan Graphical display of multiple related variables
CN107621701A (zh) * 2017-09-07 2018-01-23 苏州大学 产生双指数贝塞尔高斯光束的方法及系统
CN107621701B (zh) * 2017-09-07 2023-08-25 苏州大学 产生双指数贝塞尔高斯光束的方法及系统

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Inventor name: VAN DAELE, JEAN ALOIS RACHEL NORBERT

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Inventor name: DE ROO, JOZEF GERARD MARIA