EP0026959A1

EP0026959A1 - System for generating digital signals corresponding to selectable functions

Info

Publication number: EP0026959A1
Application number: EP80200951A
Authority: EP
Inventors: André Jules Joseph Oosterlinck; Herman Benedictus Van Den Berghe; Jozef Gerard Maria De Roo; Jean Alois Rachel Norbert Van Daele
Original assignee: KU Leuven Research and Development
Current assignee: KU Leuven Research and Development
Priority date: 1979-10-08
Filing date: 1980-10-08
Publication date: 1981-04-15

Abstract

The invention relates to a system for generating digital signals corresponding to functions of two variables, said functions corresponding to a selectable analytical relation and being of the type that can be described in a discreet form by a difference-equation or a simultaneous system of difference-equations and at least one boundary-conditions or initial condition.

It is an object of the invention to provide such a system which is adapted to generate said signals at a considerably higher rate. In view thereof the invention provides a system of the type mentioned which is characterized by:

(1) a signal generator for forming binary signals for each of said two variables, said signals being representative for said difference-equation(s) and said at least one boundary-condition or initial condition;
(2) comparing means for successively comparing, in the direction from the most significant bit (MSB) to the least significant bit (LSB), bits of equal significance of said two signals, each of which corresponds to one variable;
(3) rolling-point determining means for determining a rolling point on basis of at least one of said comparing operations, said rolling-point being a point determined by the values of both variables and relative to which a preceding part of said function, considered to be graphically displayed in cartesian coordinate-system, is rolled over 180° so as to obtain a next part of said function connected to said preceding part; and
(4) memory-means for memorizing signals corresponding to at least said last-mentioned next part of said function in the form of bit-couples.

Description

The invention relates to a system for generating digital signals corresponding to functions of a selectable number of variables, said functions corresponding to a selectable analytical relation and being of the type that can be described in a discrete form by a differential-relation or a simultaneous system of differential-relations and at least one boundary- condition or initial condition.
In the prior art systems of said type usually said functions were point by point generated by discrete integration of a difference-equation or a system of . difference-equations. Practically thereto use was made of programmable hard-ware calculating apparatus in combination with adequate soft-ware.
For such a calculating method for each point to be generated of the function a number of calculating steps have to be performed. If certain requirements are imposed to the resolution, i.e. the step size may not exceed a certain value, this imposes limitations to the rate with which functions can be generated. In view to certain application fields to be mentioned hereafter this lack of sufficient rate can be very inconvenient or even prevent use.
The invention aims to offering a solution for the disadvantages mentioned of the prior art and thereto provides a system of the type described in the preamble, said system according to the invention being characterized by:

1. a signal generator for forming binary signals for each of said two variables, said signals being representative for said differential-relation(s) and said at least one boundary-condition or initial condition for each;
2. comparing means for successively comparing, in the direction from the most significant bit (MSB) to the least significant bit (LSB), bits of equal significance of said signals, each of which corresponds to one variable;
3. rolling-point determining means for determining a rolling-point on basis of at least one of said comparing operations, said rolling-point being a point determined by the values of said variables and relative to which a preceding part of said function, considered to be graphically displayed in a orthogonal coordinate-system, is rolled over 180° so as to obtain a next part of said function connected to said preceding part; and
4. memory means for memorizing signals corresponding to at least said last-mentioned next part of said function in the form of bit-groups.

The system according to the invention is able to generate functions, e.g. corresponding with straight lines circles, parabolic curves, or trigonometric functions, logarithmic functions, exponential functions, Bessel- functions, line-figures in multi-dimensional spaces, e.g. helixes, planes, conic sections, spheres, solids of revo- being a factor 10 to 100 tires as high as can be obtained with the known prior art systems.
The system according to the invention is suited for performing the most diverging arithmetical and other mathematical operations, e.g.: multiplying; squaring; generating of functions of the most various kinds; integration; determining logarithms; determining inverse functions; determining for a given function of a value or values of one variable corresponding to a selected value of other variables determining conic section; designing nomographs; performing coordinate transformations; etc.
Several applications can be mentioned, among others: displaying a function on a graphic display, e.g. a picture- screen or a x-y-plotter; use as function-generator for universal application; controlling tool machinery, such as drilling machines and fret-saw-machines; performing calculations for designing e.g. integrated circuits.
A system according to the invention, being suited for generating digital signals corresponding to curves may be characterized by second comparing means for, after forming a new part of said function, successively comparing, in the direction from the least significant bit (LSB) to the most significant bit (MSB), bits of equal significance of said signals each corresponding to one variable, the output signals of said second comparing means in case of detection of the first unchanged bits-group being fed to said rolling-point determining means for changing a previously determined rolling-point. The rolled part will in general be smaller now. In this way by integration of the difference-equation or of the system of simultaneous difference equations a curve can be generated. Previously found points are according to the described procedure dynamically being accounted for.
The invention further relates to a system for subjecting selectable curves to selectable transformations.
Such a system is known in various implementations For fotocopying purposes for instance most often use is made of an optic system, comprising lenses, mirrors and the like, which the aid of which magnifications and reductions, rotations, translations, dilatations and combinations thereof, e.g. direction-dependent rescaling, can be accomplished. Such a prior art system is mechanically complicated, it has a limited flexibility as optical systems most often offer a limited area of configurations having - acceptable picture qualities, and it is vulnerable and therefore not fully reliable. An improvement relative to the optical systems is formed by the electronic calculating systems, in which calculation of a transformed curve from a given curve is performed in soft-ware, pro^gramm-controlled A system of this last-mentioned type, however, has a relative complicated construction and is not able to work at a high rate, due to the necessarily large number of programm steps.
An important application of the mentioned electronic is related to the text processing apparatus or word-processors. As particularly for such processors a high processing speed is of the utmost importance, the invention has at its purpose to provide an electronic curves- transformation system having a processing speed which is substantially larger than the speed of the prior art systems.
A further purpose of the invention is to provide an electronic transformation system that is also adapted to function at high speed in more dimensions. In this connection the attention is drawn for instance to potential application in industrial robots, or manipulators in which e.g. use is made of a number independent elements each having three degrees of freedom of translation and three degrees of freedom of rotation.
In order to realize the above purposes the invention provides a system of the type set out in the preamble, said system comprising

(1) addressable first memory-means having a number of memory positions, in each of which a data-word consisting of a linear combination with the multiplication factors 0,+1 or -1 of the elements (a_ij) of the matrix representing a selected transformation is stored, said data-words forming a complete set;
(2) second memory-means for storing the coordinate data of a selected curve according to a discreet points-grid;
(3) computing means connected with the outputs of said first and second memory-means for computing by means of matrix multiplication of successive points of the transformed curve,
- a displacement in one dimension over one elementary grid distance being represented by a displacement bit (DX_i, DY_i, DZ_i, ...) and a direction bit (SX, SY, SZ, ...), said displacement bit indicating whether or not said curve displaces according to the coordinate axis involved in the direction indicated by said direction-bit,
- the possible address-words for said first memory-means consisting of the complete set of combinations of displacement bits and direction-bits.

Further features and details of the system according to the invention will be mentioned and elucidated referring to the drawings, which in view of the simplicity of the drawing mainly relates to a two-dimensional case. In the drawings:

Fig. 1 shows a part of the discretized x-y-plane;
Fig. 2 a schematically presented rolling operation, which is the basis of the system according to the invention;
Fig. 3 shows the four possible rolling points in one quadrant;
Fig. 4 shows the construction of a straight line according to the invention;
Fig. 5 shows the construction of an exponential curve according to the invention;
Fig. 6 shows the construction of a circle arc- according to the invention;
Fig. 7 shows a geometric schematic diagram as an illustration of the way in which according to the invention multiplying and dividing can be performed;
Fig. 8a shows a schematic presentation of a Dx- and a Dy-register;
Fig. 8b shows a graphical presentation of the order number of a selected bit-couple depending on the moments of selection;
Fig. 9 shows a schematic diagram of a system according to the invention for generating straight lines;
Fig. 10 shows a bit-couple selection unit forming part of the system according to fig. 9;
Fig. 11 shows a data-unit forming part of the system according to fig. 9;
Fig. 12 shows an input/output-unit forming part of the system according to fig. 9;
Fig. 13 shows another embodiment of.the bits-couple selection unit;
Fig. 14 shows a system according to the invention that is also adapted for generating curves;
Fig. 15 shows a schematic diagram of the check- unit forming part of the system according to fig. 14;
Fig. 16 shows a schematic diagram of the comparitor- module forming part of the system according to fig. 14.
Fig. 17 a schematic representation of the formation of a two-dimensional curve;
Fig. 18 a block-schematic diagram of a calculating assembly according to the invention ;
Fig. 19 two examples of fonts of a text-processing apparatus, which fonts can be described by a single contour or an inner contour together with an outer contour;
Fig. 20a a square as an example of a curve to be transformed;
Figures 20b to 20d examples of figures generated from the square according to fig. 20a by certain linear transformations; and
Fig. 3 a block diagram of the transformationsystem according to the invention.

Fig. 1 shows a two-dimensional points-grid as a part of the discretized x-y-plane. Both coordinates can only assume values corresponding with the natural numbers 0, ...., N. The point A indicated as. example has the coordinates (x_A' y_A).
Fig. 2 shows in which way points indicated with three crosses (x), corresponding with a part of a discrete graph, can be used for forming a further part of said graph connected thereto. The grid points are indicated with (.).
Use is made of a "rolling operation", i.w. in a manner to be described in more detail a rolling-point (o) is chosen, and afterwards each point (x) is moved over 180° with respect to that point (o). In this way the points indicated (+) are generated. This rolling operation is mathematically identical with multiplication of a (discrete) curve with "-I" or two successive mirror operations with respect to two orthogonal axes having arbitrary orientation through the rolling point (o). The points (+) thus obtained can for a next operation serve as points of the graph.
The position of the rolling is determined by a bits-group, which for this two-dimensional case consists of two bits and thus may be referred to as a "bit-couple", i.e. a characterizing of determining quantity (Dx_i, Dy_i), consisting of two binary numbers. It will be appreciated that four bit-couples and thus also four rolling points are possible. Fig. 3 shows these four possibilities under the assumption that the first bit gives a movement in downward direction for the value "1" and for the value "0" no movement in downward direction and the second bit for the value "1" a movement in the right hand direction and for the value "0" no movement in the right hand direction.

Thus for fig. 3a: (Dx_i, Dy_i) = (1,1);
fig. 3b: (Dx_i, Dy_i) = (1,0);
fig. 3c: (Dx_i, Dy_i) = (0,0);
fig. 3d: (Dx_i, Dy_i) = (0,1).

The bit-couples are formed on basis of the binary BCD-presentation of the characteristic numbers Dx and Dy to be described in more detail later. Of these binary numbers from the most significant bit (MSB) through the least significant bit (LSB) the bits of equal significance are couple-wise combined.
As an example: Dx = 12 = 0 0 0 0 1 1 0 0 Dy = 9 = 0 0 0 0 1 0 0 1 Bit-couples: (0,0), (0,0), (0,0), (0,0), (1,1), (1,0), (0,0), (0,1).
The significance of a bit-couple gives a weight to the selected direction.
It is to be noted that with the four possible bit-couples only one quadrant is covered. In order to be able to use all four quadrants in the flat plane further a direction-couple (Sx, Sy) is introduced. The four possible direction-couples have the following meanings:

(Sx, Sy) = (1,1): increasing x, decreasing y
(Sx, Sy) = (0,0): decreasing x, decreasing y
(Sx, Sy) = (1,0): increasing x, decreasing y
(Sx, Sy) = (0,1): decreasing x, increasing y

Anticipating to the implementation to be discussed later it is here already noted that the direction-couple serves for the incrementing or decrementing of the x-and y- registers. The "sign" changes at the moment on which the register values pass zero.
As an example now follows a description of the construction of a straight line (Dx, Dy) with Dx = a and Dy = b, a and b being constants.The successive rolling-points are (Dx_i, Dy_.) for i = 1,...., n (1= MSB; n = LSB), in which n = number of bits in the BCD presentation of a and b Fig. 4 shows as an example a case in which a = 10 and b = 6.

a = 10 = 1010
b = 6 = 0110

(1,0), see fig. 4a;
(0,1), see fig. 4b;
(1,1), see fig. 4c;
(0,0), see fig. 4d;

In view of the previous discussion it will be clear that according to the indicated principle only n (= number of bits) logical desicions are required for each time doubling the construction through the rolling-points.
The principles described in the previous text part can now be generalized in the framework of integrating a difference-equation of the following form
in which z = an arbitrary function.
In the case of a straight line :
The rolling points were successively taken from the MSB tc the LSB. In the generalized case the previous remark still holds, provided that the previously found rolling-points have not changed. If, however, a change has occured the procedure returns in the direction LSB to MSB until the first bit that has remained unchanged. This implies that the rolled part will be smaller now. Thus by integration a curve can develope in which dynamically previous points are being taken into account.
Figure 5 shows the construction of an exponential curve responding to the difference- equation
in which a = 9.
As an illustration of the construction according to figure 5 the following schematic survey may serve:
As roughly indicated in fig. 5 there exists a continuous movement of the rolling point position in both directions. This movement forms the balance between the rate at which graphs can be generated and the stability.
The resolution is determined by the bit-resolution as obviously using more bits the discretized curve forms a better approximation of the analoge curve to be simulated, so that at a greater bit-resolution the procedure penetrates deeper to the less significant bits, so that also the information contained in these bits is used.
Fig. 6 shows the manner in which the arc of a circle can be generated. The difference-equation corresponding therewith has the form:
The following schematic survey may serve as illustration of the graphical construction showed in fig. 6:
As has been noted already also difference-equations arranged as a simultaneous system can be solved. As an example the following system is mentioned:
with x(o) = U
(thus x = U cos
+ V sin
)
with y(o) = V
(thus y = -U sin
⁺ V cos
)
This circular tranformation can be used for generating a sine-function (U = B and V = 0), polar-coordinates transformation (!, U, V ?z,x as y = 0 vice versa), and rotation in a flat plane .
The linear transformation can further be applied for performing multiplication or division. E.g. fig. 7 shows
For multiplication the following relation holds:
For division:
By application of this transformation a rescaling can be performed of the junction points of a construction consisting of straight lines and curved lines. The several parts of the curves are generated again on a different scale.
The generation of a vector is only a specific example of the integration of the general set of differential-relation:

DX = F(X,Y,Z, ...)
DY = G(X,Y,Z, ...)
DZ = H(X,Y,Z, ...)
.
.
.

_X

The system according to the invention is adapted to integrate a general system of differential-relations. The procedure is a selection of bits-groups (equally significant bits of the binary coded numbers DX, DY, DZ, ..) which represent the position of rolling-points in a n-dimensional space.
The order of the selection of bits-groups as well as the bits-groups themselves may change. This is caused by the differential-relations being evaluated on certain moments through the functions F, G, H, .... A possible strategy is: the functions F, G, H, ... only being evaluated in the rolling points and the normal order of the bits-group selection being reset to that particular bits-group of which all more significant bits-groups have remained unchanged after the evaluation. This interruption and resetting of the normal procedure of bits-group selection causes a forming by rolling off of line-parts having variable lengths. These line-parts also have variable directions; however, they continuously overlap one another,so that a continuous curve is being generated.
As an example the solution of the system of differential relations:

DX = Y initial conditions: X₀ = A
DY =-X Y₀ = B
DZ = C Z₀ = 0

X = A cos Z/C + B sin Z/C
Y = -A sin Z/C + B cos Z/C

After the previous illustrations of the principles according to the invention and the examples of application thereof for the ccnstruction of two-dimensional graphic patterns now a discussion on the arrangement of the system according to the invention will follow.
First of 11 a system for generating straight curves will be presen:ed. As has been discussed earlier the sequence of the selection of the bit-couples (from MSB to LSB) isconstant. Figures 8A and 8B illustrate this.
Fig. 8A shows schematically a Dx-register 1 and a Dy-register 2, both registers being of the BCD-type. According to fig. 8A these registers are arranged such that bits with equal significances are positioned on the same horizontal positions; the MSB takes the ultimate left-hand position and the LSB takes the ultimate righthand position. The numbers under the Dy-register 2 indicate the order numbers of the bit-couples (Dx₀, Dy₀), (Dx₁, Dy₁), etc., respectively.
Fig. 8B shows the order number of the selected bit-couple (0,1,2,3,4,5, etc.), in dependance of the time, i.e. the successive moments on which a bit-couple is selected.
For this se^quation the attention is drawn to the mirror effect of the previous series of selected bit-couples around each rolling-point. The point 1 is a symmetry-point for the line between 0 and 2. The point 3 is a symmetry-point for the line between 0 and 6. The point 7 is a symmetry-point for the line between 1 and 14. The point 15 is a symmetry-point for the line between 0 and 30.
Fig. 9 shows the schematic diagram of a system adapted for generating signals corresponding with straight curves. The figure shows an example for the case of N = 8 or 9 bit-couples.
In the system according to fig. 9 three units are indicated with dotted lines: the bit-couple selection unit or checking unit 3; a data unit 4, of which the Dx-register 1 and the Dy-register 2 forms part; and an input/output-unit 5.
A clock signal applied through an input 6 controls a digital 9-bits counter 7. This counter is of the common binary BCD-type; the respective counting values at the multiple output are presented in table I.
As is apparent 512 clock pulses or timing units form one complete cycle.
The multiple output of the counter 9 is connected with a bit-couple selection means 8 in which for each condition of the counter one of the nine possible bit-couples is selected (see table 1) and is applied to two 9-bits registers, namely the registers 1 and 2 mentioned already,comprising the increments/decrements Dx and Dy in BCD-code. These registers 1 and 2 can at the beginning of the procedure (or of the 512-step cycle) be loaded with the decrements Dx and Dy, namely through the inputs 9 and 10. If the bit-couple i has been selected this bit-couple (Dx_i, Dy_i) is from the outputs of the data-unit 4 fed to an interpretation- module 11 forming part of the input/output unit 5 and in which said bit-couple is combined with a direction-couple applied through two inputs 12, 13 for forming control. signals for two registers 14, 15 comprising the absolute x-position and the absolute y-position,respectively. In the beginning of the cycle these two registers comprise the beginning position of the line to be constructed and at the end of the cycle they comprise the final position. The intermediate points can now be delivered through the outputs 16, 17 for memorizing in a memory, for graphic display or direct read-out for the case the system is used as a function generator.

Fig. 10 shows an example of the bit-couple selection unit 3 presented in fig. 9;
Fi^g. 11 shows an embodiment of the data-unit 4 presented in fig. 9;
Fig. 12 shows an embodiment of the input/output unit 5 according to fig. 9. These units will successively be discussed now.

Fig. 10: the clock signal z applied to the input 6 controls a coupled series of elementary dividers-by-two or bistable flip-flops 58-66. These dividers form together a 9-bits binary counter. As indicated in table 1 each counting position corresponds with one single bit-couple selection S.. This selection takes place with the aid of a circuit of binary'logics and results in 9 bit-couple selection signals S₀,....,S₈. Thus e.g. the line S₃ is activated (i.e. the bit-couple 3 is selected) at the counting position 0000111 or 7.
Fig. 11: the decrements Dx and Dy are considered to be present in two 8-bits registers, comprising mono-stable flip-flops, the read-in operation taking place under the influence of a LOAD-signal applied to an input 68. The outputs of these flip-flops all comprise buffers, 71 - 79 and 80 - 88 respectively, controllable by S_i, so that at a bit-couple selection S_i the bit-couple Dx_i, Dy_i appears at two outputs 69 and 70.
_Fig. ₁2: this bit-couple determines, together with a direction-couple Sx, Sy, how the absolute (x, y)-position of the point to be constructed is to be adapted. Thereto two 9-bits binary up/down-counters (56, 57) are used which can be loaded with the starting position (x⁽⁰⁾), (y ⁽⁰⁾). The absolute position (x, y) can at any moment be read out from these up/down-counters and further be processed, used or memorized.
Fig. 13 shows an other embodiment of the bit-couple selection unit which is indicated by the reference 3 in fig. 9. The bit-couple selection unit 18 according to this embodiment is able to perform the same operations as the bit-couple selection unit 3 according to fi^g. 9 and 10 using a substantially lesser number of parts. The bit-couple selection unit 18 comprises a programmable logic unit 19 and a series of 8 bistable flip- flops 20, 21, 22, 23, 24, 25, 26, 27. A clock signal z_lapplied to an input 28 serves for controlling the unit 18.
The principle of this circuit can best be presented by reference to the truth-table according to table II, in which the condition-vector Q (Q0→ Q7) results in forming of the output-vector R (R1 R₈). The outnut-vector equals the series bit-couple sel ction signals S₁ → S₈ and the bit-couple selection signal S₀ is formed by the clock signal z₁ d vided by two. It obviously appears from fig. 8B and table 1 that the bit-couple 0 should be selected each two clock pulses.
The truth-table according to table II has been realized by means of the program present in the unit 19 and the flip-flops 20 through 27.
Table III shows in terms of a program the operations of the programmable logic unit 19.
The truth-table can be interpreted as follows. The sequence of the bit-couple selection is invariable, as is presented in fig. 8B and table I. The selection of a certain bit-couple i has effect that one and only one condition-quantity, namely Q_i, is changed (i.e. from the value "1" to the value "0" or from the value "0" to the value "1"), so that the condition-vector travels through a Gray-code-sequence. As is well known, this Gray-code is defined as a code in which during the counting never more than one bit at the time changes.
It is to be noted that the bit-couple S₈ does not necessarily have to be fed back. For the realization it is sufficient to use the presented 8 bistable flip-flop 20 through 27 and the programmable logic unit 19 having 8 inputs. 8 product terms and 8 outputs. The important advantage of this circuit in relation to the previous embodiment is that the rate with which straight lines can be generated is almost ten times as high: using this circuit the frequency of the clock signal z can be raised up to 10 MHz.
Fig. 14 shows the extension of the straight-lines generator as discussed to form a curves-generator. Analogous to the circuit according to fig. 9 in the circuit according to fig. 14 three units can be discriminated: a checking-unit 29, a data-unit 30 and an input/output 31.
The checking-unit 29 consists of a module 32 comprising 8 bistable flip-flops and a programmable logic unit 33. The outputs of the flip-flop-module 32 are connected with a number of the inputs of the programmable logic unit 33. The outputs of the unit 33 deliver bit-couple selection signals S_i which at the one side select the wanted bit-couples, in the same way as according to fig. 11, and which at the other side deliver the control signals from the flip-flop-module 32 (compare figure 13).
The bit-couple selection which is fixedly programmed in the programmable logic unit 33 is determined by the condition of the signals at the inputs. The outputs of a comparator-module 34 to be discussed later forming part of the data-unit 30 are connected with a second set of inputs of the programmable unit 33. This second set of inputs forming an extension relative to the straight-lines generator discussed earlier effect that the regular sequence of the bit-couples selection, as it occured during the generation of straight lines (see e.g. figure 8B ans table I), is interrupted and reset in time. This interrupting and resetting of the normal sequence has to occur at each moment the previously selected bit-couples have changed up to that rolling-point that corresponds with an unchanged bit-couple, as has been discussed before. Referring to the truth table in table II it can be verified , which new condition-vector is associated with a corresponding unchanged bit-couple.
Fig. 15 shows a more detailed schematic diagram of the checking unit 29. The attention is drawn to the analogy with the circuit according to fig. 13. The programmable logic unit 33 not only comprises the inputs Q₀ → Q₇, connected with the flip-flop module 32, but also 9 additional inputs C₀ → C₇ and 34, and, apart from the outputs R₁ → R₈, an additional output L₀. The 'interrupting and the resetting in time of the sequence of the bit-couple selection then always takes place during the time interval, in which the bit-couple 0 is selected. It is further to be noted that the bit-couple signal So is not dependent upon an output signal of the programmable unit.33 but exclusively of the clock pulse signal z_l, devided by 2, namely z₀,which also is applied to said output 34. The other bit-couple selection signals S₁ → S₈ are during said interval disabled by NAND- gates 35, 36, 37, 38, 39, 40, 41, 42, as now several outputs of the programmable logic unit 33 (in correspondance with the bit-couple selection signals) can be activated. As has been discussed already, during the normal sequence (e.g. for forming a straight line) one and only one output R_i of bit-couple selection signals S_i is activated. During the resetting in time more than one condition-variable Q_i has to be changed, as e.g. is indicated in table IV
In table IV it is also to be seen that the normal sequence of the bit-couple selection is interrupted and has been resetted over one bit-couple to the next previous rolling point (namely 2), which is signalized by the output signal C₂ = 1. Reference is made to the following discussio of the data-unit 30.
Table V shows the program of the programmable logic unit 33. Particular features of the unit 33 are: 9 outputs, 17 inputs, 4 product terms.
Now follows a discussion of the data-unit 30 forming part of the curves-generator according to fig. 14. This unit 30 comprises a Dx-register 43 and a Dy-register 44 of which the nine bit-couples with controllable buffers can be selected and transmitted to the input/output 31 drawn in detail in fig. 11. Further a comparator-module 34 is present serving for generating the important input-variables C₀ → C₇ for the programmable unit 33. The schematic diagram of this comparator-module 34 is drawn in detail in fig. 16. This comparator-module 34 serves for comparing the bit-couples from the registers 43 and 44 with the respective bit-couples from two numbers F (x,y,z,) and G (x,y,z,) which will be discussed in more detail with reference to the explanation of the input/ output unit 31. Only the 8 most significant bit-couples of ((Dx, Dy) and (F(x,y,z,), G(x,y,z,)) are compared and give raise to the forming of a vector C consisting of the signals C₀ C₇. A signal C _{i =} 0 if Dx_i = F_i and simultaneously Dy_i = G_i; a signal C_. = 1, if Dx_i ≠ F_i or Dy_i = G_i. For every i from the value 0 through the value 7 this rule is embodied in the scheme according to fig. 16 with two exclusive-OR- gates and one OR-gate, which in the fig. are not specified.
Also the attention is drawn to the fact that the mentioned Dx- and Dy-registers 43, 44 can be loaded with (F(x,y,z,) and (G(x,y,z,) respectively, not only at the beginning of a generation cycle but now also during each clock-period, namely on a moment after comparing the bit-couples Dx_i, Dy_i and F., G_i.
Now a discussion follows of the input/output unit 31 This unit comprises to 9-bits up/downcounters 45, 46 which score the absolute x- y- values, as is the case in the circuit according to fig. 12. Control signals are at one hand formed by the selected bit-couple and at the other hand by the direction-couple.
The up/down counters 46, 47 are obviously also loadable with a initial position (x^(0), y⁽⁰⁾) by means of the inputs 47, 48, respectively. At any moment the absolute position (x ,y) can be delivered through the x-output 49 and the y-output 50.
Through these outputs 49, 50 the absolute x, y-position is, together with a third value, memorized in a z-register 51, loadable through a loading input 52, applied to a calculating unit 53, which is adapted to transform the number x, y and z (each comprising 9 bits) to two numbers of 9 bits F (x,y,z,) and G (x,y,z,), which are available on the lines indicated with 54, 55. The function to be performed by the calculating unit 53 can be adjusted through control inputs 56. These functions can be e.g.:
or:
It is in this respect recalled that the general form of the difference equation is :
In the most frequently occuring practical cases the calculating unit 53 transforms information from the registers x,y,z to the registers F, G. The z-register 51 forms the connection with other simular modules in solving difference equations of higher orders.
For the calculation of arbitrary functions F(x,y,z) and G (x,y,z) also a similar module can be provided.
The input/output unit 31 further comprises an interpretation module 89 in which a bit-couple applied to two inputs 90, 91 is combined with a direction-couple applied through two inputs 92, 93 to form control signals for the up/down counter 45, 46.
Fig. 18 shows a schematic diagram of a universal curves generator. Three main blocks 101, 102, 103 can be distinguished. The first part 101 serves for controlling and contains condition-counters 104 and the priorty- logic 105. The second part 102 of the data-part contains the differential registers DX, DY, DZ ... 106 and the bits-groupselectors 107. The third part 103 serves for input/output, namely the programming of the differential-relations 108 F,G,H.... and the solution- counters 109 X, Y, Z, ...The whole system is synchronously clocked.
The processor is controlled by a typically sequential machine having memory-elements and combinatorial logics, external inputs and external outputs.
The new condition (a) is determined by the old condition (b),the old differential-registers DX, DY, DZ... (c) and the differential-relations F, G, H, ... (d). Each moment a new rolling-point is being selected, DX, DY, DZ, ... are being evaluated by F, G, H, ... The priority logics generate the index i of the bits-group (e) to be selected. In order to obtain a generation by "rolling off" of the curve, the fitting-bits-groups (f) are fed into the binary counters X, Y, Z, ... which are clocked into that direction, that is determined by SX, SY, SZ, ... (g).
After each clock cycle a new point of the curve is formed in the counters X, Y, Z, .. (h). These counters by the way are loadable with the initial conditions (j) The differential-relations are programmed by means of function-keys (k).
A prototype of the present processor is developed. It is a curves generator including three differential-relations and consists of about 40 SSI and MSI TTL IC's (nc arithmetic modules). As a grafical processor the module generates 2,5 x 10 points per second ( a new X,Y,Z, each 400 ns) which is directly written into a video - memory and read out to be presented on a TV-monitor.
Reference is now made to the figures 19 and 20, and 21 or a discussion of a transformationsystem according to the invention. A three dimensional points-grid X,Y,Z is taken as a base, the coordinates of said grid being the integers running from 0 through N. A curve in said points grid can be described by elementary displacement-bits (DX., DY_., DZ_i) and direction-bits (SX, SY, SZ). The displacement-bits indicate, whether the curve displaces according to the related coordinate axis in the direction indicated by the direction-bits. This elementary dis- placemnets can e.g. correspond with the output signals of the system described in the foregoing, for generating digital signals corresponding to selectable functions or "function-generator". They also can be directly based an other relative code (relative i.e.: from point to point) of a curve or a contour (e.g. Freeman-code).
Mathematically a transformation of the present type can be formulated in terms of matrix-multiplication, in which from a starting vector (X₀, Y₀, Z₀) by multiplication with a transformationmatrix a transformed vector (X , Y , Z ) is determined:
For instance for a certain two-dimensional dilatation transformation the following relation holds:
For a neighbour point can be written similarly:
from which immediately the relation for the new displace- ^{ments + dX} _., ⁺ dY_i, ± dZ_i follows:
As DX_i, DY_i, DZ_i can only have the values 0 or 1 it is clear the the new displacements can only be accumulations of the matrix-elements a.. and that the 64 (=₂ ^2x3, in which the number 3 corresponds with the dimension of the space) involved possible configurations is determined by at one side SX, SY, SZ and at the other side DX., DY_i, DZ_i.
Tnus according to the invention it is possible to avoid the nine multiplications, which are normally necessary, through ordinary accumulations. Further no systematic errors can occur. Thus a closed contour remains closed, even after transformation.
Fig. 19 shows and E and O, respectively, as to examples of letter-symbols which can in a word-processor be described with a single contour and a combination of an inner contour and an outer contour, respectively,
Fig. 20a shows a square as an example of an original curve to be transformed by the transformationsystem according to the invention.
The figures 20b through 20d are drawn on the same scale. It will, therefore, be clear, that the figures 20b, 20c, 20d respectively, correspond with a transformation consisting from a rescaling, a dilatation a rescaling combined with rotation, respectively, in which the several rescalings differ for the two independent directions.
Fig. 21 shows a very simplified block-schematic diagram of system according to the invention. This system comprises a memory block 110, the inputs of which are connected with the inputs of a block of adding registers 111.
The addresses for the memory block 110 are fed thereto through address inputs 112 and consist of the displacement-bits DX., DY_i, DZ. and the direction bits-SX, SY, SZ.
The below table shows the 64 data-words having orders 0 through 63, which are stored in 64 memory-positions of the memory-block together with the 64 potential addresses in the form of the potential combinations of the direction-bits.It will be appreciated that each address- word is uniqually related with one data-word and that the 64 data-words comprise all possibilities.
The read-out new displacements in the form of the data + dX_i, dY_i, dZ_i are continiously accumulated by the adding registers 111. The carry-bits DX_j, DY_j, DZ_j generated thereby form the new elementary displacement-bits. It will be clear now that also the direction-bits for these new displacements originate from the memory block 110.
It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of this invention.

Claims

1. A system for generating digital signals corresponding to functions of a selectable number of variables, said functions corresponding to a selectable analytical relation and being of the type that can be described in a descrete form by a differential-relation or a simultaneous system of differential-relations and at least one boundary-condition or initial condition, characterized by

₁) a signal generator for forming binary signals for each of said two variables, said signals being representative for said differential-relation(s) and said at least one boundary-condition or initial-condition for each of the variables;

2) comparing means for successively comparing, in the direction from the most significant bit (MSB) to the least significant bit (LSB), bits of equal significance of said signals, each of which corresponds to one variable;

3) rolling-point determining means for determining a rolling-point on basis of at least one of said comparing operations, said rolling-point being a point determined by the values of said variables and relative to which a preceding part of said function, considered to be graphically displayed in an orthogonal coordinate-system, is rolled over 180° so as to obtain a next part of said function connected to said preceding part; and

4) memory-means for memorizing signals corresponding to at least said last-mentioned next part of said function in the form of bits-groups.

2. System as claimed in claim 1, characterized by second comparing means for, after forming a new part of said function, successively comparing, in the direction from the least significant bit (LSB) to the most significant bit (MSB), bits of equal significance of said signals each corresponding to one variable, the output signals of said second comparing means in case of detection of the first unchanged bits-groups being fed to said rolling-point determining means for changing a previously determined rolling-point.

3. A system as claimed in anyone of claims 1 and 2, for subjecting selectable curves, e.g. letter- or cipher- symbols, that can be described by one or more closed contours, to selectable transformations, said system comprising:

(1) addressable first memory-means having a number of memory positions, in each of which a data-word consisting of a linear combination with the multiplication factors 0,+1 or -1 of the elements (a_..) of the matrix representing a selected transformation is stored, said data-words forming a complete set;

(2) second memory-means for storing the coordinate data of a selected curve according to a discreet points-grid;

(3) computing means connected with the outputs of said first and second memory-means for computing by means of matrix multiplication of successive points of the transformed curve,

a displacement in one dimension over one elementary grid distance being represented by a displacement bit (DX_i, DY_i, DZ_i, ... ) and a direction bit (SX, XY, S_Z, ..), said displacement bit indicating whether or not said curve displaces according to the coordinate axis involved in the direction indicated by said direction-bit.

The possible address-words for said first memory-means consisting of the complete set of combinations of displacement bits and direction-bits.

4. The system as claimed in claimed 3, in which said calculating me s have the form of adding registers for accumulating data-words representing new displacements, while the carry-bits generated thereby form the new displacement-bits and direction-bits representing a next point.