EP0022870B1

EP0022870B1 - Semiconductor circuit

Info

Publication number: EP0022870B1
Application number: EP79901379A
Authority: EP
Inventors: Jun-Ichi Mogi; Kiyoshi Miyasaka; Seiji Enomoto; Shigeki Nozaki
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 1978-10-30
Filing date: 1980-05-20
Publication date: 1983-06-08
Also published as: JPS5559756A; EP0022870A4; US4430581A; EP0022870A1; WO1980001021A1; DE2965630D1; JPS5644570B2

Abstract

Semiconductor circuit including a dynamic circuit and a bias voltage generating circuit. The bias voltage generating circuit comprises first and second bias voltage generating circuits (30) and (30'). The former circuit (30) absorbs variable substrate current having a value which is in proportion to an operating frequency of the dynamic circuit while the latter circuit (30') absorbs the substrate current having values which are not in proportion to the operating frequency of the dynamic circuit.

Description

the present invention relates to a semiconductor circuit according to the first part of claim 1, Such a circuit is known from US-A-3 806 741.

Background art

Generally, the MOS integrated circuit is provided with a bias-voltage generator so as to establish and maintain the desired optimum circuit operation of each of the semiconductor devices, such as FETs (Field Effect Transistors), which constitute the MOS integrated circuit. For instance, if the threshold voltage is below a specified or nominal level, the semiconductor device is unstable in operation, as it may be improperly rendered conductive by a noise signal, and is thus particularly unsuitable for use in logic circuits. Contrary to the above, if the threshold voltage is greater than the desired level, the speed of the operation of the semiconductor device is reduced, and the semiconductor device may fail to be turned on when an input signal is applied to the control electrode. Thus, the level of the threshold voltage must be maintained at a desired optimum level. The maintenance of the level of the threshold voltage at a desired optimum level is achieved by the bias-voltage generator which has a function to absorb the so-called substrate current (l_BB) which flows across the substrate.
In view of the operation thereof, the MOS integrated circuit is generally classified into two types of circuits: firstly a static-type circuit and; secondly a dynamic-type circuit. In the static-type circuit, for example a static-type storage device, there is no limit with respect to the operating frequency. This is because such a static-type storage device operates not based on the stray capacitors accommodated therein, but on a static current supplied from a power supply. While in the dynamic-type circuit, for example a dynamic-type storage device, there is a lower limit with respect to the operating frequency. This is because such a dynamic-type storage device is operated by using electric charges stored in the stray capacitor, which electric charges are discharged therefrom with some RC time constant. Generally, in the former static-type circuit, since this circuit is operated by using said static current, the magnitude of said substrate current does not vary and is held at a constant level. While in the latter dynamic-type circuit, since this circuit is operated by using said electric charges stored in the stray capacitor, the magnitude of the substrate current (I_BB) varies in proportion to the operating frequency thereof. That is, when the operating frequency becomes low, the magnitude of the current (l_BB) is caused to be low. Contrary to this, when the operating frequency becomes high, the magnitude of the current (l_BB) is caused to be high. Thus, since the operating frequency usually varies within a wide range of frequencies, the bias-voltage generator must be designed so as to have a capability for absorbing the substrate current (I_BB) having a maximum allowed magnitude level, which current (I_BB) will flow at a time when the circuit operates with the highest operating frequency. Therefore, such a bias-voltage generator always consumes considerably high power, even though the circuit operates with a relatively low operating frequency. This fact is the shortcoming of a typical bias-voltage generator.
For the purpose of overcoming the above mentioned shortcoming, an improved bias-voltage generator has been proposed in, for example the U.S. Patent No. 3,806,741, entitled Self-Biasing Technique for MOS Substrate Voltage, by Frederick J. Smith. In the improved bias-voltage generator, this bias-voltage generator can absorb the substrate current (l_BB) in such a manner that the magnitude thereof varies in accordance with the variation of the operating frequency of the dynamic-type circuit. In other words, the magnitude of the current (I_BB) always matches the operating frequency, thereby the aforesaid shortcoming of the typical bias-voltage generator can be overcome.
However, the improved bias-voltage generator has a disadvantage in that this bias-voltage generator cannot absorb the full substrate current (I_BB) at a time when the dynamic-type circuit operates with a very low operating frequency, due to the presence of the so-called junction leak current, the magnitude thereof is not proportional to the variation of the operating frequency. In other words, since the bias-voltage generator functions to absorb merely the substrate current (I_BB) having a very low magnitude at a time when the operating frequency is considerably low, this bias-voltage generator cannot absorb the junction leak current, because the magnitude of the junction leak current is higher than the magnitude of the substrate current (lBB) to be absorbed by this bias-voltage generator.

Disclosure of invention

An object of the present invention as claimed is, therefore, to provide a semiconductor system being provided with a dynamic-type circuit and a bias-voltage generator, which bias-voltage generator does not create the aforementioned disadvantage of the prior improved bias-voltage generator.

Brief description of drawing

Fig. 1 is a plan view of an example of a typical semiconductor device;
Fig. 2 is a schematic cross-sectional view of a bias-voltage generator, according to the present invention, taken along the line A-A shown in Fig. 1;
Fig. 3 illustrates an equivalent circuit diagram for devices shown in Fig. 2;
Fig. 4 is a graph representing a relationship between a substrate current (l_BB) and a reciprocal value of an operating frequency (i/f);
Fig. 5 depicts waveforms of signals developed at major portions in the circuit shown in Fig. 3;
Fig. 6 illustrates one example of an oscillator 31 shown in Fig. 3, and;
Fig. 7 illustrates one example of an oscillator 31' shown in Fig. 3.

Best mode for carrying out the invention

In Fig. 1, which is a plan view of an example of a typical semiconductor system, a dynamic-type storage device is illustrated as an example of the dynamic-type circuit. The storage device is comprised of left memory cell area 11-L, right memory cell area 11-R, a word decoder (DEC) 12, a left column decoder 13-L, a right column decoder 13-R, a left sense amplifier (S/A) 14-L and a right sense amplifier 14-R. The storage device further cooperates with both a left periphery circuit 1 5-L and a right periphery circuit 15-R. Many input/output pads 16 (16') are mounted on a substrate 10 at both sides thereof. Each function of the above members is already well known by persons skilled in the art. The reference numeral 17 represents a bias-voltage generator to which the present invention is specifically directed.
The bias-voltage generator 17, according to the present invention, is illustrated in Fig. 2 which is a schematic cross-sectional view taken along the line A-A shown in Fig. 1. The equivalent circuit diagram for the devices shown in Fig. 2, is illustrated in Fig. 3. In both Figs. 2 and 3, the members represented by the same reference numerals or symbols are identical with each other. The reference numeral 20 indicates a P-type substrate. A plurality of N-type regions 21-1 through 21-6 are formed in the P-type substrate 20. On the substrate 20, gate electrodes 23-1 through 23-4 are formed, respectively on gate insulators 22-1 through 22-4. Therefore, an FET 34' (also shown in Fig. 3) is composed of the N-region 21-1 (source), the N-region 21-2 (drain), the insulator 22-1 and the electrode 23-1. An FET 35' (also shown in Fig. 3) is composed of the N-region 21-2 (drain), which is common to the FET 34', the N-region 21-3 (source), the insulator 22-2 and the electrode 23-2. In a similar manner, FETs 34 and 35 are composed of the corresponding members 21-4 through 21-6, 22-3, 22-4, 23-3 and 23-4. The reference numeral 31 represents an oscillator which produces a pulse train having a frequency being in proportion to the operating frequency of the dynamic-type circuit, such as the storage device shown in Fig. 1. The reference numeral 31' represents an oscillator which produces a pulse train having a predetermined constant frequency. The word "constant" denotes that the oscillating frequency is not proportional to the operating frequency. The reference numerals 32 and 32' represent capacitors, respectively (shown in both Figs. 2 and 3). The reference numerals 33 and 33' represent the stray capacitors (not specifically shown in Fig. 2). The stray capacitors 33 and 33' are formed at, for example, each junction of the N-type regions and the P-type substrate shown in Fig. 2. The reference numerals 36 and 36' represent quasi diodes (not specifically shown in Fig. 2). The diodes 36 and 36' are inevitably created, respectively, at the respective junctions of the N-type regions and P-type substrate defining the FETs 35 and 35' shown in Fig. 2. The reference numeral 37 of Fig. 3 represents a quasi bulk resistor existing across the substrate 20 between a conductive stage 24 and the N-type region 21-1 and also between the conductive stage 24 and the N-type region 21-6 shown in Fig. 2. The reference numeral 38 of Fig. 3 represents a quasi diode existing between the N-type region 21-1 and the P-type substrate 20 and also between the N-type region 21-6 and the P-type substrate 20.
The operational principle of the bias-voltage generator according to the present invention will be clarified with reference to Fig. 4. In Fig. 4, which is a graph representing a relationship between the substrate current (I_BB) and a reciprocal value of the operating frequency (I/f), the abscissa indicates the reciprocal value of the operating frequency (I/f) and the ordinate indicates the value of the substrate current (I_BB). As previously mentioned, in the prior improved bias-voltage generator, the magnitude of the substrate current (I_BB) varies in accordance with the variation of the operating frequency (f) of the dynamic-type circuit. Consequently, the substrate current (I_BB) to be absorbed by such a bias-voltage generator, varies along a curve (41, 41') with respect to the variation of (I/f). However, such a bias-voltage generator does not take into account the presence of the aforesaid junction leak current. The magnitude level of this junction leak current is non-changeable with respect to the variation of the operating frequency (f), as is represented by a straight line (42, 42'). The junction leak current flows across each junction of the N-type regions 21-1 through 21-6 and the P-type substrate 20 (see Fig. 2). As a result, the prior improved bias-voltage generator cannot absorb the substrate current (l_BB) which corresponds to the difference in value between the current (42) and the current (41'). Consequently, the voltage potential of the substrate will deviate from the desired optimum voltage potential due to the accumulation of the substrate current which has not been absorbed by the bias-voltage generator. Accordingly, the threshold voltage cannot be maintained at the desired optimum level.
For the purpose of eliminating the aforementioned disadvantage of the prior improved bias-voltage generator, the bias-voltage generator of the present invention functions to absorb the substrate current (I_BB) along the curve 41 and the line 42. That is, when the dynamic-type circuit works with the operating frequency (f,) which is higher than a critical operating frequency (f_c), the bias-voltage generator absorbs the substrate current (41), the magnitude of which varies in accordance with the variation of the operating frequency (f_v). Contrary to this, when the dynamic-type circuit works with the operating frequency which is lower than the critical operating frequency (f_e), the bias-voltage generator absorbs the substrate current (42) which corresponds to the junction leak current. As a result, the bias-voltage generator of the present invention can always absorb the value of the substrate current (I_BB), so that the voltage potential of the substrate does not deviate from the desired optimum potential.
Returning to Fig. 3, the bias-voltage generator of the present invention is divided into two parties: firstly, a variable bias-voltage generator 30 and; a constant bias-voltage generator 30'. The former generator 30 is comprised of the aforesaid members 31 through 36 and the latter generator 30' is comprised of the aforesaid members 31' through 36'. The generator 30 functions to absorb the variable substrate current (I_BB) (corresponding to the curve (41) shown in Fig. 4) and the generator 30' functions to absorb the constant substrate current (I_BB) (correspondng to the line (42) shown in Fig. 4). In order to perform the function for obtaining the curve (41), the generator 30 includes the variable oscillator 31 which receives a control signal S(f_v) and produces an output pulse train having the frequency f_v being in proportion to the frequency of the signal S(f_v). This frequency f_v is equal to or proportional to the operating frequency of the dynamic-type circuit, such as the storage device shown in Fig. 1. Contrary to the above, in order to perform the function for obtaining the line (42), the generator 30' includes the constant oscillator 31' which produces an output pulse train having the constant frequency f_c.
The operation of each of the bias-voltage generators is as follows. It should be noted that the generators 30 and 30' have the same circuit construction, and therefore, the following explanation of the operation is effected with regard only to the generator 30' with reference to Fig. 5. Fig. 5 depicts waveforms of signals developed at major portions in the circuit of Fig. 3. The waveform of the output signal from the oscillator 30' is illustrated on row a) of Fig. 5. This output signal P has the constant frequency f_c. In a period ①, the voltage level of the output signal P changes from a voltage V_ss, to a voltage V_cc. The voltage V_ss is the same as the voltage developed at the external ground point represented by the ground symbols shown in Figs. 2 and 3. At the rising edge of the signal P in the period ①, the voltage level at a portion Ⓐ (shown in Figs. 2 and 3) rises quickly due to the presence of the capacitor 32' (see row b) of Fig. 5). Thereafter, the voltage level at the portion Ⓐ gradually decreases to a threshold voltage level V_t. This is because, since the voltage level at portion Ⓐ exceeds the threshold voltage level V_t, the FET 34' is caused to be conductive and the charges stored at the capacitor 32' are discharged to the ground (V_ss) via the FET 34' which is now conductive. Next, on row b) of Fig. 5, at the falling edge of the signal P in the period ①, the voltage level at the portion Ⓐ quickly falls down toward a voltage level V_o which is equal to
where the symbols C₃₂, and C₃₃, denote the capacitance values of the cacitors 32' and 33', respectively.
In this case, the quasi diode 36' becomes conductive and the substrate current (I_BB) flows from the substrate at a portion Ⓑ (see Figs. 2 and 3) to the capacitor 32' and the stray capacitor 33', via the diode 36'. Since the diode 36' has its own threshold voltage, for example 0.6V, it is preferable to form a bypassing root of the diode 36'. In Figs. 2 and 3, the bypassing root is comprised of the FET 35' which has a threshold voltage of about 0V. Thus, the so-called diode clamp is performed during a period ②. It should be understood that the portion Ⓑ may further be connected to the conductive stage 24 shown in Fig. 2. In this period ② the charges that is the substrate current (I_BB), are absorbed from the substrate at the portion Ⓑ, toward the capacitors 32' and 33', the amount of which charges Q is expressed by the equation, that is
where the symbol V_BB denotes a substrate biasing voltage. At the rising edge of the signal P in a period ③ (see Fig. 5), the voltage level at the portion Ⓑ quickly rises again. At the same time, the FET 34' becomes conductive again and said charges Q are discharged to the external ground point (V_ss) via the FET 34'. Thus, the charges Q, that is the substrate current (I_BB), are pumped out from the substrate by means of the bias-voltage generator 30' every time the rising edge of the output signal P appears. Since the output signal P has the constant frequency f_c subject to the constant oscillator 31', the constant substrate current (I_BB) (see the line (42) in Fig. 4) is absorbed by the generator 30'.
Regarding the bias-voltage generator 30 of Fig. 3, since the generator 30 is driven by the variable oscillator 31 which oscillates in proportion to the operating frequency f_v of the dynamic-type circuit, if when the dynamic-type circuit works with a relatively high operating frequency, for example f_h shown In Fig. 4, the magnitude of the substrate current (I_BB) becomes relatively high, such as a level I_h shown in Fig. 4, because the number of the aforesaid pumping out operations is relatively large and a relatively large amount of the charges Q are absorbed. If the dynamic-type circuit works with relatively low operating frequency, for example f, shown in Fig. 4, the magnitude of the substrate current (I_BB) becomes relatively low such as a level 1₁ shown in the same Fig. 4, because the number of the pumping out operations is relatively small and a relatively small amount of the charges Q are absorbed.
The operating frequency f_" of the dynamic-type circuit is defined by an external timing clock signal with is usually applied to, for example the input/output pad 16' shown in Fig. 1. Therefore, in this example, the input of the variable oscillator 31 of Fig. 3 may be connected to the pad 16'. One example of the oscillator 31 is illustrated in Fig. 6. In Fig. 6, the oscillator 31 is comprised of a pair of an FET 61 and an FET 62. The FET 61 is connected to the power supply (V_cc). The FET 62 receives the control signal S(fy) shown in Fig. 3. The connection between the FETs 61 and 62 leads to the capacitor 32 shown in Fig. 3. The oscillator 31 shown in Fig. 6 may also be named as a conventional level converter.
One example of the oscillator 31' is illustrated in Fig. 7. The oscillator 31' is comprised of a plurality of load FETs 71-1 through 71-5 which are commonly connected at respective gates and the same number of FETs 72-1 through 72-5. The number of pairs of the FETs must be an odd number, for example five as shown in this Fig. 7. The output of the last stage (71-5, 72-5) is, on one hand, connected to, via a buffer means 73, the capacitor 32' shown in Fig. 3 and, on the other hand, to the input of the initial stage (71-1, 72-1) via a feedback loop 74. The output of each stage is connected to the input gate of the next stage.
As mentioned above, a semiconductor device which always has an optimum threshold voltage irrespective of the variation of the operating frequency thereof can be realized.

Table of reference numerals and parts

Claims

1. A semiconductor circuit comprising a dynamic-type circuit mounted with a bias voltage generating circuit on the same semiconductor substrate, the bias voltage generating circuit maintaining the bias of the substrate at a desired optimum level by absorbing substrate current, characterised in that the said bias voltage generating circuit is comprised of a first oscillator (31) producing a first pulse train, the frequency (fv) of which is proportional to the operating frequency of the dynamic-type circuit, a second oscillator (31') producing a second pulse train, the frequency (fc) of which is independent of the operating frequency of the dynamic-type circuit, and a means for absorbing from the substrate, in synchronism with the first pulse train, a first part of the substrate current which is proportional to the operating frequency of the dynamic-type circuit and, in addition, for absorbing from the substrate, in synchronism with the second pulse train, a second part of the substrate current which is independent of the operating frequency of the dynamic-type circuit.

2. A semiconductor circuit as set forth in claim 1, wherein the second part of the substrate current corresponds to the junction leak current appearing inside the substrate, and the second pulse train has a frequency adapted to cause the absorbtion of a current corresponding to the junction leak current.

3. A semiconductor circuit as set forth in claim 1 or 2, wherein the first oscillator (31) is activated by a timing clock signal which is to be applied to the dynamic-type circuit, and the second oscillator (31') is free running.

4. A semiconductor circuit as set forth in claim 1, wherein the absorbing means is comprised of a first circuit (32-36) for absorbing the first part of the substrate current and a second circuit (32'-36') for absorbing the second part of the substrate current.

5. A semiconductor circuit as set forth in claim 4, wherein each of the said first and second circuits is comprised of at least a first capacitor (32) directly connected to the respective oscillator, a quasi diode (36) for leading the substrate current to a second capacitor (33) directly connected at one end to an external ground point (V_ss), an outlet portion (@) through which the substrate current flows, and an FET (34) the gate of which is connected to the second capacitor and one terminal of which is connected to the external ground point (Vg_s), charges of the substrate current which have been stored at some period in the second capacitor being discharged in the next period via the FET (34) when the FET becomes conductive.

6. A semiconductor circuit as set forth in claim 5, wherein another FET (35) is connected in parallel to the quasi diode (36).

7. A semiconductor circuit as set forth in claim 5 or 6, wherein the outlet portion (@) is formed on the top surface of the substrate.

8. A semiconductor circuit as set forth in claim 5 or 6, wherein the outlet portion (CBI) is formed on the bottom surface of the substrate at a conductive stage.