EP0020244B1 - Verfahren und Vorrichtung zum Adressieren eines Bildwiederholungsspeichers in einem Teletext-System - Google Patents
Verfahren und Vorrichtung zum Adressieren eines Bildwiederholungsspeichers in einem Teletext-System Download PDFInfo
- Publication number
- EP0020244B1 EP0020244B1 EP80400711A EP80400711A EP0020244B1 EP 0020244 B1 EP0020244 B1 EP 0020244B1 EP 80400711 A EP80400711 A EP 80400711A EP 80400711 A EP80400711 A EP 80400711A EP 0020244 B1 EP0020244 B1 EP 0020244B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- ebs
- row
- memory
- adr1
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
- G09G5/30—Control of display attribute
Definitions
- the invention also relates to a device for addressing an image memory, comprising a counter delivering a sequence of 5 binary elements (ebs) in parallel ADR1 to ADR5 to provide the addresses stored, a counter delivering a sequence of 6 ebs in parallel ADC1 to ADC6 to provide the column addresses, and a transcoding circuit which corresponds to a pair of a row address between 0 and 24 and a column address between 0 and 39 a character address between 0 and 999, which is transmitted to the memory in the form of a sequence of 10 ebs in parallel A o to A 9 , characterized in that the transcoding circuit transmits to the image memory the address row ADR1 to ADR5 unchanged when it receives a column address worth at least 40.
- ebs binary elements
- the transmission of the addresses stored with a column address of at least 40 provides the read addresses for the positions 1000 to 1023 remaining available in the image memory.
- the transcoding circuit comprises a transcoding memory to which are applied the ebs ADR1 to ADR5 transmitting the row address and the three ebs ADC4 to ADC6 of high weight, the three ebs ADC1 to ADC3 being transmitted directly at 1 has image memory.
- a page is formed of 25 rows of 40 characters and therefore includes 1000 characters.
- the addressing device comprises a row counter 2 capable of delivering 5 binary elements ADR1 to ADR5 in parallel representing the numbers 0 to 31 and a column counter 3 which can deliver 6 binary elements ADC1 to ADC6 representing the numbers 0 to 63.
- the column counter 3 is incremented by a clock 10 defining the character time interval, equal to 10 image points in the ANTIOPE system, ie approximately 1 ⁇ s, and it is reset at each line synchronization top TLG, ie every 64 ⁇ s.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Television Systems (AREA)
- Controls And Circuits For Display Device (AREA)
- Transforming Electric Information Into Light Information (AREA)
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7913240A FR2463453A1 (fr) | 1979-05-23 | 1979-05-23 | Procede et dispositif pour l'adressage d'une memoire d'image dans un systeme de teletexte |
FR7913240 | 1979-05-23 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0020244A2 EP0020244A2 (de) | 1980-12-10 |
EP0020244A3 EP0020244A3 (en) | 1981-02-11 |
EP0020244B1 true EP0020244B1 (de) | 1983-05-04 |
Family
ID=9225830
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP80400711A Expired EP0020244B1 (de) | 1979-05-23 | 1980-05-21 | Verfahren und Vorrichtung zum Adressieren eines Bildwiederholungsspeichers in einem Teletext-System |
Country Status (8)
Country | Link |
---|---|
US (1) | US4315257A (de) |
EP (1) | EP0020244B1 (de) |
JP (1) | JPS55161485A (de) |
CA (1) | CA1162293A (de) |
DE (1) | DE3062949D1 (de) |
ES (1) | ES8104597A1 (de) |
FR (1) | FR2463453A1 (de) |
SU (1) | SU1048996A3 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
HU180133B (en) * | 1980-05-07 | 1983-02-28 | Szamitastech Koord | Equipment for displaying and storing tv picture information by means of useiof a computer access memory |
US4388645A (en) * | 1981-04-13 | 1983-06-14 | Zenith Radio Corporation | Teletext communication system with timed multipage local memory |
JPS5836089A (ja) * | 1981-08-27 | 1983-03-02 | Sony Corp | 画像表示装置 |
US4740912A (en) * | 1982-08-02 | 1988-04-26 | Whitaker Ranald O | Quinews-electronic replacement for the newspaper |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3659283A (en) * | 1969-05-09 | 1972-04-25 | Applied Digital Data Syst | Variable size character raster display |
US3911418A (en) * | 1969-10-08 | 1975-10-07 | Matsushita Electric Ind Co Ltd | Method and apparatus for independent color control of alphanumeric display and background therefor |
US3685038A (en) * | 1970-03-23 | 1972-08-15 | Viatron Computer Systems Corp | Video data color display system |
US3794970A (en) * | 1972-11-24 | 1974-02-26 | Ibm | Storage access apparatus |
JPS50120922A (de) * | 1974-03-11 | 1975-09-22 | ||
US3955189A (en) * | 1974-07-24 | 1976-05-04 | Lear Siegler | Data display terminal having data storage and transfer apparatus employing matrix notation addressing |
JPS51101424A (en) * | 1975-03-04 | 1976-09-07 | Hitachi Ltd | Deisupureisochino seigyohoshiki |
GB1515309A (en) * | 1975-09-25 | 1978-06-21 | Mullard Ltd | Character display |
IT1084020B (it) * | 1976-03-15 | 1985-05-25 | Sperry Rand Corp | Decodificatore degli indirizzi di una memoria |
US4190835A (en) * | 1976-09-22 | 1980-02-26 | U.S. Philips Corporation | Editing display system with dual cursors |
US4117470A (en) * | 1976-10-08 | 1978-09-26 | Data General Corporation | Data bit compression system |
JPS5399826A (en) * | 1977-02-14 | 1978-08-31 | Hitachi Ltd | Controller for data display |
-
1979
- 1979-05-23 FR FR7913240A patent/FR2463453A1/fr active Granted
-
1980
- 1980-05-20 ES ES491634A patent/ES8104597A1/es not_active Expired
- 1980-05-21 EP EP80400711A patent/EP0020244B1/de not_active Expired
- 1980-05-21 DE DE8080400711T patent/DE3062949D1/de not_active Expired
- 1980-05-22 US US06/152,497 patent/US4315257A/en not_active Expired - Lifetime
- 1980-05-22 CA CA000352524A patent/CA1162293A/en not_active Expired
- 1980-05-22 SU SU802929204A patent/SU1048996A3/ru active
- 1980-05-23 JP JP6797380A patent/JPS55161485A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
EP0020244A2 (de) | 1980-12-10 |
EP0020244A3 (en) | 1981-02-11 |
ES491634A0 (es) | 1981-04-01 |
DE3062949D1 (en) | 1983-06-09 |
CA1162293A (en) | 1984-02-14 |
JPS55161485A (en) | 1980-12-16 |
SU1048996A3 (ru) | 1983-10-15 |
US4315257A (en) | 1982-02-09 |
FR2463453B1 (de) | 1985-02-15 |
FR2463453A1 (fr) | 1981-02-20 |
ES8104597A1 (es) | 1981-04-01 |
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