EP0011576A1 - Polyphonic synthesizer of periodical signals using digital techniques - Google Patents

Abstract

The invention relates to a polyphonic musical synthesizer using digital techniques. The generation of the successive waveform samples uses phase data for addressing a memory (11) of waveform, amplitude, octave rank or harmonics contained in a set of memory blocks (1). The synthesizer is controlled by the external addressing of all of the memories to write the aforementioned data there. The progress of the synthesis operations inside the synthesizer is conditioned by a sequential sequence of the reading of the different memory blocks, according to the signals of a plurality of the generators.

Description

The present invention relates to a polyphonic synthesizer of periodic signals, using digital techniques and more generally electronic, polyphonic musical instruments comprising one or more of such a synthesizer.

A synthesizer of this kind has been described in patent application No. 77 202 45 filed on July 1, 1977 (FRANCE).

Each periodic signal results from a succession of digital samples produced in particular from a memory of waveform samples, read at variable frequency, and then converted into an analog form.

Unlike other musical synthesis devices also using digital techniques, in which the waveform samples are read from the sample memory at a fixed single frequency, but at a variable phase interval (depending on the final frequency at get). the present invention relates to a synthesizer in which the samples are read at variable frequency, from several pulse signals produced by generators included in the synthesizer.

Such a structure lends itself better to the realization of a complementary synthesizer independent of the rest of the musical instrument, and which can be fairly controlled by microprocesse

The synthesizer behaves like a set of independent signal generators controlled from a set of memories which each contain at least the amplitude of an output signal. The synthesizer performs, in 1 s _an t each memory, a digital-analog conversion, to convert the amplitude data read and an instantaneous phase value, into an analog, positive or negative, voltage or current step.

In the first synthesizer mentioned above, all the periodic signals which it can produce are generated cyclically and continuously, even if the amplitudes of most are zero, because the control circuits of the synthesizer, actuated by the impulse generators included, control a digital-analog conversion for each datum in the memory set, whatever the value of this datum. So that a signal is not produced, it is then necessary to insert a datum equal to zero in the corresponding memory.

Most of the time the number of signals produced by the synthesizer is small compared to the maximum number of signals it can produce. This leads to the fact that, in the synthesizer, numerous logical conversion operations are carried out unnecessarily for signals which are ultimately not produced, and in the control microcomputer, operations for writing data of amplitude equal to zero are necessary, hence a double loss of time.

An object of the present invention is to eliminate this drawback by eliminating the synthesis of the signals not requested. Also, during operation, only the memories relating to the signals to be produced are used.

Another object of the present invention is to take advantage of the time savings achieved to allow the synthesis of additional signals or to increase the number of possible periodic signals.

The invention, as characterized in the claims, solves the problem of limiting the work of the synthesizer to the production of the only signals requested, by organizing the data in the control memories so that there is a sequence between those data. Only the significant data are included in this sequence. The reading of the data in the control memories, from the pulse generators and the production of the corresponding samples, therefore take place according to the determined sequence, which is executed repeatedly. The external operating means of the synthesizer can modify the sequence of data in the control memories at any time and replace it with a new sequence. They can also modify data used in the summary without changing the flow.

To carry out this sequence, each control memory must contain, in addition to the data used for the production of a sample, additional information which is read by the control means of the synthesizer and is used by them to determine the next memory in the sequence.

génerateur impulsionnels, chaque groupe contenant en outre une mémoire supplémentaire pour contenir un sous multiple commun de la phase instantanée de plusieurs signaux périodiques et chaque mémoire comportant une zone pour recevoir une information d'adressage d'une autre Mémoire du même groupe.According to a first alternative embodiment, all of the control memories are divided into memory groups res,

pulse generator, each group additionally containing an additional memory for containing a common submultiple of the instantaneous phase of several periodic signals and each memory comprising an area for receiving addressing information from another Memory of the same group.

It therefore appears that the internal control means of the synthesizer are only interested in the command memories linked together by the sequence, the other command memories not included in the sequence being ignored. The operations of the synthesizer are therefore limited to the production of the only periodic signals to be produced.

However, the fact that the control memory is divided into groups determined by construction, limits the number of elementary sound components associated with each generator to the number of memories of a group minus one. As all the groups are rarely all used together, a greater or lesser number of memories remain unused most of the time.

According to a second variant of the invention, the control memories of the synthesizer are no longer divided into groups, each memory being able to be assigned to any generator. Each memory includes addressing information from another memory, for carrying out the sequence. In addition, there are two types of memories of the main blocks essentially containing a submultiple of the instantaneous phase as with several signals and secondary blocks essentially containing the amplitude of these signals.

Of course, the information which can be recorded in the control memories is not limited _to that listed previously. This allows the lar ges possibilities for synthesizer commands by simple write operations in RAM.

The present invention provides a significant reduction in these writing operations due to the sequence. Likewise, the internal operations of the synthesizer are reduced.

Among the advantages of the invention, there may be mentioned the possibility of reducing the frequency of the clock which synchronizes all of the circuits, hence better possibilities for integrating these circuits in the form of integrated circuits.

Optimizing the read and convert operations also increases the design flexibility of the synthesizer. Thus the size of the memory groups can be modified to increase or decrease the number of possible signals, without increasing the complexity of the operation. Likewise, the number of generators and groups can vary, allowing the synthesis of new series of signals whose frequencies are not necessarily in relation to those of other generators. Thus, the frequencies of these generators can be variable or random.

Thanks to the second variant, the total processing time of the synthesizer operations is constantly reduced to a minimum and the use of the memories is optimal.

The reduction in processing time makes it possible to reduce the time difference between the change of state of a generator and the calculation of the samples of the corresponding sound components.

sororités élémentaires contenant un grand nombre de compositions- The removal of group limits allows

elementary sororities containing a big name bre of compositions

• La figure 1 représente le schéma d'un synthétiseur selon la première variante, la mémoire de commande étant divisée en groupes ; la figure 2 représente l'organisation des données à l'intérieur d'un groupe ; la figure 3 représente un organigramme expliquant le déroulement des opérations du synthétiseur ; la figure 4 montre un exemple de réalisation d'un convertisseur numérique-analogique ; la figure 5 représente un synthétiseur selon la seconde variante préférée de l'invention ; la figure 6 représente un organigramme de fonctionnement de cette seconde variante ; et la figure 7 représente un détail de réalisation de la logique de détection des transitions des générateurs.

Other characteristics and advantages of the present invention will appear in the description which follows, this being illustrated by the figures which represent:

• FIG. 1 represents the diagram of a synthesizer according to the first variant, the control memory being divided into groups; FIG. 2 represents the organization of the data within a group; Figure 3 shows a flowchart explaining the flow of synthesizer operations; FIG. 4 shows an exemplary embodiment of a digital-analog converter; FIG. 5 represents a synthesizer according to the second preferred variant of the invention; FIG. 6 represents an operating flow diagram of this second variant; and FIG. 7 represents a detail of implementation of the logic for detecting generator transitions.

In general, a digital musical synthesizer is built around a waveform memory containing a digital representation, point by point, of a period (or a portion of a period, if there are symmetries) d 'a periodic waveform. The input for addressing the memory receives so-called "phase" signals and the output delivers the data or signals of corresponding "amplitude". The waveform memory therefore transcodes a digital signal phase into a digital amplitude signal, which is then converted to analog form.

To reconstruct a complete periodic analog signal, digital phase signals must be applied successive to waveform memory. The latter then delivers successive amplitude signals applied to the digital-analog converter. These analog signals are filtered to eliminate quantization noise and the analog waveform is rendered.

Instead of a direct digital representation of the final waveform, the waveform memory may contain a differential representation of this waveform. Each numerical value represents the difference between the amplitude of the point considered of the waveform and that of the previous point. The digital to analog converter is then followed by an integrator which renders the final waveform. This type of synthesis has the advantage of allowing the use of digital information of reduced size (8-bit words for amplitude) without sacrificing the quality of the final result equivalent to that of a direct synthesis using size information. larger (16 bit).

There are two radically opposite methods for delivering periodic signals having different frequencies using the same waveform memory.

The first method consists in transmitting, to this memory, addressing signals at a constant frequency (very high) but whose phase difference between two consecutive addressed values varies according to the final frequency to be produced. Although requiring only a single clock for all frequencies, this method requires complex circuits necessarily combined with the control circuits of the synthesizer (keyboard, pedals, game selection circuits, etc.).

The second method consists in transmitting to the sample memory variable frequency addressing signals directly proportional to the frequency to be produced, this making it possible to address the memory with constant phase differences whatever the frequency.

A simple increment operation is sufficient for all frequencies, which eliminates the need to calculate a phase difference for each frequency. In return, the synthesizer must include several generators which can be integrated and a logic for associating the generators and the control data.

The present invention relates to a synthesizer using the second synthesis method (multiple frequencies) in combination with a differential representation of the amplitude data, preferably.

It is also distinguished by the fact that all of the commands intended for the synthesizer (frequencies, amplitudes, etc.) boil down to simple writing operations in memories called "virtual keyboard".

This virtual keyboard then constitutes a physical border between the synthesizer and the rest of the musical instrument. Such a synthesizer lends itself particularly well to an association with a microcomputer vis-à-vis which it behaves like a simple peripheral.

In the synthesizer, all the organs that constitute it are then linked to the virtual keyboard.

In French patent application no. 77.202 45, all of the internal operations of the synthesizer were triggered directly by the state changes of the generators.

According to the present invention, all of the operations are now carried out on the basis of a sequence of reading of the data contained in the virtual keyboard, this sequence depending on changes of state of the generators.

The virtual keyboard is now the essential organ of the synthesizer from which all the commands come. It includes a set of memories which can therefore be addressed from inside the synthesizer for synthesis operations, and from outside the synthesizer for synthesis commands (controls of the frequencies and amplitudes of the signals to be produced).

The user accesses the virtual keyboard via an IT system which is not the subject of this request. An action on a key or pedal of the instrument is detected by the computer system, which determines actions on several memories of the "virtual keyboard", according to a program recorded in the computer system. This makes it possible to obtain the production of complex signals which are the sum of several elementary periodic signals of the synthesizer In particular, if these periodic signals are sinusoids, the synthesis carried out is an additive synthesis or Fourier synthesis.

Figure 1 shows the block diagram of the synthesizer according to the invention.

du synthétiseur.The synthesizer is coupled to an external microcomputer system M via a set of connections called "bus" 2. This bus transmits address selection signals, data signals and control signals of writing and possibly reading, for

of the synthesizer.

As an indication, the microcomputer system is connected to one or more K organ keyboard, and also, if necessary, to a pedal board of buttons, pull tabs, or any device for entering data or events or for presenting information, which is not shown.

Thus, the microcomputer system places data in the memories of the virtual keyboard 1, according to the events which it takes into account (pressing or releasing of the keys, buttons, drawbars, etc.), of a recorded program and descriptive data of the tones or timbres of the sounds which are produced by the synthesizer.

The virtual keyboard 1 comprises a set of memories which are selected using an address memory 3. Access to these memories is made, on the one hand from the microcomputer, and on the other hand from the other synthesizer circuits. Multiplexer circuits, not shown in the figure, allow these two accesses, avoiding conflicts.

This virtual keyboard 1 is divided into groups. The inte addressing of a group memory is done using two signals, one, I, to designate the group and the other N, to designate the memory in group I.

The synthesizer also comprises a determined number of rectangular signal generators designated as a whole by the reference 6. By rectangular signal is meant any binary signal, square signal or impulse signal. there are, for example, 12 generators of periodic signals whose repetition frequencies are distributed according to the 12 semitones of an octave, and also 4 generators of variable frequency, either with analogical control by tension or current, or with com digital command. One of these generators can also be a noise generator, that is to say a generator at random frequency.

In the virtual keyboard 1, the number of groups is equal to that of the generators.

The selection of the memories of a group by the read control means, at the same time entails the selection of the signal from a generator, using a multiplexer 7.

During the execution of the operations relating to the data of a group, the selection address of said group is kept in a memory 8. This selection address is applied on the one hand to the multiplexer 7 for the selection of the signal of a generator and on the other hand, to the address memory 3 for the selection of the corresponding group. The memories 8 and 3 can moreover be combined.

The signal from the selected generator is used to increment. instantaneous phase data common to the signals produced by the entire corresponding group. To do this, an incrementation and memory circuit 9 is coupled to the multiplexer 7, by means of a control circuit -10, and to the virtual keyboard 1. The details of the structure and operation of these circuits will appear in the following.

dans le synthétiseur.Finally, all of the data relating to the synthesis of an analog level of each periodic signal at output is applied to the digital-analog conversion means. These include a circuit for calculating a standard amplitude step 11, a multiplication circuit 12, a digital analog converter, an amplifier _4 and a speaker 15, the latter two elements

in the synthesizer.

the calculation circuit 11 receives the instantaneous phase incremented and memorized by the circuit 9, the octave rank number 0 and the waveform number F read in a memory of a group of the virtual keyboard and delivers the value δA an amplitude step. The circuit 11 includes for example a memory of waveform samples which automatically delivers the data δA read at an address formed by the aforementioned digital input signals.

The multiplication circuit 12 performs the multiplication of the value δA by the amplitude value A read in the memory of the virtual keyboard and delivers the numerical value δA.

Finally, the converter 13 transforms this value δA into an analog step of current or voltage which is then amplified in 14 and diffused by 15.

The rest of the description will return in more detail to the structure and operation of each element of the synthesizer.

Figure 2 describes the structure of the virtual keyboard. This structure is important. It allows to understand the functioning of the synthesizer as a whole

In the following, the numerical values are given for information only. The virtual keyboard is divided into 16 memory groups, as many groups as there are generators 6. Each group is itself divided into 16 memory blocks of 16 bits each.

Each memory block is further divided into four words, of 4 bits each (it is this last division which separates on figure 1).

There are therefore 16 x 16 = 256 blocks of each 4 words, and each word contains at least one piece of information.

During synthesizer operation, the blocks are read one by one and the information they contain is transferred and used by other circuits.

The address memory 3 selects, by its content, a block of the virtual keyboard, from among the 256.

The selection address has 2 parts, a 4-bit part specifying the group number I and a 4-bit part specifying the number N of a block in the group.

To simplify Figure 2, only one group is shown.

The first block in the group is characterized by the value N = 0.

The four words it contains relate respectively, from left to right, to the number N1 of the next block to be read in the group (4 bits), to the number I 'of the next group when the processing relating to this group is completed. , and of the two parts (high and low) of the instantaneous phase Υ of the fundamental signal.

Reading this block therefore makes it possible to obtain the 3 pieces of information Nl, I 'and Υ in parallel.

7, par le numéro I, ait changé d'état.

augmente la valeur de Υ d'une unité, et inscrit la nouvelle valeur de dans le bloc (I, N = 0) et garde en mémoire cette valeur de Υ.Suppose that the address memory 3 is pointed at this first block and that the signal from the selected generator

7, by number I, has changed state.

increases the value of Υ by one, and write the new value of in the block (I, N = 0) and keep in memory this value of mémoire.

Then the value N1 read in this block is transmitted to the address memory 3, which addresses the block (I, N1) of the same group.

• La valeur N2 du bloc dans le même groupe sert à adresser le bloc suivant. La valeur F sert à spécifier la forme d'onde désirée. La valeur 0 sert à spécifier le rang d'harmonique ou d'octave du signal de sortie, par rapport au fondamental dont f est la phase instantanée. Enfin, la valeur A est l'amplitude du signal périodique de sortie.

The words in this block are then as follows:

• The value N2 of the block in the same group is used to address the next block. The value F is used to specify the desired waveform. The value 0 is used to specify the rank of harmonic or octave of the output signal, compared to the fundamental of which f is the instantaneous phase. Finally, the value A is the amplitude of the periodic output signal.

The information contained in each block is not limited to the only described above. For example, an analog output channel number, etc. can be specified.

At the same time as this information is read and transmitted to the conversion means 11, 12, 13 which calculate an analog step, the value N2 is used to specify the new block to be read in the group.

Reading this new block makes it possible to acquire new data F, 0, A and N3 and so on.

The last block read in group 1 finally delivers data F, 0 and A so that a last value N = 0 which allows to return to the first block from which is extracted the address of the first next group (l ', N = 0).

It should be noted that the sequence of the reading of the blocks of a group is such that all the blocks of the group are not necessarily read. If an N value is never specious in this block, the corresponding block will be ignored. Similarly, the reading of the block is sequential, but the order in which this reading is made is not necessarily the order of the values of N.

FIG. 3 represents a flowchart which describes the sequence of the functions of the synthesizer.

It is assumed that the address memory specifies the first block of a group 1 (N = 0).

At this time, the synthesizer performs a test, 21 to find out whether the generator number 1 (selected by the multiplexer 7) has changed state. The complete processing of the data of a group is therefore only carried out every half-period of the corresponding generator. To do this, the control circuit 10 can be constituted simply by an exclusive OR circuit whose two inputs respectively receive the output of the multiplexer 7 and the least significant bit of the phase value Υ read in the block (I, N = 0). An active signal is only issued by the exclusive OR if the two inputs are different. In this case, the phase is increased by one unit, written in the block (I, N = 0) in place of the previous value and kept in memory in circuit 9, to be used at the same time as the data read. in the other blocks of the same group.

If the circuit 10 does not deliver any active signal to the circuit 9, it then controls the transmission, by the circuit 8, of the following value I to the address memory 3. The synthesis of the analog levels of the signals of the block previously read n was therefore not carried out. The next generator test is then performed (functions 20 and 21, Figure 3) and so on.

As soon as a generator test is positive, the synthesis of the steps can take place, it proceeds as shown in Figure 3.

After incrementing phase Υ (function 23, performed by circuit 9), the block specified by the following value N is read, causing the values F, 0, A, etc. to be read. and the synthesis of a corresponding step (function 24). Then the value of the next N is compared to zero (function 25). As long as the test is negative, successive readings of the blocks in group I are carried out. As soon as this test is positive, the transfer of the next value I (and N = 0) allows the same cycle to be started again for another group (return to function 20).

Figure 4 gives the detail of the structure of the converter.

The phase Υ, harmonic or octave 0 and waveform F values are applied simultaneously to a circuit 30. This circuit 30 generates an address applied to a step memory 31. This memory contains in makes successive samples of one or more waveforms, in differential representation. The amplitude difference δA lu is added to the previous amplitude to obtain the new amplitude of the analog signal.

A multiplier circuit 12 performs the product of the value 5 A by the actual amplitude A read in the block of the virtual keyboard 1. The result ΔA is then applied to two analog digital converters 32 and 33 controlled one or the other by a control circuit 35.

This variant makes it possible to be able to deliver different signals to several different analog outputs, the number of ecant outputs, of course, given only by way of example.

The distinction of analog outputs is also made from information contained in the virtual calendar. For example, only three bits are used for choosing one of eight waveforms, the fourth bit being assigned to the choice of the analog channel.

In the case of FIG. 4, the control circuit 35 is for example a flip-flop. One of the outputs of the flip-flop authorizes the transmission of data to a converter, while the other output prohibits transmission to the other converter.

The structure of the converters is known, this having already been described in the aforementioned French patent application No. 77 202 45, in particular in FIG. 4. For the record, they each include an adder-subtractor circuit, an up-down counter and a circuit integrator. Amplifiers 36 and 37 and loudspeakers 38 and 39 are followed respectively. Analog filtering circuits having particular frequency responses can obviously be inserted in each analog channel. Most often, incorporated in amplifiers 36 and 37, such filtering circuits, called "formants", can be useful for improving the sound result of certain complex waveforms. This is the case, for example for signals imitating traditional wind or string instruments. In this case, the synthesizer has a sufficient number of analog output channels to separate the complex signals from each other. This separation is particularly easy according to the invention since the indication of the exit route from each analog sample is included in the set of digital data which are at its origin (F, 0, A, etc.). In the case where the number of analog output channels is greater than two, the circuit 35 is constituted, for example by a decoder circuit.

The circuit 30 which determines the address of the sample δA in the memory 31, in fact comprises conventional logic circuits. The phase value 9 is multiplied by the value 0 for the production of harmonics. In the case where the number J corresponds to the octaves with respect to the fundamental, phase 9 simply undergoes a number of shifts to the left equal to the number 0.

The multiplier circuit 12 can also be constituted by a read only memory. The digital input values δ A and A constitute the address of a value in memory. This value is then the product Ax δ A.

An improved converter structure makes it easier to obtain a higher number of analog output channels. According to this improvement, all of the up-down-counter circuits are replaced by a commercial digital-analog converter circuit, for example a current 8-bit model. This converter is then followed by a demultiplexer circuit which also receives the channel selection information read in the memory of the virtual keyboard. The channel selection control circuit is no longer necessary, this selection being carried out directly in the demultiplexer which generally includes an incorporated decoding circuit. Each output channel of the demultiplexer is then connected to the input of an integrator with the same characteristic as the integrator of the converter described above. As indicated previously, each analog output channel can, in addition, include filtering circuits adapted to a _L ype signal or stamp.

The improved converter operates as follows: during a cycle for reading the memories of a group, the beginning of the cycle is devoted to the incrementation of the phase of the fundamental. At the input of the converter, there is therefore no data to convert during the start of the cycle, and this for a few microseconds. Then, as the data is read in the other memories of the group, the converter successively receives the data read and delivers as output a series of analog samples of well defined constant duration. These samples are then distributed by the demultiplexer to the integrators which then deliver a signal whose level (voltage or current) varies proportionally (in magnitude and in sign) to the amplitude of the samples applied.

The essential advantage of this structure of the converter lies in the fact that the successive samples delivered by the converter all come from the same group, and that between each series of samples there passes a sufficient time interval to extinguish all the possible instabilities in the circuits, due in particular to defects in the linearity of the conversion, significant rise times, etc. This results in better immunity of the synthesizer to the intermodulation of signals between groups, this thanks to the structure of the virtual keyboard, and to the course of the cycle of readings of the data which it contains.

FIG. 5 describes another exemplary embodiment in which the division into groups of the memory of the virtual keyboard is no longer predetermined. Indeed, in the previous embodiment, each group has a fixed number of memory blocks, which limits the number of elementary sound components associated with each generator. According to this new variant, the size of the groups is no longer determined in advance, but results from the sequence. As all the groups are, in practice, never all used at the same time, for the same memory capacity of the virtual keyboard, a greater number of sound components can be created in the groups used.

Each group of blocks then contains a main block and secondary blocks, each main block containing, at least, a block identification word, a word relating to a generator number, a word relating to the common submultiple of the phase. instantaneous of several periodic signals, a word containing an address pointer to another main block and a word containing an address pointer to another main or secondary block, and each secondary block containing, at least, an identification word block, a word relating to the amplitude of a periodic signal, a word relating to the harmonic or octave rank of said signal and a word containing an address pointer to another secondary or main block.

The pointers are used by the sequential chaining means so that each block read contains a pointer to a next block to be read. Only the blocks containing useful information are thus addressed and read and these blocks can be located at any position in the memories.

In addition, the chain produced is in fact a double chain: a chain of main blocks and a chain of secondary blocks.

Only the main blocks are read as long as the state of the associated generators (designated by their number in each block) does not change. At each change of state of a generator, the sequence is interrupted at the level of the corresponding main block, then succeeds the sequence of the associated secondary blocks.

The virtual keyboard 1 is also coupled to a microcomputer bus 2 which can read or write digital data there. Multiplexing means not shown allow access to the memories of the virtual keyboard by the bus or by the synthesizer.

The virtual keyboard is divided into 256 memory blocks, for example. Each block can be addressed separately and the address of a block is defined by an 8-bit set. An address register 3 therefore contains, for each operation, the address of a block, and the blocks are read one by one, successively.

Each block is divided into several words which are addressed in parallel: these words are designated by the references 101, 102, 103, 104, 105, 106 and 107 for the two types of blocks (main and secondary).

These words contain the information used to synthesize the samples of the sound components (common submultiple of the instantaneous phase of several components, generator number, octave or harmonic number, type of waveform, amplitude of component, output channel number, etc.).

The length of each word can be arbitrary; it only depends on the number of values that the quantity considered can take.

There are two types of blocks which differ only in the information they contain from main blocks and secondary blocks.

The main blocks contain the generator number and instantaneous phase information, at least, as well as an identification bit of the main type (1 for example).

Secondary blocks contain at least octave or harmonic number, waveform type, amplitude and output channel number information, as well as a secondary type identification bit (bit 0 for example).

Each main block relates to a generator while each secondary block relates to a sound component of the output signal.

Each main block further comprises two words which respectively contain a primary address pointer and a secondary address pointer.

Each primary pointer designates the address of another main block, either directly (absolute addressing) or indirectly (relative addressing). To simplify the presentation, we will assume that each pointer contains an absolute address.

Each secondary pointer designates the address of another secondary or main block,

horloge 110 génère péoriedicuement des impulsions qui sont appliquées au registre 3. A enaque impulsion; l'adresse (le pointeur sélectionné) est enregistre dans le registre 3 et celui-ci commance alors l'adressage du bloc sisigne par cette adresse.Similarly, each secondary block includes a word containing a secondary address pointer, designating the address of another secondary or main block. From a bit location point of view, the secondary pointers of the

clock 110 periodically generates pulses which are applied to register 3. A pulse pulse; the address (the selected pointer) is recorded in register 3 and this then begins addressing the block located by this address.

The various cont pointers set up in the memory paths by the microcomputer have ensured that the sequence of addresses of the blcez by the register 3, at the rate of the clock 110, satisfies the copditions described below.

sage d'un nouveau plec se par suite d'exécution d' une série d'opérations.Each pulse

wise to a new plec as a result of performing a series of operations.

Depending on the main or secondary type or block read, the virtual keyboard therefore delivers either a first series of this data, a second series of data, and respectively leads to a first series of operations; or a second series of operations.

The synthesizer circuits which are connected to the virtual keyboard can therefore receive two types of information, only one of which can be taken into account.

the block identification bits before the same location in the two boce then serve as a barrier to distinguish the information of a main block from that of a secondary block, and other psrt; to validate or inhibit certain synthesizer operations.

• Blocs Principaux

The flow of synthesizer operations is therefore entirely conditioned by the sequence of reading of the main and secondary blocks, the details of which are as follows:

• Main Blocks

The generator number 1 (word 103) is applied by connection 124 to a transition detector 5 which receives all the signals from the generators 6.

The instantaneous sub-multipleϕ (words 104 for the most significant and 105 for the least significant) is applied to the increment and memory circuit 9 by the bi-directional connections 125 and 126. The state of the selected generator is compared with the least significant bit ϕo of the phase applied to detector 5, to detect a change of state of the generator.

The block type identification bit (word 101) is also applied to detector 5 (connection 122) in order to authorize detection only if it is a main block.

• S'il n'y a pas de changement d'état du générateur, par une connexion 127 appliquée au sélecteur 4, le détecteur 5 commande la sélection du bloc principal suivant (sélection du pointeur primaire appliqué au registre 3) et les opérations continuent exactement de la même manière pour un autre bloc principal, entraînant le test d'un autre
  
  secondaire.

Two cases can occur:

• If there is no change of state of the generator, by a connection 127 applied to the selector 4, the detector 5 controls the selection of the next main block (selection of the primary pointer applied to the register 3) and the operations continue exactly in the same way for another main block, causing the test of another
  
  secondary.

Secondary blocks

Connection 127 transmits a command for selection of secondary status to selector 4.

informations sort combirées de menière adresser une mé moire de formes d'ende 112 de lequelle est extraite un échantillon qui est applique à un circuit multiplicateur 12. Ce circuit reçoit en même temps la valeur d'amplituge A (mot 104) par la connexion 125. le résultat du produit est applique un convertisseur numérique-analogique is. Le bit d'identification de bloc secondaire (mot 101) est appliqué au convertisseur pour valider la conversion seulement dans ce cas. Il n'y a done pas de conversion en cas de lecture de bloc principal. Un démitiplexeur 109; commandé par le numéro de voie de sortie (mot 105), reçoit le signal analogique de sortie du convertisseur 13 et aiguille ce signal vers 1 un des intégrateurs. 114, 115_; etc.,119The value of phase ϕ memorized by the in circuit. incrementation 9, is applied 22 an address calculation circuit lll. The octave number word 102) is also

information comes out of combined form send a memory of shape of end 112 from which a sample is extracted which is applied to a multiplier circuit 12. This circuit receives at the same time the value of amplituge A (word 104) by connection 125 the result of the product is applied a digital to analog converter is. The secondary block identification bit (word 101) is applied to the converter to validate the conversion only in this case. There is therefore no conversion when the main block is read. A demitiplexer 109; controlled by the output channel number (word 105), receives the analog output signal from the converter 13 and directs this signal to 1 one of the integrators. 114, 115 _; etc., 119

All these operations are carried out in a duration less than the period of the clock 110.

On the impulse of this clock, the secondary pointer of the secondary block being selected, the register 3 addresses a new block which can be either another secondary block or another main block.

FIG. 6 represents a flowchart explaining the operation of the reading and conversion control means, according to the sequence of the synthesizer of FIG. 5.

It is assumed that a new main block has just been addressed. The generator number I (word 103 in Figure 1) is applied to the transition detector 5 to test the state of the corresponding generator (test 130 in Figure 2).

Two cases can occur.

Or the generator under test has not changed. In this case, the detector emits a primary pointer selection signal (block 131 in figure 6) and the generator tests continue (loop 130 - 131 - 130 - 131, etc.) until the detection of a change of state of a generator.

Or the generator has changed state. In this case, the instantaneous phase value (ϕ) is first incremented (132) then the secondary pointer is selected (133) making it possible to address a series of secondary blocks.

As soon as a new block is addressed, if it is a secondary block, a sample is calculated (135) and delivered to one of the analog outputs from the previously incremented phase value (test 134 negative ).

les blocs secondsires correspendants se sont même pas adresses.

the corresponding secondary blocks are not even addressed.

In addition, if the number of a generator does not appear in the flow, there will not even be a test of its condition

the sequence of reading of the various before the invention is therefore designed to be browsed as quickly as possible - without addressing unnecessary calculations

Figure 7 shows the detail of the transition detector circuit 3

It essentially comprises a multiplexer circuit 51 which receives the generator signals on the one hand .. and the number 1 (word 103), on the other hand as a selection command The generators 6 re-read square signals if this output 55 of the multiplexer is a binary signal.

the identification bit (word 101), is also applied to a validation input 56 so that only a main block can select a generator

a circuit 52! :? exelusif 52 receive the output signal from the multiplier as well as the lowest bis bet ϕ of the instantaneous phase.

The output of circuit 52 is connected to a non-inverting input of an AND circuit 53 and to an inverting input of an AND circuit 54.

The block identification signal (101) is also applied to non-inverting inputs of the AND circuits 53 and 54.

The output of ET 53 controls the phase increment circuit 9. Indeed, the output of this circuit can only be active (at state 1 in this case) if the selected block is a main block (signal 101 to 1) and if the designated generator has changed state (output at 1 of exclusive OR 52).

The output of ET 54 controls the selection of primary or secondary pointers (selector 4).

Indeed, if the block identification bit is at 0 (secondary block) or if the change of state of a generator is detected, the output of ET 54 is at state 0, commanding the selection of a secondary block. The selection of a primary pointer is only obtained if the block read is of the main type and if the corresponding generator has not changed state.

This second variant of the invention makes it possible to improve the speed of calculation of the sound elements of the synthesizer without limiting the number of sound elements for each generator.

selon une variance simpiardée de l'invention l'aaresse on une partIe de l'aeresse des biees de memoires peut être utilisée pour les moyens de conversion an même titre gue les contenus de ces blocs cela est possible par exemple pour le numéro 1 de générateur et /si le rang d'cetave cette variante diminue a souplesse d' utilisation des mémoires, mais reduit le nombre de memoires nécessaires. De même un arrangement différent des données dans ces memoires est posibleThe fact that after the calculation of the sound elements linked to a generator, there elapses a time interval at least equal to a period of the clock 10 (during the reading of at least one main block), before the calculation of another series of sound elements, the possible intermodulation between the sound elements of two consecutive series is

according to a simpiarded variance of the invention the aaresse one partIe of the aeresse of the biees of memories can be used for the means of conversion in the same title gue the contents of these blocks that is possible for example for the number 1 of generator and / if the rank of this variant decreases the flexibility of use of the memories, but reduces the number of memories required. Likewise, a different arrangement of the data in these memories is possible.

Claims (4)

1. Polyphonic synthesizer of periodic signals of the type comprising: means for producing successive digital samples of a periodic waveform, with variable repetition frequency, from digital phase and amplitude data in particular: - means of digital analog conversion of successive samples delivered by the means of production; - a determined number of rectangular signal generators of different frequencies, the frequency of each generator being multiple of at least one periodic signal which the synthesizer can produce; - a set of memory blocks for containing digital data representing, at least, the amplitude of the periodic signals to be produced; and - control means for sequential reading of the data in the memory blocks, coupled to the generators and to the means for producing samples :, to apply the data read to them substantially in synchronism with the signals of the generators;
The synthesizer being characterized by the fact that the set of memory blocks is divided into groups each containing all the data relating to the production of the periodic signals in harmonic frequency relationship with one of the generators, each block comprising a memory containing an address datum d 'another block, so that there is a chain of block addresses in each group; and the reading control means comprise means for addressing the blocks of each group according to the sequence of addresses in the blocks, each time the signal of the corresponding generator is changed.

each comprise a memory containing aures data each comprise a wise data (I ') from a main block of another group and in that the control means comprise means for addressing and reading a next main blec in one of the cases where the generator signal corresponding to the previous main block has not changed and where the reading of the secondary blocks of the previous group has taken place, after changing the signal of the corresponding generator. 8. Synthesizer according to one of the preceding claims, characterized in that the reading control means comprise an address memory (3) for addressing groups and memory blocks (1), the memory of addresses (3) comprising a first entry to receive the next block number, read in the addressed block, and a second entry to receive the next group number; and a group selection memory (8) comprising an input for receiving the following croup number read in the main block of the group addressed, an output connected to the second input of the address memory (3), and an input of command to transfer the group address when the block address is equal to that of the main block. 9. Synthesizer according to one of claims 1 to 5, characterized in that the set of memories is divided into groups, in number and in independent generator positions, the number of blocks in each group being. variable; each main block centering at least one block identification word, in word designating a generator, a word relating to a value instantaneously, * a word containing a primary address pointer designating another main block and an act paint container

(52) receiving on the one hand the binary output signal from the multiplexer (51) and on the other hand the least significant bit of the phase value read in the same main block, and logic means (33. 54 ) receiving the output signal from the exclusive OR (52) and the block identification word, to deliver on the one hand, a phase incrementation control signal in the only case where the block read is of the main type and the change of state of the designated generator is detected, and on the other hand, a selection signal, either of the primary pointer in the case where the block read is of the main type and no transition of the designated generator is detected, or of the secondary pointer in other cases. 12. Synthesizer according to one of the preceding claims, characterized in that the conversion means comprise: - an address calculation circuit (111, fig 5) receiving on the one hand the instantaneous phase value and, on the other hand the octave or harmonic rank read in the memory blocks; - a waveform memory (112, fig. 5, îl fig. 1), containing, at successive addresses, successive samples of amplitude or amplitude variation of a waveform, the memory being connected to the address circuit; - multiplication means (12 fig. 1 and fig 6) of each sample, delivered by the waveform memory, by the amplitude value one in a memory block - a digital-to-analog converter (13) for delivering an analog sample corresponding to each product produced by the multiplication means (le) filter means 14 fig 114 to 199 fig 5) analog signals delivered by the converging means

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