EP0011576B1 - Polyphonic synthesizer of periodical signals using digital techniques - Google Patents

Description

The present invention relates to a polyphonic synthesizer of periodic signals, using digital techniques and more generally electronic, polyphonic musical instruments comprising one or more of such a synthesizer.

A synthesizer of this kind has been described in document FR-A-2,396,375 published on January 26, 1979.

Each periodic signal results from a succession of digital samples produced in particular from a memory of waveform samples, read at variable frequency, and then converted into an analog form.

Unlike other music synthesis devices also using digital techniques, in which the waveform samples are read from the sample memory at a fixed single frequency, but at a variable phase interval (depending on the final frequency to be obtained ), the present invention relates to a synthesizer in which the samples are read at variable frequency, from several pulse signals produced by generators included in the synthesizer.

Such a structure lends itself better to the production of a completely independent synthesizer. of the rest of the musical instrument, and which can be easily controlled by microprocessor.

The synthesizer behaves like a set of independent signal generators controlled from a set of memories which each contain at least the amplitude of an output signal. The synthesizer performs, by reading each memory, a digital-analog conversion, to convert the amplitude data read and an instantaneous phase value, into an analog, positive or negative, voltage or current step.

In a first synthesizer, all the periodic signals which it can produce are generated cyclically and permanently, even if the amplitudes of most are zero, because the control circuits of the synthesizer, actuated by the impulse generators included, command a conversion digital-analog for each datum in the memory set, whatever the value of this datum. So that a signal is not produced, it is then necessary to insert a datum equal to zero in the corresponding memory.

Most of the time the number of signals produced by the synthesizer is small compared to the maximum number of signals it can produce. This leads to the fact that, in the synthesizer, numerous logical conversion operations are carried out unnecessarily for signals which are ultimately not produced, and in the control microcomputer, operations for writing data of amplitude equal to zero are necessary, hence a double loss of time.

An object of the present invention is to eliminate this drawback by eliminating the synthesis of unsolicited signals. Also, during operation, only the memories relating to the signals to be produced are used.

Another object of the present invention is to take advantage of the time savings achieved to allow the synthesis of additional signals or to increase the number of possible periodic signals.

The invention, as characterized in the claims, solves the problem of limiting the work of the synthesizer to the production of the only signals requested, by organizing the data in the control memories so that there is a sequence between those data. Only the significant data are included in this sequence. The reading of the data in the control memories, from the pulse generators and the production of the corresponding samples, therefore take place according to the determined sequence, which is executed repeatedly. The external operating means of the synthesizer can modify the sequence of data in the control memories at any time and replace it with a new sequence. They can also modify data used in the summary without changing the flow.

To achieve this well-known sequence in computer technology, each control memory must contain, in addition to the data used for the production of a sample, additional information which is read by the control means of the synthesizer and is used by these to determine the next memory in the flow.

According to a first alternative embodiment, all of the control memories are divided into memory groups, in a number equal to the number of pulse generators, each group further containing an additional memory for containing a common submultiple of the instantaneous phase of several periodic signals and each memory comprising an area for receiving addressing information from another memory of the same group.

It therefore appears that the internal control means of the synthesizer are only interested in the command memories linked together by the sequence, the other command memories not included in the sequence being ignored. The operations of the synthesizer are therefore limited to the production of the only periodic signals to be produced.

However, the fact that the control memory is divided into groups determined by construction, limits the number of elementary sound components associated with each generator to the number of memories in a group minus one. Since all groups are rarely all used together, a number more or less large amounts of memory remain unused most of the time.

According to a second variant of the invention, the control memories of the synthesizer are no longer divided into groups of fixed length, each memory being able to be assigned to any generator. Each memory includes addressing information from another memory, for carrying out the sequence. In addition, there are two types of memories: main blocks containing essentially a submultiple of the instantaneous phase as with several signals and secondary blocks containing essentially the amplitude of these signals.

Of course, the information which can be recorded in the control memories is not limited to that listed above. This allows wide possibilities of synthesizer commands by simple operations of writing in random access memory.

The present invention provides a significant reduction in these writing operations due to the sequence. Likewise, the internal operations of the synthesizer are reduced.

Among the advantages of the invention, there may be mentioned the possibility of reducing the frequency of the clock which synchronizes all of the circuits, hence better possibilities for integrating these circuits in the form of integrated circuits.

Optimizing read and convert operations also increases the design flexibility of the synthesizer. Thus the size of the memory groups can be modified to increase or decrease the number of possible signals, without increasing the complexity of the operation. Likewise, the number of generators and groups can vary, allowing the synthesis of new series of signals whose frequencies are not necessarily in relation to those of other generators. Thus, the frequencies of these generators can be variable or random.

Thanks to the second variant, the total processing time of the synthesizer operations is constantly reduced to a minimum and the use of the memories is optimal.

The reduction in processing time makes it possible to reduce the time difference between the change of state of a generator and the calculation of the samples of the corresponding sound components.

Removing group boundaries allows you to build elementary tones containing a large number of components.

• La figure 1 représente le schéma d'un synthétiseur selon la première variante, la mémoire de commande étant divisée en groupes ;
• la figure 2 représente l'organisation des données à l'intérieur d'un groupe ;
• la figure 3 représente un organigramme expliquant le déroulement des opérations du synthétiseur ;
• la figure 4 montre un exemple de réalisation d'un convertisseur numérique-analogique ;
• la figure 5 représente un synthétiseur selon la seconde variante préférée de l'invention ;
• la figure 6 représente un organigramme de fonctionnement de cette seconde variante ; et
• la figure 7 représente un détail de réalisation de la logique de détection des transitions des générateurs.

The present invention is explained below in more detail with the aid of drawings representing only embodiments.

• FIG. 1 represents the diagram of a synthesizer according to the first variant, the control memory being divided into groups;
• FIG. 2 represents the organization of the data within a group;
• Figure 3 shows a flowchart explaining the flow of synthesizer operations;
• FIG. 4 shows an exemplary embodiment of a digital-analog converter;
• FIG. 5 represents a synthesizer according to the second preferred variant of the invention;
• FIG. 6 represents an operating flow diagram of this second variant; and
• Figure 7 shows a detail of the logic of detection of generator transitions.

In general, a digital musical synthesizer is built around a waveform memory containing a point-by-point digital representation of a period (or a portion of a period, if there are symmetries) d 'a periodic waveform. The input for addressing the memory receives so-called “phase” signals and the output delivers the corresponding amplitude data or signals. The waveform memory therefore transcodes a digital phase signal into a digital amplitude signal, which is then converted into analog form.

To reconstruct a complete periodic analog signal, it is necessary to apply successive digital phase signals to the waveform memory. The latter then delivers successive amplitude signals applied to the digital-analog converter. These analog signals are filtered to eliminate quantization noise and the analog waveform is rendered.

Instead of a direct digital representation of the final waveform, the waveform memory may contain a differential representation of this waveform. Each numerical value represents the difference between the amplitude of the point considered of the waveform and that of the previous point. The digital to analog converter is then followed by an integrator which renders the final waveform. This type of synthesis has the advantage of allowing the use of digital information of reduced size (8-bit words for amplitude) without sacrificing the quality of the final result equivalent to that of a direct synthesis using size information. larger (16 bit).

To deliver periodic signals with different frequencies using the same waveform memory, there are two radically opposite methods.

The first method consists in transmitting, to this memory, addressing signals at a constant frequency (very high) but whose phase difference between two consecutive addressed values varies according to the final frequency to be produced. Although requiring only a single clock for all frequencies, this method requires complex circuits necessarily combined with the synthesizer control circuits (keyboard, pedals, game selection circuits, etc.).

The second method consists in transmitting to the sample memory variable frequency addressing signals directly proportional to the frequency to be produced, this making it possible to address the memory with differences in constant phases whatever the frequency. A simple incrementing operation suffices for all frequencies, which eliminates the need to calculate a phase difference for each frequency. In return, the synthesizer must include several generators which can be integrated and a logic for associating the generators and the control data.

The present invention relates to a synthesizer using the second synthesis method (multiple frequencies) in combination with a differential representation of the amplitude data, preferably.

It is also distinguished by the fact that all of the commands intended for the synthesizer (frequencies, amplitudes, etc.) boil down to simple operations of writing to memories called "virtual keyboard".

This virtual keyboard then constitutes a physical border between the synthesizer and the rest of the musical instrument. Such a synthesizer lends itself particularly well to an association with a microcomputer vis-à-vis which it behaves like a simple peripheral.

In the synthesizer, all the organs that constitute it are then linked to the virtual keyboard.

In document FR-A-2 396 375 published on January 26, 1979, all of the internal operations of the synthesizer were triggered directly by the changes of state of the generators.

According to the present invention, all of the operations are now carried out on the basis of a sequence of reading of the data contained in the virtual keyboard, this sequence depending on changes of state of the generators.

The virtual keyboard is now the essential organ of the synthesizer from which all commands come. It includes a set of memories which can therefore be addressed from inside the synthesizer for synthesis operations, and from outside the synthesizer for synthesis commands (controls of the frequencies and amplitudes of the signals to be produced).

The user accesses the virtual keyboard via a computer system which is not the subject of this request. An action on a key or pedal of the instrument is detected by the computer system, which determines actions on several memories of the "virtual keyboard", according to a program recorded in the computer system. This makes it possible to obtain the production of complex signals which are the sum of several elementary periodic signals of the synthesizer. In particular, if these periodic signals are sinusoids, the synthesis carried out is an additive synthesis or Fourier synthesis.

Figure 1 shows the block diagram of the synthesizer according to the invention.

The synthesizer is coupled to an external microcomputer system M via a set of connections called “bus” ₂ . This bus transmits address selection signals, data signals and write and possibly read control signals, for external control of the synthesizer.

As an indication, the microcomputer system is connected to one or more K organ keyboards, and also, if necessary, to a pedal board, buttons, pull tabs, or any device for entering data or events or presentation information, which is not shown.

Thus, the microcomputer system places data in the memories of the virtual keyboard 1, according to the events it takes into account (pressing or releasing of the keys, buttons, drawbars, etc.), of a recorded program and of data. descriptions of the tones or timbres of the sounds produced by the synthesizer.

The virtual keyboard 1 comprises a set of memories which are selected using an address memory 3. Access to these memories is made, on the one hand from the microcomputer, and on the other hand from the other synthesizer circuits. Multiplexer circuits, not shown in the figure, allow these two accesses, avoiding conflicts.

This virtual keyboard 1 is divided into groups. The internal addressing of a group memory is done using two signals, one, I, to designate the group and the other N, to designate the memory in group I.

The synthesizer furthermore comprises a determined number of rectangular signal generators generally designated by the reference 6. By rectangular signal is meant any binary signal, square signal or impulse signal. There are, for example, 12 periodic signal generators whose repetition frequencies are distributed according to the 12 semitones of an octave, and also 4 variable frequency generators, either with analog control by voltage or current, or with command digital. One of these generators can also be a noise generator, that is to say a generator at random frequency.

In the virtual keyboard 1, the number of groups is equal to that of the generators.

The selection of the memories of a group (signal 1) by the read control means, at the same time involves the selection of the signal from a generator, using a multiplexer 7.

During the execution of the operations relating to the data of a group, the selection address of said group (Signal 1) is kept in a memory 8. This selection address is applied on the one hand to the multiplexer 7 for the selection of the signal. a generator and on the other hand, to the address memory 3 for the selection of the corresponding group. The memories 8 and 3 can moreover be combined.

The signal from the selected generator is used to increment instantaneous phase data common to the signals produced by the entire corresponding group. To do this, an increment and memory circuit 9 is coupled to the multiplexer 7, via a control circuit 10, and to the virtual keyboard 1. Details of the structure and operation of these circuits will appear in the following.

Finally, all of the data relating to the synthesis of an analog level of each periodic signal at output is applied to the digital-analog conversion means. These include a circuit for calculating a standard amplitude step 11, a multiplication circuit 12, a digital analog converter, an amplifier 14 and a loudspeaker 15, the latter two elements not being included in the synthesizer.

The calculation circuit 11 receives the instantaneous phase ϕ incremented and memorized by the circuit 9, the octave rank number 0 and the waveform number F read in a memory of a group of the virtual keyboard and delivers the value 8A of an amplitude step. The circuit 11 includes for example a memory of waveform samples which automatically delivers the data 8A read at an address formed by the aforementioned digital input signals.

The multiplication circuit 12 performs the multiplication of the value 8A by the amplitude value A read in the memory of the virtual keyboard and delivers the numerical value ΔA.

Finally, the converter 13 transforms this value ΔA into an analog step of current or voltage which is then amplified in 14 and diffused by 15.

The rest of the description will return in more detail to the structure and operation of each element of the synthesizer.

Figure 2 describes the structure of the virtual keyboard. This structure is important. It allows you to understand how the synthesizer works as a whole.

In the following, the numerical values are given for information only. The virtual keyboard is divided into 16 memory groups, as many groups as there are generators 6. Each group is itself divided into 16 memory blocks of 16 bits each.

Each memory block is further divided into four words, of 4 bits each (it is this last division which appears in FIG. 1).

There are therefore 16 x 16 = 256 blocks of each 4 words, and each word contains at least one piece of information.

During synthesizer operation, the blocks are read one by one and the information they contain is transferred and used by other circuits.

The address memory 3 selects, by its content, a block of the virtual keyboard, from among the 256.

The selection address has 2 parts, a 4-bit part specifying the group number I and a 4-bit part specifying the number N of a block in the group.

To simplify Figure 2, only one group 1 is shown.

The first block of group 1 is characterized by the value N = 0.

The four words it contains relate respectively, from left to right, to the number N1 of the next block to be read in the group (4 bits), to the number l 'of the next group when the processing relating to this group is complete, and of the two parts (high and low) of the instantaneous phase ϕ of the fundamental signal.

Reading this block therefore makes it possible to obtain, in parallel, the 3 pieces of information N1, l 'and ϕ.

Suppose that the address memory 3 is pointed at this first block and that the signal from the generator selected by the multiplexer 7, by the number I, has changed state. Circuit 9 then increases the value of ϕ by one, and writes the new value of ϕ in the block (I, N = 0) and keeps in memory this value of ϕ.

Then the value N1 read in this block is transmitted to the address memory 3, which addresses the block (I, N1) of the same group.

• La valeur N2 du bloc dans le même groupe sert à adresser le bloc suivant. La valeur F sert à spécifier la forme d'onde désirée. La valeur 0 sert à spécifier le rang d'harmonique ou d'octave du signal de sortie, par rapport au fondamental dont ϕ est la phase instantanée. Enfin, la valeur A est l'amplitude du signal périodique de sortie.

The words in this block are then as follows;

• The value N2 of the block in the same group is used to address the next block. The value F is used to specify the desired waveform. The value 0 is used to specify the harmonic or octave rank of the output signal, compared to the fundamental of which ϕ is the instantaneous phase. Finally, the value A is the amplitude of the periodic output signal.

The information contained in each block is not limited to the only described above. For example, an analog output channel number, etc. can be specified.

At the same time as this information is read and transmitted to the conversion means 11, 12, 13 which calculate an analog step, the value N2 is used to specify the new block to be read in the group.

Reading this new block makes it possible to acquire new data F, O, A and N3 and so on.

The last block read in group 1 finally delivers data F, O and A as well as a last value N = 0 which makes it possible to return to the first block from which the address of the first following group is extracted (l ', N = 0).

It should be noted that the sequence of the reading of the blocks of a group is such that all the blocks of the group are not necessarily read. If an N value is never specified in this block, the corresponding block will be ignored. Similarly, the reading of the block is sequential, but the order in which this reading is made is not necessarily the order of the values of N.

FIG. 3 represents a flowchart which describes the sequence of the functions of the synthesizer.

It is assumed that the address memory specifies the first block of a group 1 (N = 0).

At this time, the synthesizer performs a test, 21 to find out whether the generator number 1 (selected by the multiplexer 7) has changed state. The complete processing of the data of a group is therefore only carried out every half-period of the corresponding generator. To do this, the control circuit 10 can be constituted simply by an exclusive OR circuit, the two of which inputs receive respectively the output of the multiplexer 7 and the least significant bit of the phase value ϕ read in the block (I, N = 0). An active signal is only issued by the exclusive OR if the two inputs are different. In this case, phase ϕ is increased by one, written in the block (I, N = 0) in place of the previous value and kept in memory in circuit 9, to be used at the same time as the data read in the other blocks of the same group.

If the circuit 10 does not deliver any active signal to the circuit 9, it then controls the transmission, by the circuit 8, of the following value l to the address memory 3. The synthesis of the analog levels of the signals of the block previously read n was therefore not carried out. The next generator test is then performed (functions 20 and 21, Figure 3) and so on.

As soon as a generator test is positive, the synthesis of the steps can take place, it takes place as shown in Figure 3.

After incrementing phase ϕ (function 22, performed by circuit 9), the block specified by the following value N is read, causing the values F, 0, A, etc. to be read. and the synthesis of a corresponding step (function 24). Then the value of the next N is compared to zero (function 25). As long as the test is negative, successive readings of the blocks of group 1 are carried out. As soon as this test is positive, the transfer of the next value I (and N = 0) allows the same cycle to be started again for another group (return to function 20).

Figure 4 gives the detail of the structure of the converter.

The values of phase <p, of harmonic rank or of octave 0 and of waveform F are applied simultaneously to a circuit 30. This circuit 30 generates an address applied to a step memory 31. This memory contains in fact successive samples of one or more waveforms, in differential representation. The amplitude difference 8A read is added to the previous amplitude to obtain the new amplitude of the analog signal.

A multiplier circuit 12 performs the product of the value 8A by the actual amplitude A read in the block of the virtual keyboard 1. The result AA is then applied to two analog digital converters 32 and 33 controlled either by a control circuit 35.

This variant makes it possible to be able to deliver different signals to several different analog outputs, the number of outputs being, of course, given solely by way of example.

The distinction of analog outputs is also made from information contained in the virtual keyboard. For example, only three bits are used for the choice of a waveform among eight, the fourth bit being assigned to the choice of the analog channel.

In the case of FIG. 4, the control circuit 35 is for example a flip-flop. One of the outputs of the flip-flop authorizes the transmission of data to a converter, while the other output prohibits transmission to the other converter.

The structure of the converters is known, this having already been described in document FR-A-2 396 375 published on January 26, 1979, in particular in FIG. 4. For the record, they each include an adder-subtractor circuit, an up-down counter and an integrator circuit. They are followed respectively by amplifiers 36 and 37 and speakers 38 and 39. Analog filter circuits having specific frequency responses can obviously be inserted in each analog channel. Most often, incorporated in amplifiers 36 and 37, such filtering circuits, called “formants”, can be useful for improving the sound result of certain complex waveforms. This is the case, for example, for signals imitating traditional wind or string instruments. In this case, the synthesizer has a sufficient number of analog output channels to separate the complex signals from each other. This separation is particularly easy according to the invention since the indication of the output channel of each analog sample is included in the set of digital data which are at its origin (F, O, A, etc.). In the case where the number of analog output channels is greater than two, the circuit 35 is constituted, for example by a decoder circuit.

The circuit 30 which determines the address of the sample 8A in the memory 31 in fact comprises conventional logic circuits. The phase value ϕ is multiplied by the value of harmonic rank or octave 0 for the production of harmonics. In the case where the number 0 corresponds to the octaves with respect to the fundamental, the phase <p simply undergoes a number of shifts to the left equal to the number 0.

The multiplier circuit 12 can also be constituted by a read only memory. The digital input values 8A and A constitute the address of a value in memory. This value is then the product A x 8A.

An improved converter structure makes it easier to obtain a higher number of analog output channels. According to this improvement, all of the up-down-counter circuits are replaced by a commercial digital-analog converter circuit, for example a current 8-bit model. This converter is then followed by a demultiplexer circuit which also receives the channel selection information read in the memory of the virtual keyboard. The channel selection control circuit 35 is no longer necessary, this selection being carried out directly in the demultiplexer which generally includes an incorporated decoding circuit. Each output channel of the demultiplexer is then connected to the input of an integrator with the same characteristic as the integrator of the converter described above. As indicated above, each analog output channel can, in addition, include filtering circuits adapted to a type of signal or timbre.

The improved converter operates as follows: during a cycle for reading the memories of a group, the beginning of the cycle is devoted to the incrementation of the phase of the fundamental. At the input of the converter, there is therefore no data to convert during the start of the cycle, and this for a few microseconds. Then, as the data is read in the other memories of the group, the converter successively receives the data read and delivers as output a series of analog samples of well defined constant duration. These samples are then distributed by the demultiplexer to the integrators which then deliver a signal whose level (voltage or current) varies proportionally (in magnitude and in sign) to the amplitude of the samples applied.

The essential advantage of this structure of the converter lies in the fact that the successive samples delivered by the converter all come from the same group, and that between each series of samples there passes a sufficient time interval to extinguish all the possible instabilities in the circuits, due in particular to defects in the linearity of the conversion, significant rise times, etc. This results in a better immunity of the synthesizer to the intermodulation of signals between groups, this thanks to the structure of the virtual keyboard, and to the course of the cycle of readings of the data which it contains.

FIG. 5 describes another exemplary embodiment in which the division into groups of the memory of the virtual keyboard is no longer predetermined, this grouping being no longer provided physically but logically. Indeed, in the previous embodiment, each group has a fixed number of memory blocks, which limits the number of elementary sound components associated with each generator. According to this new variant, the size of the groups is no longer determined in advance, but results from the sequence. Thus as all the groups are, in practice, never all used at the same time, for the same memory capacity of the virtual keyboard, a greater number of sound components can be created in the groups used.

Each group of blocks then contains a main block and secondary blocks, each main block containing, at least, a block identification word, a word relating to a generator number, a word relating to the common submultiple of the phase. instantaneous of several periodic signals, a word containing an address pointer to another main block and a word containing an address pointer to another main or secondary block, and each secondary block containing, at least, an identification word block, a word relating to the amplitude of a periodic signal, a word relating to the harmonic or octave rank of said signal and a word containing an address pointer to another secondary or main block.

The pointers are used by the sequential chaining means so that each block read contains a pointer to a next block to be read. Only the blocks containing useful information are thus addressed and read and these blocks can be located at any position in the memories.

In addition, the chain produced is in fact a double chain: a chain of main blocks and a chain of secondary blocks.

Only the main blocks are read as long as the state of the associated generators (designated by their number in each block) does not change. At each change of state of a generator, the sequence is interrupted at the level of the corresponding main block, then succeeds the sequence of the associated secondary blocks.

The virtual keyboard 1 is also coupled to a microcomputer bus 2 which can read or write digital data there. Multiplexing means not shown allow access to the memories of the virtual keyboard by the bus or by the synthesizer.

The virtual keyboard is divided into 256 memory blocks, for example. Each block can be addressed separately and the address of a block is defined by an 8-bit set. An address register 3 therefore contains, for each operation, the address of a block, and the blocks are read one by one, successively.

Each block is divided into several words which are addressed in parallel: these words are designated by the references 101, 102, 103, 104, 105, 106 and 107 for the two types of blocks (main and secondary).

These words contain the information used to synthesize the samples of the sound components (common submultiple of the instantaneous phase of several components, generator number, octave or harmonic number, type of waveform, amplitude of component, output channel number, etc.).

The length of each word can be arbitrary; it only depends on the number of values that the quantity considered can take.

There are two types of blocks which differ only in the information they contain: main blocks and secondary blocks.

The main blocks contain the generator number and instantaneous phase information, at least, as well as an identification bit of the main type (1 for example).

Secondary blocks contain at least octave or harmonic number, waveform type, amplitude and output channel number information, as well as a secondary type identification bit (bit 0 for example).

Each main block relates to a generator while each secondary block relates to a sound component of the output signal.

Each main block further comprises two words which respectively contain a primary address pointer and an address pointer secondary.

Each primary pointer designates the address of another main block, either directly (absolute addressing) or indirectly (relative addressing). To simplify the presentation, we will assume that each pointer contains an absolute address.

Each secondary pointer designates the address of another secondary or primary block.

Similarly, each secondary block includes a word containing a secondary address pointer, designating the address of another secondary or main block. From the point of view of bit location, the secondary pointers of the two blocks coincide.

The primary and secondary pointers are used to determine the sequence of the reading of the blocks.

An address selector 4 receives the two primary and secondary pointers, via connections 120 and 121, and transmits one of the two pointers to the address register 3. A clock 110 periodically generates pulses which are applied to register 3. At each pulse, the address (the selected pointer) is recorded in register 3 and this then controls the addressing of the block designated by this address.

The different pointers are set up in the memory blocks by the microcomputer so that the sequence of addresses of the blocks by the register 3, at the rate of the clock 110, satisfies the conditions described below.

Each pulse of the clock 110 therefore causes the addressing of a new block and, consequently, the execution of a series of operations.

Depending on the main or secondary type of the block read, the virtual keyboard therefore delivers either a first series of data or a second series of data, and leads respectively to either a first series of operations or a second series of operations.

The synthesizer circuits which are connected to the virtual keyboard can therefore receive two types of information, only one of which can be taken into account.

The block identification bits, having the same location (101) in the two blocks, then serve on the one hand to distinguish the information of a main block from that of a secondary block, and on the other hand, to validate or inhibit certain synthesizer operations.

• Blocs principaux

The flow of synthesizer operations is therefore entirely conditioned by the sequence of reading of the main and secondary blocks, the details of which are as follows:

• Main blocks

The generator number 1 (word 103) is applied by connection 124 to a transition detector 5 which receives all the signals from the generators 6.

The submultiple <p of instantaneous phase (words 104 for the most significant and 105 for the least significant) is applied to the increment and memory circuit 9 by the bi-directional connections 125 and 126. The state of the selected generator is compared with the least significant bit tp _o of the phase applied to the detector 5, to detect a change of state of the generator.

The block type identification bit (word 101) is also applied to detector 5 (connection 122) in order to authorize detection only if it is a main block.

• S'il n'y a pas de changement d'état du générateur, par une connexion 127 appliquée au sélecteur 4, le détecteur 5 commande la sélection du bloc principal suivant (sélection du pointeur primaire appliqué au registre 3) et les opérations continuent exactement de la même manière pour un autre bloc principal, entraînant le test d'un autre générateur.

Two cases can occur:

• If there is no change of state of the generator, by a connection 127 applied to the selector 4, the detector 5 controls the selection of the next main block (selection of the primary pointer applied to the register 3) and the operations continue exactly in the same way for another main block, causing the test of another generator.

If there is a change of state of the designated generator in the block, the detector 5 triggers on the one hand the incrementing and the memorization of the phase value <p by the circuit 9, the incremented value being immediately memorized in the main block in place of the previous value, and on the other hand, the selection (by connection 127) of the secondary pointer (word 107). The following period of the clock 110 then succeeds the reading of a secondary block.

Secondary blocks

Connection 127 transmits a secondary block selection command to selector 4.

The value of the phase <p, stored by the incrementing circuit 9, is applied to an address calculation circuit 111. The octave number (word 102) is also applied to this circuit by the link 123 as well as F, the waveform number (word 103) via the link 124. The information is combined so as to address a waveform memory 112 from which a sample is extracted which is applied to a multiplier circuit 12. This circuit receives at the same time the amplitude value A (word 104) by connection 125. The result of the product is applied to a digital-analog converter 13. The secondary block identification bit (word 101) is applied to the converter to validate the conversion only in this case. There is therefore no conversion when the main block is read. A demultiplexer 109, controlled by the output channel number (word 105), receives the analog output signal from the converter 13 and routes this signal to one of the integrators 114, 115, etc., 119.

All these operations are carried out in a duration shorter than the period of the clock 110.

On the impulse of this clock, the secondary pointer of the secondary block being selected, the register 3 addresses a new block which can be either another secondary block or another main block.

FIG. 6 represents a flowchart explaining the operation of the reading and conversion control means, according to the sequence of the synthesizer of FIG. 5.

It is assumed that a new main block has just been addressed. The generator number 1 (word 103 in Figure 1) is applied to the transition detector 5 to test the state of the corresponding generator (test 130 in Figure 2).

• Ou bien le générateur en test n'a pas changé. Dans ce cas, le détecteur émet un signal de sélection de pointeur primaire (bloc 131 figure 6) et les tests des générateurs continuent (boucle 130 131 130 131, etc.) jusqu'à la détection d'un changement d'état d'un générateur.

Two cases can occur:

• Or the generator under test has not changed. In this case, the detector emits a primary pointer selection signal (block 131 in figure 6) and the generator tests continue (loop 130 131 130 131, etc.) until a change of state is detected. a generator.

Or the generator has changed state. In this case, the instantaneous phase value (<p) is first incremented (132) then the secondary pointer is selected (133) making it possible to address a series of secondary blocks.

As soon as a new block is addressed, if it is a secondary block, a sample is calculated (135) and delivered to one of the analog outputs, from the previously incremented phase value (test 134 negative).

If it is a main block, the sequence continues for another generator (test 134 positive).

Thus, at each change of state of a generator, all the secondary blocks relating to this generator are explored and the corresponding sound elements are calculated and delivered.

If there is no change in the state of a generator, the corresponding secondary blocks are not even addressed.

In addition, if the number of a generator does not appear in the flow, there will not even be a test of its state.

The sequence of reading of the blocks according to the invention is therefore designed to be traversed as quickly as possible, without addressing, or unnecessary calculations.

FIG. 7 shows the detail of the transition detector circuit 5.

It essentially comprises a multiplexer circuit 51 which receives the signals from the generators 6, on the one hand, and the number I (word 103), on the other hand, as a selection command. The generators 6 deliver square signals so that the output 55 of the multiplexer is a binary signal.

The identification bit (word 101) is also applied to a validation input 56, so that only a main block can select a generator.

An exclusive OR circuit 52 receives the output signal from the multiplexer as well as the least significant bit cp _o of the instantaneous phase.

The output of circuit 52 is connected to a non-inverting input of an AND circuit 53 and to an inverting input of an AND circuit 54.

The block identification signal (101) is also applied to non-inverting inputs of AND circuits 53 and 54.

The output of ET 53 controls the phase increment circuit 9. In fact, the output of this circuit can only be active (in state 1 in this case) if the selected block is a main block (signal 101 to 1) and if the designated generator has changed state (output at 1 of exclusive OR 52).

The output of ET 54 controls the selection of primary or secondary pointers (selector 4).

Indeed, if the block identification bit is at 0 (secondary block) or if the change of state of a generator is detected, the output of ET 54 is at state 0, commanding the selection of a secondary block. The selection of a primary pointer is only obtained if the block read is of the main type and if the corresponding generator has not changed state.

This second variant of the invention makes it possible to improve the speed of calculation of the sound elements of the synthesizer without limiting the number of sound elements for each generator.

The fact that after the calculation of the sound elements linked to a generator, there elapses a time interval at least equal to a period of the clock 10 (during the reading of at least one main block), before the calculation of another series of sound elements, the possible intermodulation between the sound elements of two consecutive series is practically eliminated.

The invention applies to electronic musical instruments. Such a musical instrument will therefore include a synthesizer according to the invention controlled by a microprocessor device, for example, which will load the data into the memories of the virtual keyboard 1, according to a desired sequence. Depending on the richness of the desired sound signals, the generators 6 may contain between 12 generators at fixed frequencies and 16 generators, or more, at variable frequencies.

According to a simplified variant of the invention, the address or part of the address of the memory blocks can be used for the conversion means, in the same way as the contents of these blocks. This is possible, for example, for generator number 1, and / or the octave rank. This variant reduces the flexibility of use of the memories, but reduces the number of memories required. Likewise, a different arrangement of the data in these memories is possible.

Claims (15)

1. Polyphonic synthesizer of periodic signals of the type comprising :

- means for producing numeric successive samples of a periodic wave shape at variable repetition frequency, using numeric data of phase and amplitude in particular,

- means for numerical-analog conversion of successive samples, delivered by the producing means,

- a predetermined number of generators of rectangular signals having different frequencies, the frequency of each generator being a multiple of at least one periodic signal which the synthesizer can produce,

- an entity of memory blocks for holding numerical data representing at least the amplitude of the periodic signals to be produced and,

- means for controlling the sequential reading of data in the memory blocks, coupled to the generators and to the sample producing means for applying the read-out data to the latter substantially in synchronism with the signals of the generators, the synthesizer being characterized by the fact that

- the entity of memory blocks is divided, physically or logically, into groups having or not a fixed length, each holding the entity of data relative to the production of periodic signals in harmonic frequency relation with one of the generators, each block comprising a memory holding an address datum of another block, such that there exists an enchainment of block addresses in each group and

- the reading control means comprise means to address the block of each group according to the enchainment of the addresses in the block at each change of the signal of the respective generator.

2. Synthesizer according to claim 1, characterized in that each memory group comprises a principal block comprising a memory holding a common sub-multiple of the phase of the periodic signal in harmonic frequency relation with the corresponding generator of said group, and that the control means comprise means to increment the value of the phase in synchronism with the signal of the generator.

3. Synthesizer according to claims 1 and 2, characterized in that each memory group can comprise secondary blocks each comprising an amplitude datum and a datum relative to the harmonic range of a signal to be produced.

4. Synthesizer according to claim 3, characterized in that each secondary block can comprise in addition a memory for holding a datum relative to a particular wave shape of a signal to be produced.

5. Synthesizer according to claim 3 or 4, characterized in that each secondary block can comprise in addition a memory for holding a selection datum for the output channel of the periodic signal to be produced.

6. Synthesizer according to one of the preceding claims, characterized in that the memory entity is divided into equal groups of the same number as that of the generators, the address of each block of one and the same group comprising a common part (I) and in that the control means comprise means for the selection of the generator corresponding to each group in accordance with the common part (I) of the address.

7. Synthesizer according to claim 6, characterized in that the principal blocks of the memory groups occupy identical positions in said groups and comprise each a memory holding an address datum (I') of a principal block of another block, and in that the control means comprise means for addressing and reading a following principal block in one of the cases where the signal of the generator corresponding to the preceding principal block has not changed and where the enchainment of the secondary blocks of the preceding group has taken place after change of the signal-of the corresponding generator.

8. Synthesizer according of the preceding claims, characterized in that the reading control means comprise an address memory (3) for addressing the groups and the memory blocks (I), the address memory (3) comprising a first input for receiving the number of the following blocks, read in the addressed block, and a second input for receiving the number of the following group ; and a group selection memory (8) comprising an input for receiving the number of the following group, read in the principal block of the addressed group, an output connected to the second input of the address memory (3), and a control input for controlling the transfer of the address of the group when the address of the block is equal to that of the principal block.

9. Synthesizer according to one of claims 1 to 5, characterized in that the entity of memories is divided into groups with numbers and positions independent of the generators, the number of blocks in each group being variable ; each principal block holding at least a block identification word, a generator designation word, a word relative to an instantaneous phase value, a word containing a primary address pointer designating another principal block, and a word containing a secondary address pointer designating at least a block identification word, a word relative to the amplitude of an output signal, a word relative to the octave rang or harmonic rang of the output signal, and a word containing a secondary address pointer designating another principal or secondary block.

10. Synthesizer according to claim 9, characterized in that the reading control means comprise :

- a clock (110);

- an address register (3) delivering an address of a block simultaneously to the entity of memories (1) and having an input for the control of memorizing, connected to the clock (10), and an address input,

- an address selection circuit (4) connected to the input of the register (3) and comprising two inputs for receiving, respectively, the primary and secondary address pointers of each block, if those exist, and a selection control input,

- transition detector means (5) connected to the generators (6) and having an input for receiving the block identification word, another input for receiving the generator designating word, and output for delivering a selection signal to the selector (4), on the one hand, and phase incre- mentation command signal, on the other hand.

11. Synthesizer according to claim 10, characterized in that the transition detector means (5) comprise a multiplexer circuit (51) receiving at its input the signals of generators (6) and as a control input the number (I) designating a generator read in a principal block, and delivering at the output the instantaneous binary status of the signal of the selected generator ; an EXCLUSIVE OR circuit (52) receiving, on the one hand, the binary signal from the output of the multiplexer (51) and, on the other hand, the bit having the least significant weight of the phase value read in the same principal block, and logic means (53, 54) receiving the output signal of the EXCLUSIVE OR (52) and the block identification word for delivering, on the one hand, a phase incrementa- tion control signal in the only case where the read block is of the principal type and the change of the status of the designated generator is detected, and, on the other hand, a selection signal, either of the primary pointer in the case where the read block is of the principal type and there is no detection of the transition of the designated generator, or of the secondary pointer in the other cases.

12. Synthesizer according to one of the preceding claims, characterized in that the conversion means comprise :

- an address calculation circuit (111, figure 5) receiving, on the one hand, the instantaneous phase value and, on the other hand, the octave rang or harmonic range read in the memory blocks,

- a wave-shaped memory (112, figure 5 ; 11, figure 1) holding under successive addresses, successive amplitude samples or amplitude variation samples of a wave shape, the memory being connected to the address circuit,

- multiplication means (12, figure 1 and figure 5) for multiplying each sample, delivered by the wave shape memory, by the amplitude value, read in a memory block,

- a numerical-analog converter (13) for delivering an analog sample commensurate with each product produced by the multiplication means (12),

- filter means (14, figure 1 ; 114 to 119, figure 5) for filtering the analog signals delivered by the conversion means (13).

13. Synthesizer according to claim 12, characterized in that the address calculation circuit (111) comprises in addition a wave shape selection input for receiving the wave shape datum of a memory block.

14. Synthesizer according to claims 12 to 13, characterized in that the conversion means comprise in addition a demultiplexing circuit (109, figure 5) connected with its input to the converter output (13) with its output to a plurality of filter means (114 to 119), and with its control input to the entity of memories (1) for receiving a word relative to a number of an analog output channel.

15. Synthesizer according to one of the preceding claims, characterized in that the address or a part of the address of each block may contain at least a datum, applied to the conversion means.

Images