EP0007579A1 - Circuit de surveillance de l'état de systèmes de signalisation, spécialement de systèmes lumineux de signalisation de circulation routière - Google Patents

Circuit de surveillance de l'état de systèmes de signalisation, spécialement de systèmes lumineux de signalisation de circulation routière Download PDF

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Publication number
EP0007579A1
EP0007579A1 EP79102540A EP79102540A EP0007579A1 EP 0007579 A1 EP0007579 A1 EP 0007579A1 EP 79102540 A EP79102540 A EP 79102540A EP 79102540 A EP79102540 A EP 79102540A EP 0007579 A1 EP0007579 A1 EP 0007579A1
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EP
European Patent Office
Prior art keywords
signal
microprocessor
circuit arrangement
test
states
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP79102540A
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German (de)
English (en)
Other versions
EP0007579B1 (fr
Inventor
Heinrich Dipl.-Ing. Brunner
Peter Drebinger
Peter Dr. Höhne
Johann Hoisl
Günter Kochanowski
Walter Dipl.-Ing. Wimmer
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Siemens AG
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Siemens AG
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Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to AT79102540T priority Critical patent/ATE1305T1/de
Publication of EP0007579A1 publication Critical patent/EP0007579A1/fr
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Publication of EP0007579B1 publication Critical patent/EP0007579B1/fr
Expired legal-status Critical Current

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    • G—PHYSICS
    • G08—SIGNALLING
    • G08G—TRAFFIC CONTROL SYSTEMS
    • G08G1/00—Traffic control systems for road vehicles
    • G08G1/097—Supervising of traffic control systems, e.g. by giving an alarm if two crossing streets have green light simultaneously

Definitions

  • the invention relates to a circuit arrangement for monitoring the state of signal systems, in particular road traffic light signal systems, with a comparator device which allows actual signal states supplied by signal transmitters to be compared with predefined test signal states, and with an evaluation device which is only used to determine permissible values
  • a clock pulse sequence is supplied to the actual signal states and which indicates the presence of a fault when determining impermissible actual signal states.
  • a circuit arrangement of the type described above is already known (see magazine “Straday Fundamentalstechnik", Issue 2, 1972, pages 39 to 43).
  • the comparator device is constructed from a number of logic elements which are connected to the signal transmitters in fixed wiring.
  • the signal states of the existing signal transmitters are compared with so-called "hostile" signal images. If a match of the actually existing signal states, that is to say the actual signal states of the relevant signal transmitters, with such a predetermined signal image is determined, this state is evaluated as a faulty state in an appealing signal fuse.
  • the disadvantage here is that due to the individual wiring in accordance with the prevailing circumstances, a changeover or expansion of such a circuit arrangement in adaptation to new or changed conditions is difficult to hear.
  • the invention is therefore based on the object to show a way in which in a circuit arrangement of the type mentioned different signal states can be safely monitored for their admissibility or inadmissibility in a simple manner, without changing the signal states to adapt to changed conditions or an expansion of the signaling system to be monitored, manual wiring work must be carried out in the circuit arrangement in question.
  • test signals indicating the test signal states are recorded in a memory and the signals indicating the actual signal states of the signal transmitters can be processed in at least one microprocessor such that each is an actual one -Signal state indicating signal is compared with all the test signals called up successively from the memory.
  • the invention has the advantage over the known circuit arrangement considered above that a change in the signal states to be monitored by signaling systems in adaptation to changed circumstances or as a result of an extension without the need for manual wiring work in the circuit arrangement monitoring the relevant signal states. Rather, it is sufficient to simply exchange the memory provided for another memory which contains the test signals which are suitable for the respective case.
  • test signals indicating the non-permitted signal states of the signal transmitters are stored in the respective memory. This results in a particularly simple control option for the evaluation device. Otherwise, this enables a positive determination of the presence of impermissible actual signal states of the signal transmitters, which is often desirable for safety reasons.
  • signal transmitters belonging to two separate groups of signal transmitters are expediently provided, a separate microprocessor being provided for processing the signals emitted by the signal transmitters of each group of signal transmitters. This advantageously enables a particularly reliable detection of the actual signal states of the signal transmitters that are present.
  • each microprocessor is permanently assigned a separate memory for recording test signals indicating predetermined test signal states.
  • the monitoring to be carried out can still be carried out when the circuit part containing a microprocessor is inoperative so that it is unable to detect any impermissible actual signal states.
  • the signal transmitters are expediently connected on the output side to inputs of the respective microprocessor via pulse-controlled transmission elements.
  • pulse-controlled transmission elements In this way, there is the advantage of a relatively simple possibility of monitoring the transmission paths between the signal generators and the microprocessors. The proper functioning of the transmission paths can be concluded from the occurrence of pulses on these transmission paths.
  • a particularly simple pulse control is obtained when an AC mains voltage, which is supplied by a mains AC voltage source that feeds the signal transmitters, is used for pulse control of the transmission elements. In this case, no separate pulse control source needs to be provided for the pulse control of the transmission elements.
  • a particularly simple and reliable monitoring of the transmission paths mentioned arises when the between the. pulse pauses from the transmission elements successively emitted signal pulses are monitored for their presence with the aid of the respective microprocessor. During the occurrence of the relevant signal pauses, there must be defined potential relationships on the transmission paths in question which can be easily determined in the respective microprocessor.
  • the respective microprocessor receives a separate test signal can be supplied, upon the recording of which the microprocessor in question has to emit a specific signal.
  • D a - can also advantageously monitor the proper operation of the respective microprocessor in the course of the safe monitoring of the signal states of the signal transmitters, which overall contributes to an increase in the operational reliability of the entire circuit arrangement.
  • the procedure is such that when two microprocessors are used, each microprocessor can trigger the supply of a test signal to the other microprocessor and allow the evaluation of the message signal emitted by this other microprocessor. This advantageously ensures mutual monitoring of the two microprocessors and safe operation of the entire circuit arrangement.
  • test signals are expediently those signal bit - used combinations in which the respective microprocessor outputs a of the permissible in the presence of actual signal states of output clock pulse sequence different output signal without causing the delivery of the presence of a fault indicating alarm signal by the associated evaluation circuit of the respective other microprocessor can be evaluated.
  • the respective test signal bit combinations are to a certain extent intentionally intended to indicate the presence of a malfunction, which the respective microprocessor should also recognize, without, however, triggering the associated evaluation circuit so that it triggers an alarm.
  • the measure in question accommodates the use of conventional evaluation circuits with electromechanical switching elements, which take a relatively long time to trigger span that is on the order of a few milliseconds - while the output signal of the respective microprocessor may occur, for example, within a few microseconds.
  • the respective test signal can expediently be loaded into a register under the control of the respective microprocessor, which is connected on the output side to those inputs of the other microprocessor to which the respective test signal is to be supplied. In this way, a simple, controlled provision of the respective test signals is advantageously achieved.
  • the circuit arrangement shown in the drawing is used to monitor the state of a signaling system, which may in particular be a traffic light signaling system.
  • This signal system includes a number of signal transmitters which, in the present case, may not only emit the actual signaling signs, but also should emit signals corresponding to their signal states, that is to say state signals.
  • These status signals can either be emitted by the signal generators themselves or by signaling elements connected to these signal generators.
  • These detectors can be voltage detectors or current detectors; such notification elements are known per se and need not be further explained here.
  • the status signals emitted by the signal transmitters or by the associated signaling members occur at connections Ea1 to Ean and indicated in the drawing Eb1 to Ebn on.
  • connections Ea1 to Ean and indicated in the drawing Eb1 to Ebn on two groups of corresponding connections are provided in the present case, connections of both groups of connections corresponding to one another being supplied in each case with signal signals corresponding to one another or status signals associated with them. This means that the signal states of the individual signal transmitters are recorded redundantly.
  • Each group of connections Ea1 to Ean or Eb1 to Ebn has at least as many connections as signal transmitters or signaling elements associated therewith are provided within the signaling system to be monitored.
  • logic elements GUa1 to GUan with their one inputs are connected to the connections Ea1 to Ean.
  • logic elements GUb1 to GUbn formed by AND gates, are connected in a corresponding manner with their one inputs.
  • All of the link elements GUa1 to GUan, GUb1 to GUbn just mentioned are connected with their respective other inputs to the output of a clock pulse generator Tg, which makes the link elements transferable in pulses by emitting pulses.
  • the AND gates GUa1 to GUan are connected on the exhaust gas side in each case via OR gates GOa1 to GOan to the one input connections Ea1 to Ean of a first microprocessor MP1.
  • the AND gates GUb1 to GUbn are connected with their outputs via OR gates GOb1 to GObn to the one input connections eb1 to ebn of a second microprocessor MP2.
  • the two microprocessors MP1 and MP2 like each other completely corresponding microprocessors, such as those of the type SAB8048.
  • the OR gates GOal to GOan just mentioned are also connected on the input side to the outputs of the register stages of a first register Reg1, which may be a shift register.
  • This shift register Reg1 is connected with a signal and shift input to an output connection as21 of the microprocessor MP2.
  • the OR gates GOb1 to GObn connected on the output side to the input connections eb1 to ebn of the microprocessor MP2 are connected in a corresponding manner to the outputs of register stages of a register Reg2, which may also be a shift register.
  • This shift register Reg2 is connected with a signal and shift input to an output connection as11 of the microprocessor MP1.
  • a program memory and a data memory are associated with each of the two microprocessors MP1, MP2.
  • the microprocessor MP1 is connected with an input terminal em11 to the associated program memory ROM1, which is a read-only memory and which can be programmable if necessary.
  • the microprocessor MP1 With an input connection em12, the microprocessor MP1 is connected to an associated data memory RAM1, which may also be a permanent memory or a memory with random access that is protected against power failure.
  • the other microprocessor MP2 is connected in a corresponding manner via an input connection em21 to its associated program memory ROM2 and via an input connection em22 to its associated data memory RAM2. The same applies to these two memories ROM2 and RAM2 as to the memory associated with the microprocessor MP1.
  • a separate evaluation device US1 or US2 is permanently associated with each of the two microprocessors MP1, MP2.
  • the evaluation device US1 is connected on the input side to an output connection am1 of the microprocessor MP1.
  • the evaluation device US2 is connected on the input side to an output connection am2 of the microprocessor MP2.
  • These two evaluation devices may each contain an electromechanical device, such as a relay R1 or a relay R2, which is excited by the respective microprocessor in the presence of a signal indicating a malfunction. As already indicated above, it is necessary for the relays in question to be energized for the respective signal to have a certain minimum duration.
  • the two evaluation devices Us1 and Us2 control, as is indicated schematically in the drawing, a monitoring circuit in which, for example, a power supply unit Svg for the signal generators mentioned above may be located. As indicated in the drawing, there are normally closed contacts r1 and r2 of the mentioned relays R1 and R2 of the two evaluation devices Us1, Us2 in this monitoring circuit.
  • the excitation circuit mentioned is interrupted when at least one of these two relays is energized, whereupon the voltage supply device Svg can interrupt the voltage supply to the signal transmitters.
  • the microprocessor MP1 is connected with an output connection as12 to an input connection es21 of the microprocessor MP2, which is on the other hand, is connected via an output connection as22 to an input connection es11 of the microprocessor MP1.
  • the microprocessor MP1 is connected with an input terminal es12 to the output terminal am2 of the microprocessor MP2, which is connected with an input terminal es22 to the output terminal am1 of the microprocessor MP1. Control processes are carried out via these connections of the two microprocessors MP1 and MP2, which will be discussed in more detail below.
  • the respective microprocessor MP1 or MP2 emits a clock pulse sequence from its output connection am1 or am2 when the respective actual signal state is recognized as a permissible actual signal state.
  • the respective clock pulse sequence is then fed to the associated evaluation device Us1 or Us2, which does not signal a fault message when such a clock pulse sequence occurs.
  • the above-mentioned comparison processes which the respective microprocessor executes can be carried out between signals indicating the actual signal states on the one hand and test signals indicating unauthorized signal states or test signals merely indicating approved signal states on the other hand.
  • the relevant comparison processes can be carried out with the aid of the arithmetic unit contained in the respective microprocessor.
  • each actual signal state is repeated several times all test signal states compared.
  • the signals indicating the individual actual signal states of the signal transmitters are now not supplied as permanent signals to the corresponding input connections of the microprocessors, but rather these signals are supplied via the pulse-controlled AND gates GUa1 to GUan or GUb1 to GUbn. Accordingly, characteristic pulses for the respective actual signal states occur at the corresponding input connections of the two microprocessors. In contrast, pulse gaps occur between these pulses.
  • the organization may now be such that the microprocessors can also determine the presence of such pulse pauses and, from the non-occurrence of such pulse pauses, can conclude that there is an incorrect transmission path for the signals indicating the actual signal states.
  • the respective microprocessor with a separate test signal for the duration of at least one of the aforementioned pulse pauses.
  • This is done via the shift registers Reg1, Reg2.
  • the shift register Reg1 is associated with the microprocessor MP1 and the shift register Reg2 is associated with the microprocessor MP2.
  • the shift register Reg1 is loaded by the microprocessor MP2 with test signal bits which form the separate test signal and which the microprocessor MP2 may emit from its output connection as21.
  • the shift register Reg2 is loaded in a corresponding manner with test signal bits from the output connection as11 of the microprocessor MP1. The relevant charging processes do not need to be carried out at the same time.
  • the respective reporting signal is recorded and evaluated by the other microprocessor in each case - ie by the microprocessor which previously triggered the test signal.
  • the output connections am1 and am2 of the two microprocessors are connected to the input connection es22 and es12 of the other microprocessor.
  • this microprocessor MP2 may be informed that a test signal is supplied to the microprocessor MP2 between the output terminal as12 of the microprocessor MP1 and the input terminal es21 of the microprocessor MP2.
  • this microprocessor MP1 will be informed via the control line between the output connection as22 of the microprocessor MP2 and the input connection es11 of the microprocessor MP1 that a corresponding test signal has been fed to it on the input side. It is also possible, however, for the respective control microprocessor to be informed via the relevant control lines that it is receiving an output signal to be evaluated from the other microprocessor (at the input connection es12 of the microprocessor MP1 or at the input connection es22 of the microprocessor MP2). . In this way, each of the two microprocessors can be used to monitor whether the other microprocessor generates the associated message signal in response to the test signal supplied to it on the input side.
  • the monitoring microprocessor can issue a corresponding fault message submit and initiate the response of its associated evaluation device.
  • These monitoring measures then ensure particularly reliable monitoring of the signal states of the signal detectors, which emit the signals characteristic of their signal states to the connections Ea1 to Ean and Eb1 to Ebn mentioned.
  • the respective microprocessor sends a corresponding message signal to its associated evaluation device which - since the message signal in question occurs for a sufficiently long time - now responds and thus reports the presence of a fault.
  • the power supply device Svg of the signal transmitters can be switched off, so that the signal transmitters are then de-energized.
  • the signal transmitters it is also possible in this case for the signal transmitters to perform a certain predetermined emergency operation, e.g. a blinking operation.
  • microprocessors MP1, MP2 which the microprocessors execute sequentially have been considered.
  • the microprocessors MP1, MP2 are associated with the program memories ROM1 and ROM2 already mentioned above.
  • the data controlling the execution of the above-mentioned operating processes are stored in these program memories, which the respective microprocessor calls up in succession with the aid of the program step counter contained therein, in order then to carry out corresponding control processes.
  • the pulse-wise actuation of the mentioned AND gates GUa1 to GUan, GUb1 to GUbn from the clock pulse generator Tg takes place in the cycle of an AC mains voltage, which is supplied by a mains AC voltage source that feeds the signal generators.
  • the mentioned AND gates can trigger impulses driving in pulses in a time sequence of 20 ms or 10 ms, for example at bull crossings of the relevant mains alternating voltage.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Optical Communication System (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Traffic Control Systems (AREA)
EP79102540A 1978-08-01 1979-07-18 Circuit de surveillance de l'état de systèmes de signalisation, spécialement de systèmes lumineux de signalisation de circulation routière Expired EP0007579B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT79102540T ATE1305T1 (de) 1978-08-01 1979-07-18 Schaltungsanordnung zur ueberwachung des zustands von signalanlagen, insbesondere von strassenverkehrs-lichtsignalanlagen.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2833761 1978-08-01
DE2833761A DE2833761C3 (de) 1978-08-01 1978-08-01 Schaltungsanordnung zur Überwachung des Zustands von Signalanlagen, insbesondere von Straßenverkehrs-Lichtsignalanlagen

Publications (2)

Publication Number Publication Date
EP0007579A1 true EP0007579A1 (fr) 1980-02-06
EP0007579B1 EP0007579B1 (fr) 1982-06-30

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EP79102540A Expired EP0007579B1 (fr) 1978-08-01 1979-07-18 Circuit de surveillance de l'état de systèmes de signalisation, spécialement de systèmes lumineux de signalisation de circulation routière

Country Status (4)

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US (1) US4290136A (fr)
EP (1) EP0007579B1 (fr)
AT (1) ATE1305T1 (fr)
DE (2) DE2833761C3 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0137964A2 (fr) * 1983-10-17 1985-04-24 Stührenberg, Rolf Dispositif pour la fiabilité du signal dans les agencements de feu de signalisation
EP0172454A1 (fr) * 1984-08-01 1986-02-26 Siemens Aktiengesellschaft Dispositif de contrôle pour installations de feux de signalisation
DE19716576C1 (de) * 1997-04-21 1999-01-07 Stuehrenberg Gmbh Elektrobau S Verfahren zur Verkehrssignalsteuerung
DE19848405C2 (de) * 1997-04-21 2002-10-10 Stuehrenberg Gmbh Elektrobau S Verfahren zur Verkehrssignalsteuerung

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2150372B (en) * 1983-11-25 1986-12-10 Ferranti Plc Lamp failure detector
DE3346009A1 (de) * 1983-12-20 1985-06-27 Müller Verkehrstechnik GmbH, 7306 Denkendorf Lichtsignalsteuersystem fuer verkehrssignalanlagen
DE3682729D1 (de) * 1985-09-05 1992-01-16 Philips Nv Ueberwachung eines konfliktdetektors fuer verkehrsampeln.
AU604804B2 (en) * 1985-09-05 1991-01-03 Adt Services Ag Improvements in and relating to conflict monitor systems
DE3541549A1 (de) * 1985-11-25 1987-05-27 Stuehrenberg Rolf Verfahren und vorrichtung zur signalsicherung in lichtzeichenanlagen
EP0287991B1 (fr) * 1987-04-21 1991-09-18 Siemens Aktiengesellschaft Montage de circuit pour le test automatique du fonctionnement d'un dispositif de contrôle
FR2647932B1 (fr) * 1989-06-02 1991-09-06 Forclum Force Lumiere Elect Dispositif de telesurveillance de feux de carrefour et procede de mise en service d'un tel dispositif
DE3930877C1 (en) * 1989-09-15 1990-10-18 Stuehrenberg Gmbh, 4930 Detmold, De Traffic signal system safety circuit - has two processors receiving signal state combinations for checking their reliability
US5173691A (en) * 1990-07-26 1992-12-22 Farradyne Systems, Inc. Data fusion process for an in-vehicle traffic congestion information system
US5182555A (en) * 1990-07-26 1993-01-26 Farradyne Systems, Inc. Cell messaging process for an in-vehicle traffic congestion information system
US5164904A (en) * 1990-07-26 1992-11-17 Farradyne Systems, Inc. In-vehicle traffic congestion information system
US20060074546A1 (en) * 1999-04-19 2006-04-06 Dekock Bruce W System for providing traffic information
US6466862B1 (en) * 1999-04-19 2002-10-15 Bruce DeKock System for providing traffic information
US7908080B2 (en) 2004-12-31 2011-03-15 Google Inc. Transportation routing
US8717181B2 (en) 2010-07-29 2014-05-06 Hill-Rom Services, Inc. Bed exit alert silence with automatic re-enable
WO2016018936A1 (fr) 2014-07-28 2016-02-04 Econolite Group, Inc. Contrôleur de signal de trafic auto-configurable
EP2995242B1 (fr) 2014-09-11 2023-11-15 Hill-Rom S.A.S. Appareil de support de patient

Citations (3)

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US3629802A (en) * 1968-07-18 1971-12-21 Gulf & Western Industries Conflicting phase error detector
US3778762A (en) * 1971-07-23 1973-12-11 Solid State Devices Inc Monitor for detecting conflicting traffic control signals
US3902156A (en) * 1974-10-07 1975-08-26 Gulf & Western Industries Multi-channel ac conflict monitor

Family Cites Families (2)

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US3988670A (en) * 1975-04-15 1976-10-26 The United States Of America As Represented By The Secretary Of The Navy Automatic testing of digital logic systems
US4084262A (en) * 1976-05-28 1978-04-11 Westinghouse Electric Corporation Digital monitor having memory readout by the monitored system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3629802A (en) * 1968-07-18 1971-12-21 Gulf & Western Industries Conflicting phase error detector
US3778762A (en) * 1971-07-23 1973-12-11 Solid State Devices Inc Monitor for detecting conflicting traffic control signals
US3902156A (en) * 1974-10-07 1975-08-26 Gulf & Western Industries Multi-channel ac conflict monitor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0137964A2 (fr) * 1983-10-17 1985-04-24 Stührenberg, Rolf Dispositif pour la fiabilité du signal dans les agencements de feu de signalisation
EP0137964A3 (fr) * 1983-10-17 1987-09-23 Stührenberg, Rolf Dispositif pour la fiabilité du signal dans les agencements de feu de signalisation
EP0172454A1 (fr) * 1984-08-01 1986-02-26 Siemens Aktiengesellschaft Dispositif de contrôle pour installations de feux de signalisation
DE19716576C1 (de) * 1997-04-21 1999-01-07 Stuehrenberg Gmbh Elektrobau S Verfahren zur Verkehrssignalsteuerung
DE19848405C2 (de) * 1997-04-21 2002-10-10 Stuehrenberg Gmbh Elektrobau S Verfahren zur Verkehrssignalsteuerung

Also Published As

Publication number Publication date
DE2833761A1 (de) 1980-02-14
DE2963235D1 (en) 1982-08-19
DE2833761C3 (de) 1981-12-03
EP0007579B1 (fr) 1982-06-30
DE2833761B2 (de) 1981-02-12
US4290136A (en) 1981-09-15
ATE1305T1 (de) 1982-07-15

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