EP0000863B1 - Résistance semiconductrice intégrée à compensation de température - Google Patents

Résistance semiconductrice intégrée à compensation de température Download PDF

Info

Publication number
EP0000863B1
EP0000863B1 EP78100173A EP78100173A EP0000863B1 EP 0000863 B1 EP0000863 B1 EP 0000863B1 EP 78100173 A EP78100173 A EP 78100173A EP 78100173 A EP78100173 A EP 78100173A EP 0000863 B1 EP0000863 B1 EP 0000863B1
Authority
EP
European Patent Office
Prior art keywords
resistor
voltage
temperature
resistance
epitaxial layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP78100173A
Other languages
German (de)
English (en)
Other versions
EP0000863A1 (fr
Inventor
David Leo Bergeron
Geoffrey Brownell Stephens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0000863A1 publication Critical patent/EP0000863A1/fr
Application granted granted Critical
Publication of EP0000863B1 publication Critical patent/EP0000863B1/fr
Expired legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802—Resistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
    • G05D23/00—Control of temperature
    • G05D23/19—Control of temperature characterised by the use of electric means
    • G05D23/1906—Control of temperature characterised by the use of electric means using an analogue comparing device
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
    • G05D23/00—Control of temperature
    • G05D23/19—Control of temperature characterised by the use of electric means
    • G05D23/20—Control of temperature characterised by the use of electric means with sensing elements having variation of electric or magnetic properties with change of temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H01L27/0211—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique adapted for requirements of temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the invention relates to a temperature-compensated integrated semiconductor resistor according to the preamble of claim 1.
  • TCR resistance temperature coefficient
  • US Pat. No. 3,683,306 describes a method by which the resistance temperature coefficient is to be brought to zero by using the ion implantation agent to cause structural damage in the region into which the integrated semiconductor resistor is to be introduced.
  • Temperature sensors that convert a temperature applied to them into another physical quantity, for example a voltage, are also known per se.
  • a temperature sensor is known from the magazine "Electronics", vol. 48, dated January 23, 1975., pages 79 to 83, which has an NPN transistor and a diffused-in resistor. In this transistor resistor arrangement, temperature changes are converted into base-emitter voltage changes. Since it is a thermocouple for the measurement of effective values of voltages over a wide frequency range as well as the power and gain of amplifiers, this element is not optimized as a temperature sensor to compensate for the temperature response of integrated resistors and therefore cannot be used directly.
  • the invention seeks to remedy this situation by providing improved resistance / temperature compensation which overcomes the disadvantages mentioned, i.e. Complexity of the manufacturing process, limitation of the resistance range, as well as limitation of the resistance / temperature compensation range, avoided.
  • the invention therefore has the advantage that normal, uncomplicated processes can be used to produce an integrated, temperature-compensated semiconductor resistor.
  • resistance values can be generated over a wide range, which can also be compensated for in wide temperature ranges.
  • the resistance of a resistor made by ion implantation or diffusion is a function of the temperature at which it is operated.
  • the temperature compensation circuit shown here is based on the knowledge that the resistance of such a resistor is also a function of the potential difference between the connection of the resistor which carries the highest positive potential and the epitaxial layer itself. Temperature compensation is effected in that a temperature sensor is connected to the epitaxial layer, which carries an output voltage which changes in the opposite direction to the resistance temperature coefficient of the resistor. Therefore, the total change in resistance of the considered resistance produced by ion implantation or diffusion approaches zero over a wide range of temperature fluctuations.
  • FIG. 1 shows an N-type epitaxial semiconductor layer 4 which is applied to a P-type substrate 2.
  • the P-doped contact regions are shown at 6 and 10, the resistor 8 made of P-doped material being located between them in the epitaxial layer.
  • Resistor 8 is shown as a resistor manufactured by ion implantation, although the principle of the invention is also applicable to resistors made according to other principles for which resistance temperature compensation is desired; i.e. a resistor diffused into the epitaxial layer Ep can also be used instead of the resistor made by ion implantation.
  • the resistance of the resistance 8 produced by means of ion implantation increases with increasing temperature. In order to compensate for this increase in resistance, it must be ensured that the resistance voltage coefficient of the potential difference between the epitaxial layer 4 and the resistor 8 brings about an equal and opposite change in resistance of the resistor 8.
  • the PN barrier layer, which surrounds the resistor 8 in the epitaxial layer 4, has a depletion zone, the thickness of which decreases as the potential difference between the resistor 8 and the epitaxial layer 4 decreases.
  • a temperature sensor 24 is connected to the epitaxial layer 4 via a contact 12 and an aluminum contact 22, the circuit mentioned lowering its output voltage V EPI as the temperature of its surroundings rises. As is known in itself, contacts are also attached at positions 18 and 20. By lowering the potential V EPI with increasing temperature, the desired resistance compensation for the resistor 8 is therefore brought about.
  • the temperature sensor 24 consists of two voltage dividers connected in parallel, which are connected between a voltage + V cc and ground.
  • the partial resistors 30 and 32 form a voltage divider with a tap, which is connected to the base of an NPN transistor 26.
  • the second voltage divider consists of a partial resistor 28 and the NPN transistor 26, whose common connection point is also the output node of the circuit for generating the voltage V epi .
  • the voltage drop between V CR and the base of NPN transistor 26 is determined using the constant magnitude of V cc and the constant. Ratio of resistors 30 and 32 kept constant. In this way, the base-emitter voltage of the NPN transistor 26 is kept constant. However, the PN junction at the emitter-base junction of the NPN transistor 26 changes its current flow characteristic with the change in the ambient temperature.
  • the potential difference between the resistor 8 and the epitaxial layer 4 is reduced in order to achieve a reduction in resistance in accordance with the resistance voltage coefficient of the transistor. Since both the resistor and the epitaxial layer are positively biased with respect to the resistor, the epitaxial layer 4 must be forced to change the voltage drifting into the negative in order to reduce the resistance value of the resistor 8 (V EPI > V ⁇ in FIG. 1). In order to generate a voltage drifting into the negative, the temperature sensor 24 must generate a negative change in the voltage V EPI with increasing temperature.
  • Fig. 2 shows a graphical representation of the resistance temperature coefficient versus the resistance of the layer for resistors manufactured by ion implantation, for a certain group of process conditions over a wide range of the ion implantation dose, which result in sheet resistances of 100 ohms per area element to 5000 ohms per area element.
  • the resistance temperature coefficient extends over a range of approximately 1100 parts per million and per degree Celsius (ppm / ° C) to over 4000 ppm / ° C for this range of sheet resistance.
  • Other curves with higher or lower resistance temperature coefficients can be achieved by changing the set of process conditions, in particular the implantation energy, the oxide thickness, the background concentration (epitaxy) and the heating duration and temperature of the heating step downstream of the implantation.
  • a resistance with a sheet resistance of 5000 ohms per surface element has a resistance temperature coefficient of about 4000 ppm / ° C. Therefore, a resistor whose resistance value is 10,000 ohms at 25 ° C, have a resistance of 10000 + 10000 x 4000 x 10 6 x (75-25) and 12, 000 Ohm at 75 ° C.
  • FIG. 3 shows a graphical representation of the resistance voltage coefficient (VCR) over the nominal sheet resistance, for a resistor manufactured according to the same process conditions as that explained in connection with FIG. 2.
  • the change in resistance with the voltage depends on the charge carrier depletion along the PN barrier layer, which is formed between the resistance region and the oppositely doped epitaxial layer.
  • the thickness of the region depleted of charge carriers is a function of the doping concentration on both sides of the barrier layer and the potential difference (electric field) between both sides of the barrier layer.
  • V eff The potential (bias) across the junction is both a function of the potential applied to the epitaxial layer relative to the positive end of the resistor and the potential applied to both ends of the resistor.
  • V eff The total effect of these two potentials can be expressed as a combined effective voltage (V eff ), which can be recorded in the following algebraic expression:
  • This voltage can be viewed as the mean potential difference across the resistance epitaxial barrier.
  • a resistance of 5000 ohms per surface element at 25 ° C has a TCR of 4000 ppm / ° C and a VCR of 10,000 ppm / V, then it has approximately a constant value of 25 ° C to 75 ° C if the Biasing the epitaxial layer against the positive end of the resistance is set from 30 volts at 25 ° C to 10 volts at 75 ° C.
  • the bias voltage on the epitaxial layer is set by the temperature sensor 24 shown in FIG. 1, which is attached in the immediate vicinity of the resistor, the temperature of which is then to be compensated, so that the temperature of the resistor is the same or almost the same, like the temperature of temperature 24.
  • Examples of other possible realizations of the compensation of the temperature response can be seen in that a P-zone within an N-epitaxial layer and the epitaxial layer are used to form a resistance whose temperature change is compensated for by changes in the depletion zone, which are reversed by those biased P-zone is formed.
  • a resistor is formed by placing a P-zone in an N-epitaxial layer, such as one used to make a transistor base zone overlapped by a narrower N + -zone, such as one is the case that is used to form a transistor emitter region. It is a so-called pinch resistor.
  • the compensation of the temperature response of the P resistor is achieved in that the opposite bias voltage at the N + zone and the epitaxial layer with respect to the P resistor standing zone is varied.
  • the exemplary embodiment explained in detail can be expanded by compensating for a plurality of resistors in a common epitaxial layer, only this one temperature sensor being used with the compensation circuit according to FIG. 1.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Automation & Control Theory (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)

Claims (4)

1. Résistance semi-conductrice intégrée à compensation de température comportant une région de résistance d'un type de conductivité dans une couche épitaxique du type de conductivité opposée, munie de contacts électriques espacés les uns des autres, caractérisée en ce que l'un des contacts électriques (18; Figure 1) est à un potential de référence, la résistance (8) a un coefficient positif de résistance par rapport à la tension (VCR) et un coefficient prédéterminé de résistance par rapport à la température (TCR), un détecteur de température (24) est connecté au circuit intégré très près, de la résistance, sa borne de tension de sortie étant connectée à la couche épitaxique (4) et sa borne d'alimentation de tension étant connectée à un potential de référence, et en ce que la caractéristique de tension de sortie du détecteur de température, par rapport à la température sur sa borne de sortie, varie inversement par rapport au coefficient de résistance par rapport à la tension de la résistance de telle sorte que les variations de résistance de ladite résistance en fonction de la température peuvent être compensées par les variations de tension provoquées par le détecteur de température sur la couche épitaxique.
2. Résistance semi-conductrice intégrée à température compensée selon la revendication 1, caractérisée en ce que le détecteur de température (24), connecté par sa borne de sortie à la couche épitaxique (4) à travers un premier contact (22, 12), est composé de deux diviseurs de tension (26, 28; 30, 32) montés en parallèle, le premier diviseur de tension étant composé d'une résistance partielle (28) et d'une résistance contrôlée (26) à caractéristique de température négative, dont l'électrode de commande est connectée à la prise du second diviseur de tension entre ses résistances partielles (30, 32), et en ce que la borne de tension de sortie est identique à la prise du premier diviseur de tension entre la résistance contrôlée (26) et la résistance partielle (28), et la tension d'alimentation (Vcc) est branchée sur la connexion entre les deux résistances partielles (28, 30) des deux diviseurs de tension.
3. résistance semi-conductrice intégrée à température compensée selon la revendication 2, caractérisée en ce que la résistance contrôlée (26) est formée d'un transistor NPN dont la tension d'émetteur-base est maintenue constante par une chute de tension constante entre la tension d'alimentation (Vcc) et la base du transistor, résultant d'une tension d'alimentation constante et d'un rapport fixe des résistances partielles (30, 32) du second diviseur de tension, de sorte que le flux de courant à travers la couche d'appauvrissement PN entre l'émetteur et la base du transistor varie avec la température, entraînant ainsi la variation du flux de courant à travers la résistance partielle (28) du premier diviseur de tension et en conséquence de la valeur de la tension de couche épitaxique (Vepi) fournie à la couche épitaxique par la borne de sortie du détecteur de température.
4. Résistance semi-conductrice intégrée à température compensée selon l'une quelconque ou plusieurs des revendications 1 à 3, caractérisée en ce que plusieurs résistances semiconductrices (11) formées selon la revendication 1, peuvent être simultanément compensées en fonction de la température dans leur valeurs respectives de résistance par un détecteur de température (24) connecté comme spécifié dans la revendication 2.
EP78100173A 1977-08-18 1978-06-15 Résistance semiconductrice intégrée à compensation de température Expired EP0000863B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/825,759 US4229753A (en) 1977-08-18 1977-08-18 Voltage compensation of temperature coefficient of resistance in an integrated circuit resistor
US825759 1977-08-18

Publications (2)

Publication Number Publication Date
EP0000863A1 EP0000863A1 (fr) 1979-03-07
EP0000863B1 true EP0000863B1 (fr) 1981-07-15

Family

ID=25244865

Family Applications (1)

Application Number Title Priority Date Filing Date
EP78100173A Expired EP0000863B1 (fr) 1977-08-18 1978-06-15 Résistance semiconductrice intégrée à compensation de température

Country Status (4)

Country Link
US (1) US4229753A (fr)
EP (1) EP0000863B1 (fr)
JP (1) JPS5432989A (fr)
DE (1) DE2860835D1 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2825794C2 (de) * 1978-06-13 1986-03-20 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Abschaltbarer Thyristor
JPS5799765A (en) * 1980-12-12 1982-06-21 Fujitsu Ltd Semiconductor resistance element
DE3139556A1 (de) * 1981-10-05 1983-04-21 Philips Patentverwaltung Gmbh, 2000 Hamburg Schaltungsanordnung zur messung von temperaturen
DE3539402A1 (de) * 1985-11-07 1987-05-21 Rohde & Schwarz Leistungsmesssensor zum messen von hochfrequenzleistung
JPH0693485B2 (ja) * 1985-11-29 1994-11-16 日本電装株式会社 半導体装置
US4990987A (en) * 1986-12-18 1991-02-05 Gte Products Corporation Over-temperature sensor and protector for semiconductor devices
JPH0653417A (ja) * 1992-05-19 1994-02-25 Texas Instr Inc <Ti> 抵抗器回路およびそれを形成する方法
US6548840B1 (en) * 2000-04-03 2003-04-15 Hrl Laboratories, Llc Monolithic temperature compensation scheme for field effect transistor integrated circuits
SE516411C2 (sv) * 2000-05-26 2002-01-15 Ericsson Telefon Ab L M Anordning för att kompensera variationer hos ett motstånds ytresistans på ett chips
KR100404748B1 (ko) * 2001-01-20 2003-11-14 박경숙 레버형 도어록
US7253074B2 (en) * 2004-11-05 2007-08-07 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Temperature-compensated resistor and fabrication method therefor
KR100854463B1 (ko) 2007-05-21 2008-08-27 주식회사 하이닉스반도체 온도센서회로 및 이를 이용한 반도체 메모리 장치
US8093956B2 (en) * 2009-01-12 2012-01-10 Honeywell International Inc. Circuit for adjusting the temperature coefficient of a resistor
US9595518B1 (en) 2015-12-15 2017-03-14 Globalfoundries Inc. Fin-type metal-semiconductor resistors and fabrication methods thereof

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3017520A (en) * 1960-07-01 1962-01-16 Honeywell Regulator Co Integral transistor-thermistor and circuit using same for compensating for changing transistor temperature
US3484658A (en) * 1966-08-25 1969-12-16 Nippon Telegraph & Telephone Temperature compensated semiconductor resistor
US3700977A (en) * 1971-02-17 1972-10-24 Motorola Inc Diffused resistor
US3936789A (en) * 1974-06-03 1976-02-03 Texas Instruments Incorporated Spreading resistance thermistor
US4005471A (en) * 1975-03-17 1977-01-25 International Business Machines Corporation Semiconductor resistor having a high value resistance for use in an integrated circuit semiconductor device
US4075649A (en) * 1975-11-25 1978-02-21 Siemens Corporation Single chip temperature compensated reference diode and method for making same
US4053915A (en) * 1976-03-22 1977-10-11 Motorola, Inc. Temperature compensated constant current source device
FR2351505A1 (fr) * 1976-05-13 1977-12-09 Ibm France Procede de correction du coefficient en tension de resistances semi-conductrices, implantees ou diffusees
US4044371A (en) * 1976-09-29 1977-08-23 Honeywell Inc. Plurality of precise temperature resistors formed in monolithic integrated circuits
US4132998A (en) * 1977-08-29 1979-01-02 Rca Corp. Insulated gate field effect transistor having a deep channel portion more highly doped than the substrate

Also Published As

Publication number Publication date
JPS5432989A (en) 1979-03-10
JPS5635029B2 (fr) 1981-08-14
US4229753A (en) 1980-10-21
EP0000863A1 (fr) 1979-03-07
DE2860835D1 (en) 1981-10-22

Similar Documents

Publication Publication Date Title
DE2854901C2 (de) Integrierte Konstantspannungsgenerator-Schaltung
DE2143029C3 (de) Integrierte Halbleiterschutzanordnung für zwei komplementäre Isolierschicht-Feldeffekttransistoren
DE2351732C2 (de) Schaltungsanordnung zum Schutz eines Leistungstransistors vor Überlastung
DE2951835C2 (fr)
EP0000863B1 (fr) Résistance semiconductrice intégrée à compensation de température
DE2559360A1 (de) Halbleiterbauteil mit integrierten schaltkreisen
DE2505573C3 (de) Halbleiterschaltungsanordnung mit zwei Isolierschicht-Feldeffekttransistoren
DE1283399B (de) Feldeffekt-Transistor mit zwei ohmschen Elektroden und mit einer isolierten Steuerelektrode
DE1090331B (de) Strombegrenzende Halbleiteranordnung, insbesondere Diode, mit einem Halbleiterkoerper mit einer Folge von wenigstens vier Zonen abwechselnd entgegengesetzten Leitfaehigkeitstyps
DE3228574A1 (de) Referenzspannungsgenerator
WO1983002528A1 (fr) Circuit darlington a transistors
DE69320749T2 (de) Strommessschaltung
DE202015105413U1 (de) Integrierte, floatende Diodenstruktur
DE1589707B2 (de) Temperaturkompensierte Z Diodenanord nung
DE2300116A1 (de) Hochfrequenz-feldeffekttransistor mit isolierter gate-elektrode fuer breitbandbetrieb
DE2832154A1 (de) Halbleitervorrichtung mit isoliertem gate
EP0047392B1 (fr) Commutateur haute-tension à semiconducteur
DE2635218A1 (de) Anordnung zum schutz eines transistors
DE2116106A1 (de) Inverser Transistor
DE69623265T2 (de) Emitterballast ueberbrueckung für radiofrequenz-leistungstransistoren
DE2513893C2 (de) Transistorverstärker
DE1075746B (de) Vorrichtung zur Temperaturkompensation eines Flächentransistors
DE2263075A1 (de) Monolithische integrierte halbleiteranordnung
EP0179099B1 (fr) Dispositif semiconducteur monolithique integre et procede pour sa fabrication
DE2541887C3 (de) Monolithisch integrierte Halbleiterschaltung mit einer I2 L- Konfiguration

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): DE FR GB

17P Request for examination filed
GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 2860835

Country of ref document: DE

Date of ref document: 19811022

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19840605

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19840619

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19890531

Year of fee payment: 12

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19900228

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19900301

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19900615

GBPC Gb: european patent ceased through non-payment of renewal fee
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT