EA004072B1 - A device for encoding/decoding n-bit source words into corresponding m-bit channel words, and vice versa - Google Patents

Abstract

1. A device for encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal, wherein the bit stream of the source signal is divided into n-bit source words, which device comprises converting means adapted to convert said source words into corresponding m-bit channel words, characterized in that each value of the n-bit source words together with another value of the n-bit source words forms a pair of source words, the values of the source words of said pair of n-bit source words differ in the bit values of the q<TH> bits in the n-bit source words, q being a constant, the pairs of n-bit source words being subdivided into a first part and a remaining part, and the converting means are adapted to convert n-bit source words into m-bit channel words, in such a manner that the conversion of the two source words forming a pair of source words of the first part of the pairs of n-bit source words is parity preserving and the conversion of the two source words forming a pair of source words of the remaining part of the pairs of n-bit source words is parity inverting. 2. A device as claimed in claim 1, characterized in that the converting means are adapted to convert a block of p consecutive n-bit source words into a corresponding block of p consecutive m-bit channel words, where n, m and p are integers, m>n>=2, p<=1, and where p can vary. 3. A device as claimed in claim 2, characterized in that m=n+1. 4. A device as claimed in claim 3, characterized in that n=2. 5. A device as claimed in claim 4, characterized in that the device is adapted to convert single source words into corresponding single channel words in accordance with the following Table: Source word Channel word SW1 00 SW1 101 SW2 01 SW2 100 SW3 10 SW3 000 SW4 11 SW4 001 6. A device as claimed in claim 4 or 5, wherein the converting means are adapted to convert 2-bit source words into corresponding 3-bit channel words, so as to obtain a channel signal in the form of a (d,k) sequence, where d=1, the device further comprising means for detecting the position in the bit stream of the source signal where encoding of single 2-bit source words into corresponding single channel words would lead to a violation of the d-constraint at the channel word boundaries and for supplying a control signal in response to said detection, characterized in that, in the absence of the control signal, the converting means are adapted to convert single 2-bit source words into corresponding single 3-bit channel words. 7. A device as claimed in claim 6, wherein, in the presence of the control signal, which occurs during the conversion of two consecutive source words, the converting means are adapted to convert a block of said two consecutive 2-bit source words into a block of two corresponding 3-bit channel words, in such a manner that one of the two source words in the block of source words is converted into a 3-bit channel word which is not identical to one of the four channel words CW1 to CW4, in order to preserve the d=1 constraint, characterized in that, in the presence of said control signal, the converting means are further adapted to convert the block of said two subsequent 2-bit source words into a corresponding block of two subsequent 3-bit channel words,. 8. Device as claimed in claim 1 or 7, characterized in that the converting means are adapted to convert blocks of two consecutive 2-bit source words into blocks of two consecutive 3-bit channel words in accordance with the coding given in the following Table: Block of 2 source words Block of 2 channel words 00 00 100 010 00 01 101 010 11 00 000 010 11 01 001 010 9. A device as claimed in claim 6, 7 or 8, where k has a value larger than 5, the device being further having means for detecting the position in the bit stream of the source signal where encoding of single 2-bit source words into single 3-bit channel words would lead to a violation of the k-constraint and for supplying a second control signal in response to said detection, characterized in that, in the presence of the second control signal, which occurs during the conversion of three consecutive 2-bit source words, the converting means are adapted to convert a block of said three consecutive 2-bit source words into a block of corresponding three consecutive 3-bit channel words, the converting means are further adapted to convert two of the three source words in the block into corresponding 3-bit channel words not identical to the four channel words CW1 to CW4, in order to preserve the k constraint. 10. A device as claimed in claim 1 or 9, characterized in that the converting means are adapted to convert blocks of three consecutive 2-bit source words into blocks of three consecutive 3-bit channel words in accordance with the coding given in the following Table: Block of 3 source words Block of 3 channel words 10 10 10 000 010 010 10 10 11 001 010 010 01 10 11 101 010 010 01 10 10 100 010 010 11. A device as claimed in any one of the preceding claims, characterized in that the conversion means are adapted to perform a signal processing operation upon the binary source signal, which operation is equivalent to the conversion of consecutive source words into consecutive channel words, followed by an aT-precoding of said channel words. 12. A device as claimed in claim 1 or 11, characterized in that it further comprises bit-adding means for adding one bit to subsequent blocks of r bits of the source signal. 13. A device as claimed in any one of the preceding claims, characterized in that it further comprises means for recording the stream of data bits of the binary channel signal in a track on the record carrier. 14. A method of encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal, wherein the bit stream of the source signal is divided into n-bit source words, the method comprising the step of converting said source words into corresponding m-bit channel words, characterized in that each value of the n-bit source words together with another value of the n-bit source words forms a pair of source words, the values of the source words of said pair of n-bit source words differ in the bit values of the q<TH> bits in the n-bit source words, q being a constant, the pairs of n-bit source words being subdivided into a first part and a remaining part, and the converting step comprises the conversion of n-bit source words into m-bit channel words, in such a manner that the conversion of both the two source words forming a pair of source words of the first part of the pairs of n-bit source words is parity preserving and the conversion of the two source words forming a pair of source words of the remaining part of the pairs of n-bit source words is parity inverting. 15. A record carrier provided with a binary channel signal, which binary channel signal has been obtained by conversion of a corresponding binary source signal, wherein the bit stream of the binary channel signal has been divided into m-bit channel words, the binary source signal has been divided into n-bit source words and the m-bit channel words have been obtained by conversion of the n-bit source words into corresponding m-bit channel words, characterized in that each value of the n-bit source words together with another value of the n-bit source words forms a pair of source words, the values of the source words of said pair of n-bit source words differ in the bit values of the q<TH> bits in the n-bit source words, q being a constant, the pairs of n-bit source words being subdivided into a first part and a remaining part, the conversion of the n-bit source words into m-bit channel words being such that the conversion of the two source words forming a pair of source words of the first part of the pairs of n-bit source words is parity preserving and the conversion of the two source words forming a pair of source words of the remaining part of the pairs of n-bit source words is parity inverting. 16. A record carrier provided with a 1T-precoded channel signal, which 1T-precoded channel signal has been obtained by 1T-precoding of a binary channel signal, which binary channel signal has been obtained by conversion of a corresponding binary source signal, wherein the bit stream of the binary channel signal has been divided into m-bit channel words, the binary source signal has been divided into n-bit source words and the m-bit channel words have been obtained by conversion of the n-bit source words into corresponding m-bit channel words, characterized in that each value of the n-bit source words together with another value of the n-bit source words forms a pair of source words, the values of the source words of said pair of n-bit source words differ in the bit values of the q<TH> bit in the n-bit source words, q being a constant, the pairs of n-bit source words being subdivided into a first part and a remaining part, the conversion of the n-bit source words into m-bit channel words being such that the conversion of the two source words forming a pair of source words of the first part of the pairs of n-bit source words is parity preserving and the conversion of the two source words forming a pair of source words of the remaining part of the pairs of n-bit source words is parity inverting. 17. A device for decoding a stream of data bits of a binary channel signal into a stream of data bits of a binary source signal, wherein the bit stream of the channel signal is divided into m-bit channel words, which device comprises deconverting means adapted to deconvert m-bit channel words into corresponding n-bit source words, characterized in that each value of the n-bit source words together with another value of the n-bit source words forms a pair of source words, the values of the source words of said pair of n-bit source words differ in the bit values of a q<TH> bit in the n-bit source words, q being a constant, the pairs of n-b

Description

The invention relates to a device and to a method of encoding a stream of information bits of a binary source signal into a stream of information bits of a binary signal in a transmission channel in which the bit stream of the source signal is divided into η-bit source words, and the device contains conversion means thus which converts the specified source words to the corresponding t-bit words of the transmission channel. The invention also relates to a recording medium and to a decoding device of a stream of information bits of a binary signal of a transmission channel obtained by a coding device, to obtain a stream of information bits of a source binary signal.

The aforementioned coding device is known from the book KA Schuhamera Imming Coding Methods for Digital Recording Devices, chapter 5.6.7, pp. 127-131, Prentice Hall, 1991 (Sobshchd 1ss1shk | ie5 £ from ίΐβίΐαΐ tesotbegue by LU KA 8cblobateg 1t1pk, ebar1eg 5.6.7, pp. 127 1о 131, Rtebbse Na11 (1991)). The book describes a coding device that generates (b, c) a sequence that satisfies the following parameters: the transmission rate is 2/3, (1.7), a similar coding device is also proposed in US Pat. No. 4,337,458 Cohn et al. (Sop ! a1.). The known coding scheme has the disadvantage of having a constant signal level, which may become excessively large and, therefore, introduces distortions in communication systems that cannot process the DC component, as well as distortions in any recording of data on magnetic media.

The object of the invention is to create such a device for encoding p-bit source words into corresponding t-bit words of the transmission channel so that the device itself does not generate a constant component of the signal in the transmission channel, but it additionally provides this possibility by taking additional measures, as well as would provide the possibility of implementing the transmission channel signal in the form of (b, c) sequence.

The device according to the invention is characterized in that each value of n-bit source words together with a different value of the digit source words forms a pair of source words, and the meanings of the source words of the specified pair of n-bit source words differ from each other in the bit value in the | -bit source words, where the value of c. | is a constant, pairs of initial words are subdivided into the first part and the rest, and the conversion tool is made so that it converts the n-bit source words to the t-bit words of the transmission channel in such a way that the two source words that form a pair of source words from the first part of pairs of n-bit source words, carry out with parity preservation, and the transformation of two source words, which form a pair of source words from the rest of the pairs of digit initial words, ie parity inversion.

The term “parity preserving” means that the converted n-bit source words have the same parity as the parity (after adding modulo 2) the corresponding t-bit words of the transmission channel into which they are converted. The term with parity inversion means that the converted bit words have parity that is inverse to parity (after adding modulo 2) the corresponding t-bit words of the transmission channel into which they are converted. As a result, a one-to-one relationship can be obtained between the parity of two source words from a pair and the parity of the corresponding transmission channel words, which allows effective control of the constant component of the binary signal of the transmission channel after pre-AT coding.

The coding device according to the invention can be used in conjunction with a bit addition device, in which 1 bit is added to the code words of a certain length. The received signal can be fed to the encoding device of the present invention. The signal of the transmission channel from the encoding device is fed to the 1T-precoding device. The purpose of the bit addition device is to add bit 0 or bit 1 to the data blocks in the input signal of the conversion device to produce a signal at the output of the pre-coding device that does not have a DC component or which contains a tracking control signal having a certain frequency. The output signal of the pre-coding device is recorded on a recording medium. The addition of 1 bit to code words of a certain length is carried out so that this bit is in place of the. | -Th discharge of the η-bit source words supplied to the conversion device. In this way, two different p-bit source words can be obtained. P-bit source words obtained in a similar way differ only in the value of the bit in the c. | -Th bit. These two η-bit source words form a pair of n-bit source words. In the case when the conversion of the specified pair of source words is carried out with parity preserved, adding bit 0 to the signal applied to the input of the conversion device results in retaining the same polarity in the output signal of the preliminary 1T coding device, and adding bit 1 leads to the presence of reverse polarity in the output of the device 1T-coding. In the case when the conversion of the specified pair of source words is performed with parity inversion, adding bit 0 to the signal that is fed to the input of the conversion device results in the reverse polarity in the output signal of the 1T encoding device, and adding bit 1 causes the polarity The output of the 1T precoder remains the same. Therefore, the conversion device acts on the output signal of the 1T pre-coding device so that it is possible to control the current value of the difference between the number of zeros and ones in the digital output signal of the 1T-pre-coding device so that its dependence on time has the required form.

In a preferred embodiment, the device according to the invention is characterized in that the conversion tool is designed in such a way that it converts a block from p consecutive η-bit source words to a corresponding block from p consecutive t-bit words of the transmission channel, where η, t and p are integers numbers, m> n> 2, p> 1, and where p can take different values.

In the preferred embodiment, m is equal to n + 1, and n is equal to 2. Below, it will become clear that in the case when n = 2, the device according to the invention, together with the additional measures taken, can be used to generate transmission channel signals in the form (x, k a) sequence where n = 1. At higher values of n, the generation (1, k) of the sequence is impossible. In addition, the presence of n = 2, meaning that two-digit source words are converted into three-digit transmission channel words, results in an increase of 50% in the number of bits in the transmission channel signal created by this device.

Various transformations of two-digit source words into three-digit transmission channel words are possible, in which pairs of one-digit source words either preserve parity, or parity inversion takes place. One of these transformations is the subject of claim 5. However, it should be noted that various permutations of the channel codes listed in the table are possible, the total number of which is 8.

The invention proposes a device in which the conversion tool is designed in such a way that it converts two-digit source words into the corresponding three-digit transmission channel words to obtain a transmission channel signal in the form (s, k) of a sequence, where d = 1, and the device additionally contains a means of detecting the location in the bit stream of the original signal, in which the encoding of single two-digit source words into the corresponding single words of the transmission channel pr leads to violation of the limitation on s at the limits of the word of the transmission channel, and carrying out the issuance of a control signal in response to the indicated detection, and which may additionally differ in that the conversion tool is designed in such a way that, in the absence of a control signal, it converts single two-digit source words to corresponding single three-digit transmission channel words.

The device, in particular, is characterized in that the conversion tool is additionally designed in such a way that, if the specified control signal is present, it performs the conversion of a block consisting of these two consecutive two-digit source words into a corresponding block of two consecutive three-digit transmission channel words.

The possibility of converting one (for example, the second) of two consecutive source words into a three-bit word that is not identical to the four words SKP1-SKP4 (CA1-CA4) of the transmission channel allows the receiver to detect the existence of a situation in which the encoding of single source words into the corresponding single the words of the transmission channel could lead to violation of the restriction on d = 1. Now the encoding device encodes a block of two two-digit source words as a block of two three-digit transmission channel words. Each block value of two two-digit source words together with another block value forms a pair of two two-digit source words, while the meanings of the specified pair of two two-digit source words differ in the bit value in the c | -th bit of one of the two two-digit source words. Thus, the conversion device acts on the output signal of the preliminary 1T encoding device so that the current value of the difference between the number of zeros and ones in the digital output signal of the preliminary 1T encoding device can be controlled so that its dependence on time has the required appearance while satisfying the conditions of the limitation on d = 1.

To implement coding of blocks of two two-bit source words, the device according to the invention may differ in that the conversion tool is designed in such a way that it converts the blocks of two consecutive two-digit source words into blocks of two consecutive three-digit transmission channel words in accordance with the coding scheme specified in the table below.

A block of two source words Transmission channel two word block 00 00 100 010 00 01 101 010 11 00 000 010 11 01 001 010

To generate (b, c) a sequence in which the value of k exceeds 5, the device according to the invention additionally contains a means for detecting the location in the bit stream of the original signal, in which the encoding of single two-digit source words into single three-digit transmission channel could to violate the restriction on k, and carrying out the issuance of the second control signal in response to said detection, which may additionally differ in that the transform means in the presence of a second control signal arising from the conversion of three consecutive two-digit source words, it converts a block of these three consecutive two-digit source words into a block of three corresponding consecutive three-digit transmission channel words, and the conversion tool is additionally designed in this way that, to ensure that the constraint on k is maintained, it converts two of these three source words, containing in the block, into the corresponding three-bit words of the transmission channel, which are not identical to these four words of the SKP1-SKP ₄ (C ^ 1-C ^ ₄ ) transmission channel.

These measures allow encoding of a block of three two-bit source words as a block of three three-digit transmission channel words, while satisfying the constraints on k, while the encoding operation allows you to constantly control the current value of the difference between the number of zeros and ones in the digital signal of the device preliminary 1T-coding so that its dependence on time had the required form.

The method of converting two (for example, second and third) of three consecutive source words into a three-bit word that is not identical to the four words of the UPC _{1 of the} UPC ₄ (C0 | -C0. ₄ ) transmission channel allows the receiver to detect the existence of a situation in which encoding single two-digit source words into corresponding single three-bit transmission channel words could violate the constraint on k. After detecting such a situation, a decoding device can decode Contents block of three three-digit channel words into a corresponding block of two-digit three initial words by the operation reverse to that performed in encoding.

To implement the coding of blocks of three two-bit source words, the device according to the invention may differ in that the conversion tool is designed in such a way that it converts the blocks of three consecutive two-digit source words into blocks of three consecutive three-digit transmission channel words in accordance with the coding scheme specified in the table below.

A block of three source words Three word channel block 10 10 10 000 010 010 10 10 11 001 010 010 01 10 11 101 010 010 01 10 10 100 010 010

A decoding device for a stream of information bits of a binary signal of a transmission channel into a stream of information bits of a binary source signal, in which the stream of bits of a transmission channel signal is divided into bit words of the transmission channel, containing inverse conversion means designed to inverse t-bit the words of the transmission channel in the corresponding pre-bit source words, and characterized in that each value of n-bit source words, along with a different value yadnyh source words forming a pair of source words, the values of the initial words of said pair of n-bit source words differ in the bit value with |. that discharge of n-bit source words, where the value of a. | is constant, the pairs of pre-bit source words are subdivided into the first part and the rest, and the inverse transform is designed to invert the t-bit words of the transmission channel into n-bit source words in such a way that the inverse transformation of the t-bit words of the transmission channel into the source words, which form a pair of source words from the first part of pairs of n-bit source words, are carried out with preservation of parity, and the reverse conversion of bit words of the transmission channel into the source is, words that form a pair of source words of the remaining part of the pairs of n-bit source words, is carried out with inversion parity.

Ί

It should be noted that US Pat. No. 4,547,890 discloses a conversion device that converts p-bit source words to t-bit words of a transmission channel, in which there is no constant component of the signal in the transmission channel. However, the conversion device does not always convert the n-bit source words to the t-bit words of the transmission channel in such a way that the conversion of two source words, which form a pair of source words from the first part of pairs of n-bit source words, is a parity conversion, and the transformation of two source words, which form a pair of source words from the rest of the pairs of n-bit source words, is a parity inversion transformation. In addition, to create an output signal without a constant component, an algorithm is needed to select the t-bit word of the transmission channel.

A more detailed description of embodiments of the invention will now be given by way of examples with reference to the drawings, in which FIG. 1 shows the first embodiment of the device;

in fig. 2A shows a second embodiment of the device;

in fig. 2B shows a third embodiment of the device; and in fig. 3 shows a fourth embodiment of the device;

in fig. 4 shows the application of the device in the 1-bit insertion scheme into equally spaced discharges of a serial source signal, and FIG. 5 shows an embodiment of a decoding device.

FIG. 1 shows a device having an input terminal 1 serving to receive a stream of information bits of a binary source signal 8. An input terminal 1 is connected to the input of a shift register 2 having two cells X ₁ and X ₂ for receiving two consecutive source bits of the original signal 8. Shift register 2 functions as a serial-to-parallel code conversion device to obtain consecutive two-digit source words of the IC (8 \ Y). The outputs of these two cells are connected to two inputs Rin _s Rin ₂ (ΐ _1, ί ₂₎ logic circuit LS (LC) which serve to input logic values (XI, x ₂₎ of the source bits that are in locations, in the logic circuit LS.

The device additionally contains a second shift register 4, having three cells Υ ₁ , ₂ and ₃ . Outputs About |. About ₂ and about ₃ logical circuits of the LAN are connected to the corresponding inputs of these three cells Υ ₁ , Υ ₂ and Υ _{3 of the} shift register 4, through which the logical values ( ₁ , ₂ , ₃ ) of the transmission channel words are entered. The output 6 of the shift register 4 is connected to the terminal device 8 output. The shift register 4 functions as a parallel-serial conversion device that converts the three-digit UCS of the transmission channel, obtained from the output of the LAN logic circuit, into a serial stream of information bits of the binary signal C1 of the transmission channel.

The logic circuit of the LAN is designed in such a way that it converts consecutive two-digit source words of the IC into three-digit words of the transmission channel. Each of the two-digit source words of the IC together with one more two-digit source word form a pair of source words. The choice of two two-digit source words is carried out in such a way that their meanings differ only in the value of the bit in the c | -th bit. Thus, if the c. | -Th bit of a bit is the last bit of a bit, the values 00 and 01 form the first pair, and the values 10 and 11 form the other pair. The choice of the two-digit source word conversion operation was carried out in such a way that the transformation of the first pair of two-digit source words is performed with parity preservation, and the transformation of the other pair is performed with parity inversion. The term “parity inversion” means that the number of units in the source word to be converted is the inverse of the number of units in the corresponding word of the transmission channel after performing, if necessary, modulo 2 units in the word of the transmission channel. In other words, if the number of units in the source word is even, then the number of units in the transmission channel word will be odd, and, conversely, if the number of units in the source word is odd, then the number of units in the transmission channel word will be even.

For example, the LAN of the conversion tool is designed in such a way that it converts the two-bit source words of the IC into three-digit words of the transmission channel UPC in accordance with the table below.

Table 1

Original word (X1, X2) Transmission channel word ^(y b ^y 2, ^y 3 ⁾ IS1 00 SKP1 101 IS2 01 SKP2 100 Sar ten UPC ₃ 000 IS4 eleven UPC ₄ 001

Pairs of two-digit source words are formed from such source words that are distinguished by the bit (x2) in the second digit.

It should be noted that the first bit of the source word is supplied to the shift register 2 first and that the output of the first bit of the transmission channel word from the output 6 of the shift register 4 is carried out first.

The bit stream of the words of the transmission channel is represented as BVN-I (without returning to zero with inversion) (ΝΚΖΙ), which means that the presence of a unit leads to a change in the recording current when recording the signal of the transmission channel on a magnetic recording medium.

The device of FIG. 1 can be used to generate the C ₁ signal _of the transmission channel in the form (b, k) of a sequence that satisfies the constraint on b = 1. This means that at least one zero is present in the serial data stream of the transmission channel signal between two consecutive units. That is, continuous sequences of two or more units are prohibited in the transmission channel signal.

A situation may arise in which the transformation of combinations consisting of two consecutive two-digit source words, carried out without modification, for example, by means of the device of FIG. 1, can violate the restriction on b = 1. Such combinations are the following combinations: 00 00, the transformation of which, without modification, leads to the creation of two three-digit transmission channel words having the form 101 101; 00 01, the conversion of which, without modification, leads to the creation of two three-digit transmission channel words having the form 101 100; 11 00, the conversion of which, without modification, leads to the creation of two three-digit transmission channel words having the form 001 101; and 11 01, the conversion of which, without modification, leads to the creation of two three-digit transmission channel words having the form 001 100.

To provide modified coding of blocks of two two-digit source words into blocks of two three-digit transmission channel words, it is necessary to detect the occurrence of such combinations. FIG. 2A shows a modified embodiment of the device of FIG. 1, which, in addition to the usual coding of two-bit source words into three-bit words of a transmission channel, can additionally perform detection of the above combinations and perform modified coding, invariably ensuring that the constraints on b = 1 for the transmission channel signal are satisfied.

The device of FIG. 2A contains a shift register with four cells, X ₁ through X ₄ , used to receive four consecutive bits (XI, x ₂ , x ₃ , x ₄ ) from the serial bit stream of the original signal 8. The outputs of these four cells in the specified order connected to the corresponding inputs V1-VH4 logical circuit LAN '. The device further comprises a detection device Ό1. The detection device Ό1 is executed in such a way that it detects in the consecutive bit stream of the original signal that location in which the encoding of the single source words of the bit stream into the corresponding single words of the transmission channel, performed without modification, results in violation of the b = 1 restriction for the C signal transmission channel, and is designed in such a way that, in response to such detection, it feeds a control signal to its output 10.

The output 10 of the detection device Ό1 is connected to the input 12 of the control signal of the logic circuit LAN '. The logic circuit LAN has six outputs from ₁ to ₆ , which are connected to the corresponding inputs of cells ₁ to _{6 of the} second shift register 4.

In the absence of a control signal at the input 12 of the control signal, the LS 'logic circuit converts the first two-digit source word χιχ ₂ into a three-digit word y _{1 2 2} and ₃ transmission channels in accordance with the above table. 1. As soon as the scheme of the detection device регистри1 registers the presence of a combination of two two-digit source words (x ₁ x ₂ , x ₃ x ₄ ), which is equal to one of the above combinations, the logic circuit LAN 'transforms this combination in accordance with the modified coding scheme shown in the following table.

table 2

Original words Non-Modified Coding Scheme Modified coding scheme 00 00 101 101 100 010 00 01 101,100 101 010 11 00 001 101 000 010 11 01 001,100 001 010

The table shows that the initial transformation of single two-digit original words, carried out without modification, leads to violation of the restriction on b = 1, since two units appear on the boundary between the two received words of the transmission channel. Consequently, the logical scheme of drugs' is designed in such a way that it converts blocks of two two-digit source words given in the left column of the above table into blocks of two three-digit transmission channel words given in the right column of the above table. 2, with a modified coding mode. It can be seen that now there are no violations of the restriction on b = 1. In addition, the modified coding is again performed either with parity preservation or with parity inversion, but now for pairs of two two-digit source words. This is very useful from the point of view of the possibility of obtaining a signal without a constant component from the output of a pre-coding device by adding 1 bit to the input signal, which results in a bit stream of the original signal, which is fed to a coding device. In this situation, this means that if the number of units in blocks of two two-digit source words that form a pair is odd (even), then the number of units in a block of two received three-digit transmission channel words is odd (even), or get the opposite depending on whether the pair is transformed from a block of two-digit source words with parity preservation or with parity inversion. In addition, the encoding of one of the two two-bit source words, which is the second in the above table, in the form of a three-digit word of the transmission channel is carried out so that it is not equal to any of the four transmission channel words from Table. 1. This is due to the fact that at the receiver side it is possible to detect this three-digit word of the transmission channel that does not belong to the table below. 1 is a set of four three-bit words of the transmission channel, which allows implementing the corresponding decoding operation, which is the operation inverse to the encoding operation, the description of which is given with reference to the table. 2

The logic circuit LAN produces a block of two three-bit words of the transmission channel, obtained by encoding in accordance with the table. 2, to their outputs, output _1- out ₆ (about ₁ -o ₆ ), and the words of the transmission channel from this block are served in six cells Υ ₁ -Υ _{6 of the} shift register 4 '. From the description of the present embodiment, it is understood that the detection of situations in which modified coding is necessary is carried out by the detection device Ό1 using the original words.

FIG. 2B shows a different design of the device performing modified coding, the description of which is given with reference to the table. 2. In this case, the detection of situations in which it is necessary to carry out modified coding is performed using the transformed words of the transmission channel. The device of FIG. 2B contains a detection device Ό1 ′ having 6 inputs for receiving two consecutive three-digit transmission channel words obtained by means of coding without modification. The detection device Ό1 'determines whether two consecutive three-bit words of the transmission channel, obtained using coding without modification, are equal to one of the four six-digit sequences shown in the middle column of the table. 2 under the heading Coding Scheme without modification. If this is the case, then the detection device Ό1 'generates a switch signal to its output 10 and an ADR (AO) signal addressing to its output 10'. The switching signal is fed to the input 45 of the switching signal in the shift register 4. The ADR (AO) address signal is fed to the input 46 of the addressing signal in the ROM 47 (permanent memory). In response to the detection, respectively, of one of the four six-bit sequences shown in the middle column of the table. 2, the detection device I1 'generates one of four possible addressing signals from AD1 to AD4 (AO1-AI4). For example, the AD1 (AO1) addressing signal is generated when the detection device I1 'detects the presence of the sequence 101 101, and the AD4 (AO4) addressing signal is generated after the detection of the six-digit sequence 001 100. The six-digit sequences in the right column of the table. 2, is stored in the ROM 47. After receiving the AD1 addressing signal, the ROM supplies to its outputs O1-OUT6 (O1-O6) a six-bit sequence 100 010, and after receiving the addressing signal AD2, the ROM delivers to its outputs a six-digit sequence 101 010. After receiving the AD3 signal, addressing the ROM sends a six-digit sequence 000 010 to its outputs, and after receiving the AD4 signal, the addressing ROM sends a six-bit sequence 001 010 to its outputs. Now each memory cell of the shift register 4 has two inputs, one of which is ene with an appropriate output of the logic circuit LS 'and the other is connected to a corresponding output of the ROM 47.

In the usual situation in which there is no violation of the restriction on d = 1, the conversion is performed without modification, and the switching signal is absent, and the shift register receives the bits supplied from the logic circuit LAN through the upper inputs of the shift register 4. In that case if the restriction on d = 1 is violated, a switch signal is sent to the input 45 of the switching signal, and this leads to the fact that the shift register receives a six-bit sequence representing a modified sequence The bone that the ROM supplies to the lower inputs of the shift register 4.

The presence of a limit on k in (th, k) sequence means that the transmission channel signal allows continuous sequences from, to a maximum, to zeros located between two consecutive ones.

There may be a situation in which the transformation of three consecutive two-digit source words, carried out without modification, violates the restriction on k.

For example, as a result of the transformation of the sequence of source words, having the form 101 010, carried out without modification, three three-bit words of the transmission channel are obtained of the following form: 000 000 000. In the case when it is necessary to obtain (b, k) a sequence in which k equals 6 , 7 or 8, such a combination of three three-digit transmission channel words should not arise.

Another example is the sequence of the original words of the form 101011, as a result of which, carried out without modification, three three-bit transmission channel words are obtained: 000 000 001. Such a combination of three three-digit transmission channel words does not satisfy the restriction on k = 6 or k = 7 . In addition, such a combination of three three-bit transmission channel words may follow the previous transmission channel word, which ends with 0, which may lead to violation of the k = 8 constraint. In addition, this combination ends with 1, which can lead to violation of the b = 1 restriction if this combination is followed by a three-bit transmission channel word starting with 1. Similar reasoning is valid for the sequence of source words of the following type: 01 10 ten.

As another example, a sequence of source words of the type 01 10 11 is used, as a result of which three three-bit transmission channel words of the following type are obtained without modification: 100 000 001. Like the one described above, such a combination can lead to violation of the b = 1 restriction.

To enable the implementation of modified coding, it is necessary to detect the presence of such combinations. FIG. 3 shows an embodiment of a device that, in addition to the usual coding of two-digit source words into three-digit transmission channel words, can additionally detect the above combinations and in which modified coding can be implemented.

The device of FIG. 3 contains a shift register 2, having six cells X ₁ through X ₆ , used to receive six consecutive bits from the serial bit stream of the original signal 8. The outputs of these six cells in the specified order are connected to the corresponding inputs in. \ | -In ₆ logical scheme of drugs. The device further comprises a detection means Ό2. The detection means Ό2 is designed in such a way that it detects the location in the sequential bit stream of the original signal, in which the coding of the bit stream, carried out without modification, violates the constraint on k for the transmission channel signal C ₁ , and is performed in such a way that in response on the specified detection produces a control signal at its output 15.

The outputs of these six cells are also connected to the four corresponding inputs of input ₁ in ₆ (ίι- ₆ ) of the LS logical circuit. The output 15 of the detection means Ό2 is connected to the input 16 of the control signal of the drug logic circuit. The drug logic circuit has nine outputs, output1-output9 (θι-ο ₉ ), which are connected to the corresponding inputs of cells Υ ₁ -Υ _{9 of the} second shift register 4.

In the absence of control signals at inputs 12 and 16 of control signals, the logic circuit of the LAN converts a single two-digit source word χιχ ₂ into a single three-digit word y1y ₂ and ₃ transmission channels in accordance with the above table. 1. As soon as the scheme of the device обнаружения1 detection registers the presence of a block of two two-digit source words χ ₁ χ ₂ , x ₃ x ₄ , which is equal to one of the combinations given in the above table. 2, the logic circuit of the drug performs the conversion of this combination in accordance with the conversion rule given in Table. 2, resulting in a block y1y ₂ y ₃ y ₄ y ₅ y ₆ , consisting of two three-bit transmission channel words.

As soon as the detection device Ό2 registers the presence of a χιχ ₂ χ ₃ χ ₄ , x ₅ x ₆ block, consisting of three two-digit source words, which is equal to one of the above combinations, the logical logic circuit performs the block conversion in accordance with the modified coding scheme, which is specified in the table below, resulting in a block of three three-digit transmission channel words.

Table 3

Original words Non-Modified Coding Scheme Modified coding scheme 10 10 10 000 000 000 000 010 010 10 10 11 000 000 001 001 010 010 01 10 11 100,000 001 101 010 010 01 10 10 100,000,000 100 010 010

The logic circuit of the LAN is designed in such a way that, in a modified coding mode, it performs the conversion of blocks of three two-digit source words given in the left column of the above table. 3, into blocks of three three-digit transmission channel words, which are listed in the right-hand column of the above table. Through the implementation of a modified coding according to the table. 3 receive the transmission channel signal satisfying the restriction on k = 8. In addition, the modified coding of pairs of two source words is carried out in the same way with parity preservation or with parity inversion.

This is very useful to ensure that the output of a pre-coding device without a constant component is obtained by adding 1 bit to the input signal to obtain a stream of bits of the original signal that is fed to the coding device. In this situation, this means that if the number of units in blocks of three two-digit source words that form a pair is odd (even), then the number of units in the resulting block of three three-digit transmission channel words is odd (even), or receive the opposite the situation depends on whether the transformation of a pair of blocks of three two-digit source words is a parity-preserving transformation or a parity-inversion transformation. In addition, the coding of two of the three two-bit source words, which are the second and third in the above table, in the form of a three-bit word of the transmission channel is carried out so that it is not equal to any of the four transmission channel words from Table. 1. This is due to the fact that on the receiver side it is possible to detect these two consecutive three-digit transmission channel words that do not belong to the table below. 1 is a set of four three-bit words of the transmission channel, which allows implementing the corresponding decoding operation, which is the operation inverse to the encoding operation, the description of which is given with reference to the table. 3

The logic circuit of the LAN produces combinations of three three-digit transmission channel words obtained by encoding in accordance with Table. 3, to its outputs O ₁ -OUT _e (o ₁ -o _e) and the transmission channel words supplied to the nine cells Υ ₁ -Υ ₉ of the shift register 4. The serial data signal flow channel C ₁ is supplied to the output terminal 8.

Obviously, instead of detecting a violation of the constraint on k at the level of the original signal, such detection can be carried out at the signal level of the transmission channel in the same way as the one described with reference to FIG. 2b.

As stated above, other conversion rules are possible for converting single two-bit source words into single three-digit transmission channel words. These conversion rules are listed in the seven tables below.

Table 4

Source word (X1, X2) Word (U1, U2, Oz) transmission channel IS1 00 SKP1 101 IS2 01 SKP2 001 Sar ten SKPZ 000 IS4 eleven UPC ₄ 100

Table 5

Original word (X1, X2) Word (U1, U2, Oz) transmission channel IS1 00 SKP1 000 IS2 01 SKP2 100 IS3 ten SKPZ 101 IS4 eleven UPC ₄ 001

Table 6

Original word (X1, X2) Word (Y1, Y2, Oz) transmission channel IS1 00 SKSh 000 IS2 01 UPC ₂ 001 IS3 ten UPC _h 101 IS4 eleven UPC ₄ 100

Table 7

Original word (X1, X2) Word (Y1, Y2, Oz) transmission channel IS1 00 SKSh 100 IS2 01 UPC ₂ 101 IS3 ten UPC _h 001 IS4 eleven UPC ₄ 000

Table 8

Original word (X1, X2) Word (U1, U2, Oz) of the transmission channel IS1 00 SKP1 001 IS2 01 SKP2 101 Sar ten SKPZ 100 IS4 eleven UPC ₄ 000

Table 9

Original word (X1, X2) Word (U1, U2, Oz) of the transmission channel IS1 00 SKP1 100 IS2 01 SKP2 000 Sar ten SKPZ 001 IS4 eleven UPC ₄ 101

Table 10

Original word (X1, X2) Word (U1, U2, Oz) transmission channel IS1 00 SKP1 001 IS2 01 SKP2 000 Sar ten SKPZ 100 IS4 eleven UPC ₄ 101

It is obvious that using the above principles, additional to the above transformation rules can be obtained for encoding blocks of two or three two-digit source words into blocks of two or three three-digit transmission channel words.

An explanation of another embodiment of the encoding device is given with reference to the table below. 11. This table outlines the mapping rule for a coding device that can encode three-digit source words into four-digit transmission channel words.

Table 11

Original word (X1, X2) Word (U1, U2, U ₃ ) transmission channel IS1 000 SKP1 0000 IS2 001 SKP2 0001 IS ₃ 010 UPC ₃ 0100 IS4 011 UPC ₄ 0101 IS5 100 UPC ₅ 1001 IS6 101 UPC ₆ 1000 IS7 110 UPC ₇ 0010 IS8 111 UPC ₈ 1010

In tab. 11, the transformation of the source word belonging to the pairs of source words (IS1, IS ₂ ) and (IS ₃ , IP ₄ ) is carried out with preservation of parity, and the transformation of the source word belonging to the pairs of source words (IC ₅ , IC ₆ ) and (IS-. IC ₈ ) perform parity inversion. In this case, the value of a pair of source words differs only in the value of a bit x ₃ . However, the same table can also be used to create pairs of source words that differ only in the value of a bit x ₂ . For example, the pairs of source words can be formed as follows: (IC _L IS ₃ ), (IC 2, IC ₄ ), (IC 5, IC ₇ ) and (ISB, IC), while the conversion of the first two pairs and the last two pairs is performed respectively with parity preservation and with parity inversion. It should be noted that in the conversion table according to the invention there is no need for the number of pairs of source words, the conversion of which is carried out while preserving parity, to be equal to the number of pairs of source words that are converted with parity inversion. Thus, the operation of converting a three-digit source word into a four-digit word of the transmission channel can contain the operation of converting three pairs of source words with parity preservation and the operation of converting one pair of source words with parity inversion.

As indicated above, the use of the devices described above is extremely appropriate in conjunction with a conversion device, in which 1 bit is inserted after every r bits of a serial data stream to perform or not to perform a polarity conversion. FIG. 4 shows such a set, in which the device 7 ′ according to the present invention is located after the conversion device 40, and the device 1 of the prior art 1T coding is located after the device 7 ′. The output signal of the device 1 1T pre-coding is fed to the generator 43 of the control signal, which generates a control signal for the device 40 conversion, through which control insert or 0 or 1 in a serial data stream, which is fed to the device 7 '. The insertion of bit 0 or 1 always leads respectively to an increase and a decrease or to a decrease and an increase in the current value of the difference between the number of zeros and ones at the output of the pre-coding device 42. By means of what is shown in FIG. 4 devices can input a tracking tone of a certain frequency into a serial data stream, or it can keep the constant component of the data stream equal to zero. In addition, in the case when the device 7 'is designed in such a way that it generates (b, k) sequences as described above, this leads to the fact that the output signal of the device from FIG. 4 is an output signal (b, k) with a limitation of the distance between magnetization transitions (QD). Examples of the conversion device 40 are given in the Bell Systems Technical Journal, vol. 53, no. B, p. 1103-1106 (Wells 11 Testamés-1 1igia1, Wo1.53, Νο.6, pp. 1103-1106).

FIG. 5 shows a decoding device for decoding a serial data stream obtained by the encoding device of FIG. 3, resulting in a binary source signal. The decoding device has an input terminal 50 through which the signal of the transmission channel is received, and the input terminal 50 is connected to the input 56 of the shift register 51, which contains nine cells from ₁ to ₉ . The shift register 51 functions as a serial-parallel conversion device, supplying blocks of three three-bit transmission channel words to inputs in 1 in _{9 of} logic circuit 52. Logic circuit 52 contains three tables: Table. 1, tab. 2 and tab. 3. Outputs 1-out 6 of logic circuit 52 are connected to the inputs of cells X ₁ -X _{6 of the} shift register 54, the output 57 of which is connected to the output terminal 55. The circuit 53 of the detection device has inputs in _1- in ₆ , connected respectively to the outputs of cells Υ ₄ -Υ ₉ shift register 51, and has outputs output ₁ and output ₂ , which are connected respectively to the inputs of control 1 and control 2 (c1, c2) of the control signal of logic circuit 52. The detection device circuit 53 can detect bit pattern 010 in cells ₄ , Υ ₅ and Υ ₆ shift register 51 and can implement detection of the bit pattern 010010 in cells ₄ through _{9 of the} shift register 51.

After detecting the bit pattern

010010 the detection device circuit 53 generates a control signal at its output of output ₂ , and after detecting the bit combination 010 in cells Υ ₄ , Υ ₅ and Υ ₆ with the simultaneous absence of the bit combination 010 in cells ₇ , ₈ and Υ _9, it generates control signal at its output

In the absence of control signals, the logic circuit 52 converts the three-bit word of the transmission channel stored in the cells Υ ₁ , Υ ₂ and ₃ into the corresponding two-digit source word according to Table. 1 transforms and feeds a two-digit source word into cells X ₁ and X ₂ . If there is a control signal at the input of the control unit, logic circuit 52 converts a block of two three-digit transmission channel words stored in cells ₁ through ₆ , into a block of two two-digit source words according to the table. 2 transformations and submits two two-bit source words to cells X ₁ -X ₄ . If there is a control signal at the input of the control unit, logic circuit 52 converts a block of three three-digit transmission channel words stored in cells ₁ through ₉ into a block of three two-digit source words according to Table. 3 transformations and feeds three two-bit source words into cells X ₁ -X ₆ . This is how the serial data stream of the transmission channel signal is converted into a serial data stream of the original signal.

Encoded information, which is fed to the input 50, can be obtained by reproducing information from a recording medium, for example from a magnetic recording medium 23 or from an optical recording medium 23 '. For this, the device of FIG. 5 contains a reading device 62 that reads information from a track on a record carrier, and a device 62 contains a reading head 64 that reads information from a specified record track.

Although the description of the invention has been made with reference to preferred embodiments thereof, it should be understood that these examples are not limiting. Consequently, specialists in this field of technology can be implemented various modifications without going beyond the scope of the patent claims of the invention, which are defined by the claims. For example, as a result of the modification of the decoding device of FIG. 5, such a device can be created in which the detection device 53 performs the detection of various modified states when decoding on the basis of the decoded information, and not from the encoded information, which is disclosed and shown in FIG. 5. In addition, it should be noted that, for example, the transform device 7 'and the pre-coding device 42 can be combined into one block, in which, depending on the input η-bit source words, the direct conversion of these η-bit source words in three-digit words that feed the output of the combined block. In addition, it is also advisable to use the invention in a device for converting 8-bit source words into 15-bit transmission channel words.

The use of the verb contains in itself and its variants does not exclude the presence of other blocks or operations than those stated in the claim. In addition, the use of the indefinite article before the name of the block does not exclude the presence of many such blocks. Any reference designations in the claims enclosed in parentheses should not be construed as limiting the scope of patent claims as defined by the claims. The invention may be implemented by hardware, as well as by software. By means of the same hardware product several means can be realized. In addition, each and every feature of novelty or combination of features is inherent to the invention.

Claims (19)

CLAIM 1. A device for encoding a stream of information bits of a binary source signal into a stream of information bits of a binary signal in a transmission channel, in which the bit stream of the source signal is divided into η-bit source words, the device comprising conversion means configured to convert said source words to the corresponding t-bit words of the transmission channel, characterized in that each value of η-bit source words together with another value of η-bit source words they form a pair of source words, and the meanings of the source words of the specified pair of η-bit source words differ from each other by the bit value in s. | that category of η-bit source words, where the value of c. | is constant, the pairs of η-bit source words are divided into the first part and the rest, and the conversion means is configured to convert η-bit source words to t-bit words of the transmission channel in such a way that the conversion of two source words forming a pair of source words from the first part of the pairs of η-bit source words, is carried out with preservation of parity, and the conversion of two source words, forming a pair of source words from the rest of the pairs of η-bit source words suschestvlyaetsya inversion parity. 2. The device according to claim 1, characterized in that the conversion means is arranged to convert a block of p consecutive η-bit source words into a corresponding block of p consecutive t-bit words of a transmission channel, where η, t and p are integer numbers, m> n> 2, p> 1, and where p can take different values. 3. The device according to claim 2, characterized in that m = n + 1. 4. The device according to claim 3, characterized in that η = 2. 5. The device according to claim 4, characterized in that the device is configured to convert single source words to the corresponding single words of the transmission channel in accordance with the table below. Source word Transmission Channel Word IS1 00 SKP1 101 IS2 01 SKP2 one hundred Sat 10 SKPz 000 IS4 eleven UPC ₄ 001 6. The device according to any one of paragraphs.4, 5, characterized in that the conversion means is arranged to convert two-bit source words to the corresponding three-bit words of the transmission channel, resulting in a signal of the transmission channel in the form of (s, k) sequence, where d = 1, while the device further comprises a means for detecting the location in the bit stream of the original signal, in which the encoding of single two-bit source words in the corresponding single with ova transmission channel might lead to a violation limit minutes at word boundaries of the transmission channel, and performs outputting a control signal in response to said detection, wherein the control signal conversion means performs conversion of the single two-digit source words into corresponding single three-bit words of the transmission channel. 7. The device according to claim 6, characterized in that the conversion means is configured to implement, if there is a control signal that occurs when converting two consecutive source words, converting a block of these two consecutive two-bit source words into a block of two corresponding three-bit words of the transmission channel so that in order to maintain the constraint on = = 1, the conversion of one of the two source words from the block of source words into a three-bit word of the transmission channel is carried out It is such that it is not identical to any of the four words SKP | -SKP _{4 of} the transmission channel, while the conversion means is further configured to, if the control signal is provided, convert a block consisting of the indicated two consecutive two-bit source words to the corresponding block consisting of two consecutive three-bit words of the transmission channel. 8. The device according to any one of claims 1, 7, characterized in that the conversion means is configured to convert blocks of two consecutive two-bit source words into blocks of two consecutive three-bit words of the transmission channel in accordance with the encoding scheme specified in the table below . A block of two source words Transmission Channel Two-Word Block 00 00 100 010 00 01 101 010 11 00 000 010 11 01 001 010 9. The device according to any one of claims 6 to 8, characterized in that the value of k exceeds 5 and the device further comprises means for detecting that location in the bit stream of the original signal, in which the encoding of single two-bit source words into single three-bit words of the transmission channel to violation of the restrictions on k, and issuing a second control signal in response to the specified detection, while the conversion means is configured to be implemented, if there is a second control the signal that occurs when converting three consecutive two-bit source words, converting a block of these three consecutive two-bit source words into a block of three corresponding consecutive three-bit words of a transmission channel, the conversion means being further configured to convert two of these three source words contained in block, in the corresponding three-bit words of the transmission channel that are not identical to these four words SKP1-SKP ₄ channel transfer, to ensure that the restrictions on k. 10. The device according to any one of claims 1, 9, characterized in that the conversion means is configured to convert blocks of three consecutive two-bit source words into blocks of three consecutive three-bit words of the transmission channel in accordance with the encoding scheme specified in the table below . Block of three source words Block of three words transmission channel 10 10 10 000 010 010 10 10 11 001 010 010 01 10 11 101 010 010 01 10 10 100 010 010 11. The device according to any one of the preceding paragraphs, characterized in that the conversion means is arranged to carry out a signal processing operation for a binary source signal, and this operation is equivalent to converting consecutive source words to consecutive words of a transmission channel with subsequent preliminary AT-coding of said channel words transmission. 12. The device according to any one of claims 1, 11, characterized in that it further comprises means for adding bits, adding one bit to consecutive blocks of g bits of the original signal. 13. The device according to any one of the preceding paragraphs, characterized in that it further comprises means for recording a stream of information bits of a binary signal in a transmission channel to a track of a recording medium. 14. A method of encoding a stream of information bits of a binary source signal into a stream of information bits of a binary signal in a transmission channel, in which the bit stream of the original signal is divided into η-bit source words, and the method includes the operation of converting the specified source words into corresponding t-bit words of the transmission channel characterized in that each value of η-bit source words together with another value of η-bit source words form a pair of source words, and the values of the source words of the specified pair η-bit of the source words differ in the bit value in the S. | -th bit of η-bit source words, where η is a constant, the pairs of η-bit source words are divided into the first part and the rest, and the conversion operation includes the conversion operation of η-bit source words into t-bit words of the transmission channel, which is carried out in such a way that the conversion of both two source words, forming a pair of source words from the first part of the pairs of η-bit source words, is performed with preservation of parity, and transform of the two source words forming a pair of source words of the remaining part of the pairs of η-bit source words, the parity inversion is performed. 15. A recording medium into which a binary signal of a transmission channel is supplied, wherein this binary signal of a transmission channel is obtained by converting a corresponding binary source signal, in which a bit stream of a binary signal in a transmission channel is divided into t-bit words of a transmission channel, the binary source signal is divided into η-bit source words, and t-bit words of the transmission channel are obtained by converting η-bit source words to the corresponding t-bit words of the transmission channel, characterized in that each value of η-bit source words, together with another value of η-bit source words, form a pair of source words, and the values of the source words of the specified pair of η-bit source words differ among themselves by the bit value in the s. | -th bit of η-bit source words, where the quantity η is constant, the pairs of η-bit source words are divided into the first part and the rest, while the conversion of η-bit source words into t-bit words of the transmission channel is carried out with the possibility of converting two source words parity, forming a pair of source words from the first part of the pairs of η-bit source words, while maintaining parity, and the conversion of two source words, forming a pair of source words from the rest of the pairs of η-bit source words, is performed with parity inversion. 16. A recording medium into which a transmission channel signal with preliminary 1T coding is supplied, wherein this binary signal of a transmission channel with preliminary 1T coding is obtained by preliminary 1T encoding of a binary signal in a transmission channel, and a binary signal in a transmission channel is obtained by converting a corresponding binary source signal, in which the bitstream of the binary signal in the transmission channel is divided into t-bit words of the transmission channel, the binary source signal is divided into η-bit source e words, and bitwise words of the transmission channel are obtained by converting η-bit source words to the corresponding t-bit words of the transmission channel, characterized in that each value of η-bit source words together with another value of η-bit source words form a pair of source words moreover, the values of the source words of the indicated pair of η-bit source words differ from each other by the bit value in the c. | -th bit of η-bit source words, where the value η is constant, the pairs of η-bit source words are subdivided into the first part and the rest, while the conversion of η-bit source words to t-bit words of the transmission channel is carried out so that the conversion of two source words forming a pair of source words from the first part of the pairs of η-bit source words is performed with parity the conversion of two source words, forming a pair of source words from the rest of the pairs of η-bit source words, is performed with inverse parity. 17. A device for decoding a stream of information bits of a binary signal of a transmission channel into a stream of information bits of a binary source signal, in which the bit stream of a signal of a transmission channel is divided into channel words of the transmission channel, the device comprising inverse transform means configured to perform the inverse transformation of channel channel words transfer to the corresponding η-bit source words, characterized in that each value of η-bit source words together with another value m of η-bit source words form a pair of source words, and the values of the source words of the specified pair of η-bit source words differ among themselves by the bit value in the c. | -th category of η-bit source words, where the value of c. | is constant, the pairs of η-bit source words are subdivided into the first part and the rest, and the inverse transform means is capable of performing the inverse transformation of the t-bit words of the transmission channel into η-bit source words such that the inverse transformation of the t-bit words of the transmission channel to source words, which form a pair of source words from the first part of pairs of η-bit source words, are performed with parity, and the conversion of t-bit words of the transmission channel to the original is, words that form a pair of source words of the remaining part of the pairs of η-bit source words, the parity inversion is performed. 18. The device according to 17, characterized in that the inverse transform means is configured to inverse transform a block of p consecutive different-bit words of a transmission channel into a corresponding block of p consecutive η-bit source words, where η, t and p are integers, m> q> 2, p> 1, and where p can take different values. 19. The device according to any one of paragraphs.17, 18, characterized in that the inverse transform means is configured to reverse transform the t-bit words of the transmission channel into η-bit source words in accordance with at least one of the tables given in the description .