MXPA99006015A - Device for encoding/decoding n-bit source words into corresponding m-bit channel words, and vice versa - Google Patents

Abstract

A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C) satisfying a (d,k) constraint, wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (y1, y2, y3). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for ech n-bit source word is parity preserving (table I). The relations hold that m>n=1, p=1, and that p can vary. Preferably, m=n + 1. Further, a sync word generator (9) is available for generating a q-bit sync word also satisfying said (d,k) constraint, the said sync word starting with a'0'bit and ending with a'0'bit, the device further comprising mergingmeans (19) for merging said sync word in said stream of databits of the binary channel signal, and that q is an integer value larger than k(Fig. 1). Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

Description

DEVICE TO CODIFY / DECODE ORIGINAL N BITS WORDS EH CORRESPONDING M BITS CHANNEL WORDS AND VICE VERSA The invention relates to a device for encoding a data bitstream of a binary original signal in a data bit stream of a binary channel signal, which satisfies a predetermined constraint (d, k), wherein the flow of bits of the original signal is divided into n-bit original words, device which comprises conversion means, adapted to convert the original words into corresponding m-bit channel words, the conversion means are adapted to convert a block of p words of n consecutive bits, in a corresponding block of p channel words of m consecutive bits, so that the conversion of each block of p original words of n consecutive bits, • substantially preserves the parity, where n, m and p are integers, m > n > 1, p > 1, and where p may vary. The invention also relates to a recording device comprising the encoding device for decoding the channel signal in a record carrier, the record carrier itself, in a decoding method, and a device for decoding a bit stream of data of a binary channel signal, obtained by means of the encoding device, to obtain the data bitstream of a binary original signal.

An encoding device mentioned in the above is known from USP 5,477,222 (PHN 14448). The document describes a device for encoding a data bit stream of a binary original signal, in a data bit stream of a binary channel signal satisfying a displacement length restriction (1, 8). This means that, in the serial data stream of the channel signal, at least one "zero" and at most eight "zeros" are present between two consecutive "ones" in the channel signal. It should be noted in this regard, that additional precoding, such as a well-known precoding IT, is normally applied to the constrained sequence d, k (1, 8), resulting in a limited sequence in the offset length with a length of minimum displacement of 2 and a maximum displacement length of 9. The known conversion preserves parity.

"Preserve parity" means that the parity of the original words of n bits to be converted, equal parity (after the addition of module 2) of the corresponding m-bit channel words to which they are converted. As a result, the claimed n to m conversion device does not influence the polarity of the signal. When the parity conversion is preserved, an efficient DC control can be applied, such as by inserting the control bits Dc into the data stream of the original words.

The object of the invention is to provide -_ an appropriate synchronization word to be inserted in the serial data stream of the channel signal. The device according to the invention is characterized in that the device comprises means generating synchronization words, in order to generate a q synchronization word that also satisfies the restriction (d, k), the synchronization word begins with a "0" bit ", and ends with a" 0"bit, the device further comprises fusion means for fusing the synchronization word in the data bit stream of the binary channel signal, and because q is an integer value greater than k . It is well known in the art to add synchronization words to a serial data stream of a channel signal. Reference is made in this regard to WO 96/31,880. The proposed synchronization word violates the prescribed restriction k. This has its disadvantages, since a relatively long synchronization word is required, that is, more prone to errors, and ~ results in a relatively large overload. According to the invention, a synchronization word of q bits is proposed, so that, after combining the sequence of channel words with the synchronization word, the obtained signal satisfies the restriction (d, k). This has the advantage that a word is required of shorter synchronization, resulting in a smaller overload. In addition, since the synchronization word begins with a "0" bit and ends with a "0" bit, it can be merged between any m-word channel words, for example, when d is taken equal 1. Preferably, the synchronization word begins with a sequence of bits "01" and ends with a sequence "10". This causes the restriction k to be satisfied. In one embodiment, in which the encoding device generates a channel signal that satisfies the constraint d = 1, a 15-bit synchronization word is preferably used, such as the synchronization word "010000000010010". When k = -8, this synchronization word satisfies the formula q = 2k - 1, and is very efficient, even when comparing, for example, with other synchronization words that do not violate the restrictions d, k of the fused signals, as described in USP 4,501,000 (PHQ 80.007). It should be noted, however, that the synchronization word defined above could be equally used in an encoding device that will provide an output data stream satisfying another constraint k, such as k = 7 or less (so that the synchronization word does not satisfy the restriction k of the encoded signal), ok greater than 8.

In another embodiment, a synchronization word is generated that begins with a sequence of bits "01", and ends with a sequence of "100" bits, such as the 16-bit synchronization word "0100000000100100". In another embodiment, a synchronization word is generated that begins with a sequence of bits "01" and ends with a sequence of "1000" bits, such as the 17-bit synchronization word "01000000001001000". In a further embodiment, a synchronization word is generated starting with a bit sequence "01" and ending with a bit sequence of "10000", such as the 18-bit synchronization word "010000000010010000". For certain conversions from n to m, the synchronization word ending with two or more "zeros" can lead, after concatenation with a subsequent channel word and with unmodified coding, to a violation of the restriction k. This can be overcome by changing the conversion, so that the restriction k is satisfied, with a local violation of the property of parity preservation. The coding device according to the invention can be used in coordination with a bit adding unit, in which a bit is added to the key words of a certain length of the original signal. The signal obtained can be applied to the coding device of the present invention. The channel signal of the encoding device is applied to a precoder 1T. The purpose of the bit adding unit is to add a "0" or a "1" to the consecutive keywords included in the input signal of the converter, to obtain an output signal from the DC free precoder, or that includes a signal Tracking pilot that has a certain frequency. The output signal of the precoder is registered on a record carrier. The addition of a "0" bit in the input signal of the converter results in the polarity of the output signal of the precoder ÍT remaining the same. The addition of a bit "1" results in the inversion of the polarity of the output signal of the precoder ÍT. The converter therefore has an influence on the output signal of the precoder ÍT, so that the value of the current digital sum of the output signal of the precoder ÍT can be controlled, so that it has a desired control as a function. weather. The invention will be better described in the following description of the figures, in which Figure 1 shows a modality of the device according to the invention, Figure 2 shows a first elaborated _version of the converter in the device, Figure 3a shows a second, Figure 3b a third, and Figure 4 shows a fourth elaborate version of the converter in the device, Figure 5 is the application of the device according to the invention in an array to insert a bit over equidistant positions in the original signal in series , Figure 6 is an embodiment of the encoding device, and Figure 7 is an elaborate version of the converter unit of the encoding device of Figure 6. Figure 1 shows a device for encoding a data bit stream of a binary original signal in a data bitstream of a binary channel signal satisfying a predetermined constraint (d, k). The device has an input terminal 3 for receiving the original binary signal and an output terminal 5 for supplying the channel signal that satisfies the restriction (d, k). The device comprises a nam bit converter 7, having an input 1 coupled to the input terminal 3 and an output 8 coupled to a first terminal of a controllable switch 19. The converter 7 is adapted to divide the input bit stream in n-bit original words and convert the original words into corresponding m-bit channel words. More precisely, the converter ^ 7 converts a block of p words originals of n consecutive bits in a corresponding block of p words, channel of m consecutive bits, so that the conversion of each block of p original words of n consecutive bits, preserves the parity. n, m and p are integers, m > n > 1, p > 1, and p may vary, as will be clarified later. The device further comprises a synchronization word generator 9 for generating a q-bit synchronization word that also satisfies the restriction (d, k). q is an integer value greater than k. An output 11 of the synchronization word generator 9 is coupled to a terminal b of the controllable switch 19. A terminal c of the switch., 19 is coupled to the output terminal 5 of the device. The switch can be controlled in one of two switching positions, ac and bc, under the influence of the switching control signal on line 13, generated by a processing unit 17. In the switching position ac, the device converts the original signal in the channel signal and in position bc, a synchronization word may be inserted in the channel signal. The insertion of a synchronization word can take place repeatedly at "equidistant" positions in the channel signal, wherein a synchronization word is fused to the channel signal, each time between two successive m-channel words. It will be clear that the processing unit 17 also controls the converter 7, so that it stops the conversion at the moment when the synchronization word is based on the data flow of the channel signal. At this time, it can be said that the synchronization word begins with a "0" bit and ends with a "0" bit. First, the operation of the converter 7 will be further explained. The coding device of the filter 1 could, in addition, be provided with a writing unit 21 for writing the channel signal generated by an encoding device in a track on a record carrier. 23. The record carrier 23 can be a magnetic or optical record carrier. In the example of a magnetic record carrier 23, the writing unit 21 is provided with at least one magnetic head 25 for writing the channel signal in such track on the record carrier 23. In the example of an optical record carrier 23 ', the writing unit 21 is provided, with a light source, such as a laser, for writing the information in the registration carrier 23'. Figure 2 shows a first elaborated version of the converter 7. The terminal 1 of the converter is coupled to an input of a deviated register 2 having two cells Xi and X2, to receive the original consecutive bits of the original signal S. The deviated register 2 works with a serial to parallel converter, to obtain original words of consecutive 2 bits SW. The outputs of the two cells are coupled to two inputs ii, i2 of the logic circuit LC, to supply the logical values (xi, x2) of the original bits present in the cells. The converter 7 further includes a second offset register 4 having three cells Y? F Y2 and Y3. The outputs ci, o2 and o3 of the logic circuit LC are coupled to the inputs of the three cells Yi, Y2 and Y3, respectively, to the offset register 4, to supply the logical values (y-./- Y, y3) of the channel words. An output 6 of the diverted register 4 is coupled to an output terminal 8.

The offset register 4 functions as a parallel to serial converter, to convert the words of the 3-bit CW channel supplied by an LC logic circuit into the serial flow of the data bits of a signal converted to binary Ci. The LC logic circuit is adapted to convert consecutive 2-bit original words SW into 3-bit channel words, so that the conversion of each original 2-bit word preserves parity. This means that the number of "ones" in the original word to be converted is equal to the number of "ones" in the corresponding channel word, the addition of module 2 is carried out on the "ones" in the channel word . Or, put another way: yes the number of "ones" in the original word is even, the number "ones" in the word of channel will be even. Y: if the number of "ones" in the original word is odd, the number of "ones" in the channel word will be odd. As an example, the LC conversion means are adapted to convert the original 2-bit SW words for 3-bit CW channel words according to the following table: TABLE I It should be noted here that the first bit in the original word is first applied to the deviated register 2 and that the first bit in the channel word is first supplied from the output 6 in the deviated register 4. The bitstream of the words of channel in the NRZI notation (no return to the inverse of zero), which means that a "one" results in a transition in the current writing of the channel signal register on a magnetic record carrier. The converter of Figure 2 can be used to generate a converted signal Ci in the form of a sequence (d, k) satisfying the restriction d = l. This means that at least one "zero" is present between two subsequent "ones" in the serial data stream of the converted signal Ci. That is, a concatenation of two or more "ones" in the converted signal Ci, and thus in the channel C signal, is prohibited. It could happen that the unmodified conversion, such as by means of the device of FIG. 1 , or combinations of two original 2-bit subsequent words, may violate the constraint d = l. Those combinations are the combinations; "00 00", which by unmodified conversion, would lead to the two 3-bit channel words "101 101", "00 01", which, by unmodified conversion, would lead to the two channel words of 3 bits. "101 100"; "10 00", which, by unmodified conversion would lead to the two 3-bit channel words "001 101" and "10 01", which by unmodified conversion would lead to two 3-bit channel words "001 100" The occurrence of such combinations must be detected, so that a modified coding takes place of blocks _of two original 2-bit words in blocks of two 3-bit channel words. A modified embodiment of a converter of figure 2 which is, in addition to the "normal" coding of the original 2-bit words in 3-bit channel words, capable of detecting the combinations identified above, and is capable of performing a modified coding, so that the restriction d = l on the converted signal Ci, and thus on the C-channel signal, still satisfied, is shown in figure 3a. The converter of figure 3a includes a deviated register having four cells xi to X to receive four consecutive bits (xi, x2, x3, x4) of the serial bit stream of the original signal S. The outputs of the four cells are coupled to the corresponding inputs ii to i4 respectively, of the logic circuit LC as well as to the corresponding inputs of a detector unit DI. The detector unit DI is adapted to detect the position in the source of serial bits of the original signal, where the unmodified coding of a single original word in the bitstream corresponding to a single channel word, would lead to a violation of the constraint d = l of the converted signal Cx, and are adapted to supply a control signal as its input 10 in response to such detection. The output 10 of the detector unit DI is coupled to a control signal input 12 of the circuit logical LC '. The LC logic circuit has six outputs ?? to Os, which are coupled to the inputs of cells Yi to Y6 respectively, in the second offset register 4 '. In the absence of a control signal at the input of the control signal 12, the logic circuit LC converts the first original 2-bit word "i x2" into the three-bit word "yi y2 y3" in accordance with the Table I given above. As soon as the detector circuit Di detects a combination of two original 2-bit words (xi, 2, 3, X4), which are equal to one of the combinations given above, the LC logic circuit converts the combination according to the coding. modified as given in the following table: TABLE II As can be seen from the table, the unmodified conversion of the only two words 2-bit originals, leads to a violation of the constraint d = l, since two "ones" occur at the boundary between the two channel words obtained. The logic circuit LC 'is therefore adapted to convert in a modified coding mode, the blocks of two original 2-bit words, given in the left column of the previous table into blocks of two 3-bit channel words. , given in the right column of table II above. As can be seen, no violation of the constraint d = l occurs anymore. In addition, the modified coding in the same way preserves parity. This means in the present situation that, if the number of "ones" in the block of two original 2-bit words is odd (even) the number "ones" in the block of 2 words of 3-bit channel obtained is odd _ (pair) . In addition, one of the two original 2-bit words, which is in the previous table the second, is encoded in a 3-bit word of the channel, which is different from X of the four channel words in Table I. The reason for this is that on the receiver side, a detection of this 3-bit channel word does not belong to the set of four 3-bit channel words of Table I if possible, so that a corresponding decoding can be performed. , which is the inverse of the fluid coding with respect to table II.

The block of two words of the 3-bit channel obtained by means of the coding in accordance with Table II, is supplied by the LC logic circuit to its outputs Oi to Oe, channel words which are supplied to the six cells Yi to Y6 of the diverted record 4 '. It is clear from the described modality, that situations where a modified coding is needed, is detected by means of the Di detector using the original words. In Figure 3b a different construction of a converter is shown to carry out the modified conversion described with reference to Table II. In this case, the detection of the situations in which a modified coding should be carried out, is decided using the converted channel words. The device of Figure 3b includes a detector DI 'having 6 inputs to receive two subsequent 3-bit channel words by means of unmodified coding. The detector Di 'detects whether the two subsequent 3-bit channel words obtained using the unmodified coding equals one of the four 6-bit sequences given in the middle column under the "unmodified coding" of Table II. If so, the detector DI 'treats a switching signal as its output 10 and a routing signal AD as its output 10'. The switching signal is applied to an input of the switching signal 45 of the diverted register 4. "The addressing signal AD is applied to an input of the addressing signal 46 of a ROM 47. The detector Di 'generates one of the four possible addressing signals AD1 to AD4, in response to the detection of a corresponding one of the four 6-bit sequences in a middle column of Table II., the address signal AD1 is generated when the detector DI 'detects the sequence "101101" and generates the address signal AD4 after the detection of the 6-bit sequence "001100". ROM 47 has the 6-bit sequences shown in the right column of the stored table II. After reception of the AD1 addressing signal, the ROM supplies the 6-bit sequence "101 010" at its outputs Oi to oe, and after the reception of the AD2 addressing signal, the ROM supplies the 6-bit sequence "101 010" in your exits. After reception of the AD3 addressing signal, the ROM supplies the 6-bit sequence "000 010" at its outputs, and after reception of the AD4 addressing signal, the ROM supplies the 6-bit sequence "001 010"in your outputs. Each location of the memory-of the diverted register 4"has two inputs now, one of them is coupled to a corresponding output of the logic circuit LC, the other is coupled to a corresponding output of the ROM 47.

In the normal situation, when the restriction d = l is not violated, an unmodified conversion is carried out, and the switching signal is absent, so that the deviated register accepts the supply bits by the LC logic circuit via the inputs higher than the offset register 4. "If the constraint d = l is violated, the switching signal applied to the input of the switching signal 45 results in the deviated register accepting the 6-bit sequence, which is the sequence modified, applied by the ROM to the lower entries of the deviated register 4". The restriction k in a sequence (d, k) means that a concatenation of at most k "zeros" between two subsequent "ones" in the channel signal is allowed. It may happen that the unmodified conversion of three subsequent 2-bit original words may violate constraint k. As an example: the sequence of original words "11-11 11" by unmodified conversion would lead to the three three-bit channel words "000 000 000". If a sequence (d, k) is to be obtained where k equals 6, 1 or 8, such a combination of three 3-bit channel words should not occur. Another example is the sequence of original words "11 11 10" which by unmodified conversion, would lead to the three 3-bit channel words "000 000 001". This combination of three 3-bit channel words does not satisfy a restriction of k = l or k = 7. In addition, this combination of three 3-bit channel words can follow a previous channel word ending with a "0", so that it can lead to a violation of a restriction k = 8. In addition, the combination ends with a "1", so that it can lead to a violation of the restriction d = l, if the combination is followed by a 3-bit channel word that starts with a "1". An equivalent reasoning is valid for the sequence of original words "01 11 11". A further example is the sequence of original words "01 11 10", which by conversion without modification would lead to the three 3-bit channel words "100 000 001". This combination can, in the same way as it was previously, lead to a violation of the restriction d = l. The occurrence of such combinations would be detected, as a modified coding could take place. An embodiment of a converter which is, in addition to the "normal" coding of the original 2-bit words in 3-bit channel words, capable of detecting the combinations identified above, and is capable of performing a modified coding, shown in figure 4.

The converter of figure 4 includes a deviated register 2"having six cells Xi to Xe so that it receives six consecutive bits of the serial bit stream of the original signal S. The outputs of the six cells are coupled to the corresponding inputs ii to respectively, of the logic circuit LC "and to the corresponding inputs of a detector unit D2. The detector unit D2 is adapted to detect the position of the serial bitstream of the original signal, where the unmodified coding of the bit stream would lead to a violation of the restriction k in the converted signal Ci, and thus, in the channel signal C, and is adapted to supply a control signal at its output 15 in response to such detection. The output 15 of the detector unit D2 is coupled to a control signal input 16 of the logic circuit LC ". The logic circuit LC" has nine outputs O to a, which are coupled to the inputs of the cells ia Yg respectively, of the second offset register 4. "In the absence of control signals at the control signal inputs 12 and 16, the LC logic circuit" converts a single original 2-bit word "xi x2" into a single channel word of 3. bits "y y2 y3" in accordance with table I given above. As soon as the detector circuit DI detects a block of two original 2-bit words "x2, x3 x4", which is equal to one of the combinations given in Table II above, the LC logic circuit "converts the combination according to the conversion rule as given in table II, to obtain a block of two 3-bit channel words" yx y2 y3 y4 ys e "- As soon as detector D2 detects a block of three original 2-bit words" xx x2 x3 x4 x5 x6", which is equal to one of the combinations given above, the LC logic circuit" converts the block according to the Modified coding as given in the following table, to obtain a block of three 3-bit channel words: TABLE III The LC logic circuit "is adapted to convert to a modified coding mode, the blocks of three original 2-bit words given in the left column of Table III above, in blocks of three 3-bit channel words as it is given in the right column from the previous table. By performing the modified coding as for Table III, a channel signal has been obtained, which satisfies the constraint k = 8. In addition, the modified coding in the same way preserves parity. In addition, two of the three original 2-bit words, which are in the previous table, the second and the third, were coded in a 3-bit channel word, which is not equal to one of the four channel words from table I. The reason for this is that on the receiver side, it is possible to detect that those two consecutive 3-bit channel words do not belong to the set of the four 3-bit channel words in Table I, so that a corresponding decoding can be performed, which is inverse to the coding defined with reference to table III. The combination of three 3-bit channel words obtained by means of coding in accordance with Table III, is supplied by the LC logic circuit "at its outputs or? To 09, channel words which are supplied, at nine o'clock. cells Yx to Yg of the deviated record 4". The serial data stream of the converted signal Cx is supplied to the output terminal 8. It will be evident that, in the same manner as described with reference to FIG. 3b, the detection of the violation of the restriction can be carried out on the level of the converted signal, instead of the level of the original signal.

It has been said above that other conversion rules are possible to convert single 2-bit original words into single 3-bit channel words. Those conversion rules are given in the following three tables.

TABLE IV TABLE V TABLE VI It is evident that the extensions of these conversion rules for coding blocks of two or three original 2-bit words, in blocks of two or three three-bit channel words, can be obtained using the teachings given above. It should be noted that, although the converters have been described as converting 2-bit original words into 3-bit word of the channel, the invention is equally applicable with converters that convert (as an example), original 3-bit words to channel words of 4 bits. For the mode of the 2 to 3 bit converter 7 which performs a converted signal satisfying a displacement length restriction (1,8), the synchronization word generator 9 preferably generates a q bit synchronization word that starts with " 01"and ends with" 10". More specifically, the generator 9 generates a 15-bit synchronization word, which is equal to "010000000010010". The advantages of using this synchronization word are: the synchronization word satisfies the restriction of the displacement length (1,8), so that the use of the synchronization word does not lead to an increase in the restriction k of the restricted parity preservation code (1,8). - the synchronization word is a unique word in the sequence of the channel signal. since the synchronization word starts and ends with a "0" bit, this can always be merged between two 3-bit channel words. - since the synchronization word is only 15 bits in length, it implies a relatively low overload. The synchronization word defined above could also be used in the parity preserving coders that generate a sequence of channel words that does not satisfy a different restriction k, such as k = 7. In this situation, the synchronization word, as such, violates the restriction k of the generated channel signal. As stated above, the devices according to the invention can be used in a very suitable in an encoding array wherein one bit is inserted after each group of a plurality of bits in the serial data stream of the original signal, to perform a polarity conversion, or not. Such an encoding arrangement is shown schematically in Figure 5, where the encoder 40 is followed by the encoding device 41 according to the present invention, and a precoder IT 42, well known in the art. The output signal of the precoder ÍT 42 is applied to a control signal generator 43, which generates the control signal for the converter 40, to control whether a "0" or a "1" is inserted in the data stream in series applied to the device 41. The coding device 41 can be inserted between the converter 40 and the precoder ÍT 42 without any modification. By means of the arrangement shown in Figure 5, it is possible to include a tracking tone of a certain frequency, in the serial data stream, or to keep the DC content of the data stream at zero. Further, when the encoder device 41 is adapted to generate a sequence (d, k) as explained above, it causes the output signal of the array of Figure 4 to be an output signal RLL (d, k). The embodiments of the converter 40 are given in Bell System Technical Journal, Vol 53, No. 6, pp. 1103-1106.

Figure 6 shows a decoding device for recoding the serial data stream obtained by the encoding device, to obtain an original binary signal. The decoder device has an input terminal 60 for receiving the channel signal, input terminal 60, which is coupled to an input 50 of a bit converter 62. An output 55 of the converter 62 is coupled to an output terminal 64 of the decoder device. The device further comprises a synchronization detecting unit 66, having an input 68 coupled to the input terminal 60 and an output 70, which is coupled to a deactivatable input 72 of the converter 62. The decoder receives the channel signal with the m-bit channel words and the synchronization words via its input terminal 60. In the example of m = 3 and n = 2, the 3-bit channel words are converted into the converter 62 in the original words of 2. bits and supplied to the output terminal 64. After reception of a synchronization word, this synchronization word is detected by the detector 66, and a deactivation signal is generated via the output 70 to deactivate the converter 62 during the time interval in which the synchronization word appears at the input 50. Then, the converter 62 is activated, so that the 3-bit channel words that match the synchronization word can be converted into original 2-bit words. The decoder device of Figure 6 could, moreover, be provided with a reading unit 76 for reading a channel signal of a track on the registration carrier 23, generated by the encoding device of Figure 1, provided with the writing unit 21. The record carrier 23 can be a magnetic or optical record carrier In the example of a magnetic record carrier 23, the reading unit 76 is provided with at least one magnetic head 78 for reading the signal of channel of the track on the registration carrier 23. Figure 7 shows a mode of the converter 62 of Figure 6. The converter 62 comprises a deviated register 51, which comprises nine cells Y to Yg. The deviated register 51 functions as a series to parallel converter, so that the blocks of three 3-bit channel words are applied, to the inputs ix to ig of the logic circuit 52. The logic circuit 52 comprises the three tables I, II and III. s? a? 6 of the logic circuit 52 are coupled to the inputs of the cells Xx to X6 of the diverted register 54, which has an output 57 coupled to an output terminal 55. A detector circuit 53 having inputs ix is present to I6 coupled to the outputs of the cells from Y4 to Yg respectively, of the diverted record 51, and outputs ?? and o2 coupled to the control inputs Cx and c2 respectively, of the logic circuit 52. The detector circuit 53 is capable of detecting a bit pattern "010" in the cells Y4, Y5 and Ye of the diverted register 51, and is capable of detecting a bit pattern "010010" in cells Y4 through Yg of diverted register 51. After detection of bit pattern "010010", detector circuit 53 generates a control signal over its output o2, and after detection of a bit pattern of "010" in cells Y4, Y5 and Ye, as long as there is no "010" bit pattern in cells Y7, Y8 and Yg, this generates a control signal over its output ??. In the absence of the control signals, the logic circuit 52 converts the 3-bit channel word stored in cells Yi, Y2 and Y3 into its corresponding 2-bit original word, as for conversion table I, and supplies the word 2-bit original to cells Xx and X2. In the presence of the control signal at input ci, logic circuit 52 converts the block of two 3-bit channel words stored in cells Yi to Y into a block of two original 2-bit words, as for the table II conversion, and supplies the original 2-bit words to cells Xi to X4. In the presence of the control signal at the input c2, the logic circuit 52 converts the block of three 3-bit channel words stored in the cells Yi to Yg in a block of three original 2-bit words as for conversion table III, and supply the three original 2-bit words to cells Xi to X6. In this way, the serial data stream of the channel signal is converted to the serial data stream of the original signal. Other synchronization words that could be used in an encoding device that preserves parity, such as the device described above, will be discussed later. Instead of the 15-bit synchronization word described above, a 16-bit synchronization word that is equal to "0100000000100100", or a 17-bit synchronization word that is equal to "01000000001001000", or a word could be used. 18-bit synchronization that is equal to "010000000010010000". The three synchronization words described here can lead to a violation of restriction k, when the synchronization word is concatenated with a next 3-bit channel word, more specifically, the channel word obtained from the original word " 11"according to table I above. Such concatenation could lead to a sequence: 0100000000100100 000 ' Suppose that the next two original words are the words "10 00". The concatenation of the synchronization word with the group of channel words obtained by converting the sequence of the original word "10 00", would lead to the following sequence: "0100000000100100 000 000 010", see table II. This sequence violates the restriction k = 8. To solve this, table I could be modified, in all cases, when an original word "11" appears directly after the synchronization word, so that the "original word" 11" be converted to channel word "010". In a different solution, the conversion from "11" to "010" is carried out only, when in fact a violation of the restriction k occurred with the unmodified conversion. Although the invention has been described with reference to the preferred embodiments thereof, it should be understood that these are not limiting examples. In this way, the different modifications may be apparent to those skilled in the art, without departing from the scope of the invention, as defined in the claims. In addition, the invention falls on each and every feature or combination of novel features.

Claims (44)

CHAPTER REIVINDICATOR OR Having described the invention, it is considered as a novelty and, therefore, what is contained in the following claims is claimed.

1. A device for encoding a data bitstream of a binary original signal into a data bitstream of a binary channel signal, which satisfies a predetermined constraint (d, k), wherein the bitstream of the original signal is divided into n-bit original words, device which comprises converting means adapted to convert the original words into corresponding m-bit channel words, the conversion means are adapted to convert a block of p original words of n consecutive bits in a corresponding block of p channel words of m consecutive bits, so that the conversion for each block of _p original words of n consecutive bits substantially preserves the parity, where n, m and p are integers, m > n > 1, p = 1, and where p can vary, characterized in that the device comprises means generating synchronization words to generate a q synchronization word, which also satisfies the restrictions (d, k), the synchronization word begins with one "0" bit and ends with an "O" bit, the device further comprises fusion means for fusing the synchronization words in the data bit stream of the binary channel signal, and that q is an integer value greater than k.

2. The device according to claim 1, wherein d > 1, characterized in that the synchronization word starts with a sequence of bits "01" and ends with a sequence "10".

3. The device according to claim 1 or 2, characterized in that q = 2k-1.

4. The device according to claim 1, 2 or 3, characterized in that q = 15.

5. The device according to claim 1, 2, 3 or 4, characterized in that the synchronization word is equal to 010000000010010.

The device according to claim 1, wherein d > 1, characterized in that the synchronization word starts with a sequence of bits "01" and ends with a sequence "100".

The device according to claim 6, characterized in that q = 16.

The device according to claim 6 or 7, characterized in that the synchronization word is equal to 0100000000100100.

9. The device according to claim 1, wherein d > 1, characterized in that the synchronization word begins with a sequence of bits "01" and ends with a sequence "1000".

10. The device according to claim 9, characterized in that q = 17.

The device according to claim 9 or 10, characterized in that the synchronization word is equal to 01000000001001000.

12. The device according to the claim 1, wherein d > = 1, characterized in that the synchronization word begins with a sequence of bits "01" and ends with a sequence "10000." 13.

The device according to claim 12, characterized in that q = 18.

The device according to claim 12 or 13, characterized in that the synchronization word is equal to 010000000010010000.

15. "The device according to any of the preceding claims, characterized in that d = 1 and k = 8.

16. The device according to any of the preceding claims, characterized in that m = n + 1.

17. The device according to claim 15, characterized in that n = 2.

18. The device according to claim 17, characterized in that the device is adapted to convert unique original words into corresponding single channel words, according to the following table. :

19. The device according to claim 17 or 18, wherein the converting means are adapted to convert original 2-bit words into corresponding 3-bit channel words, to obtain a channel signal in the form of a sequence (d, k) for which it is held that d = 1, the device further comprises means for detecting the position in the bit stream of the original signal, where the encoding of unique 2-bit original words into corresponding single channel words would lead to a violation of the restriction d in the limits of the channel word and to supply a control signal in response to detection, characterized in that, in the absence of the control signal, the converting means are adapted to convert original words of _-2 unique bits, in corresponding 3-bit-unique channel words, so that the conversion for each original 2-bit word preserves parity.

The device according to claim 19, wherein, in the presence of the control signal, which occurs during the conversion of two consecutive original words, the. converting means are adapted to convert a block of two consecutive original 2-bit words, into a block of two corresponding 3-bit channel channel words, so that one of the two words in the original word block is converted to a 3-bit channel word, which is not identical to one of the four words of channel C ia CW4, to preserve the restriction d = 1, characterized in that, in the presence of t.the control signal, the converting means are adapted in addition, to convert the block of the two subsequent 2-bit original words, into a corresponding block of two subsequent 3-bit channel words, so that the conversion of the block of two subsequent 2-bit original words preserves the parity.

21. The device according to claim 20, characterized in that the converting means are adapted to convert the blocks of two consecutive 2-bit original words, into blocks of two consecutive 3-bit channel words, in accordance with the coding given in The following table:

22. The device according to claim 20 or 21, wherein k has a value greater than 5, the device is further provided with means for detecting the position in the bit stream of the original signal, where the coding of the original words of 2 unique bits in single 3-bit channel words, would lead to a violation of the k restriction and supply a second control signal in response to detection, characterized in that, in the presence of the second control signal, which occurs during the conversion of three original words of 2 consecutive bits, the converters are adapted to convert a block of three original words of 2 consecutive bits, in a block of three channel words of corresponding 3"consecutive bits, so that the conversion of the block of three original 2-bit words preserve parity, the converting means are also adapted to convert two of the three original words in the block in corresponding 3-bit channel words, not identical to the four words of channel C ia CW4, to preserve the restriction of k

23. The device according to claim 22, characterized in that the converting means are adapted to convert blocks of three consecutive original 2-bit words into blocks of three consecutive 3-bit channel words, in accordance with the code given in the following table: block of 3 original words block of 3 words of channel 11 11 11 000 010 010 11 11 10 001 010 010 01 11 10 101 010 010 01 11 11 100 010 010

24. The device according to claim 18, also dependent on claims 6, 8, 9, 11, 12 or 14, characterized in that, if the original 2-bit word follows directly the synchronization word inserted in the channel, the signal is equal to "11", the device is adapted to convert the original word "11" in the channel word "010".

25. The recording device for recording a channel signal in a track on a record carrier, the recording device is characterized in that it comprises the coding device, according to any of the preceding claims, and in that it comprises writing means for Write the channel signal generated by the encoder device on the track on the record carrier.

26. The record carrier, characterized in that it is obtained with the recording device according to claim 25.

27. The record carrier according to claim 26, characterized in that the registration carrier is an optical reservation carrier.

28. A device for decoding a data bit stream, of a binary channel signal that satisfies the restriction (d, k), obtained by means of the encoding device according to any of claims 1 to 23, to obtain a flow of data bits of a binary original signal, the device comprises deconverting means for deconverting a block of p consecutive channel words, in a corresponding block of p consecutive original words, so that the conversion per_ each block retains parity, where n, m and p are integers, m > n, p = l, and where p can vary, characterized in that the device further comprises means for detecting the presence of a q synchronization word in the data bit stream, the synchronization word also satisfies the restriction ( d, k), the restriction word begins with a "0" bit and ends with a "0" bit, and because d, k and q are integers greater than 0 and because q is greater than k.

29. The device according to claim 28, wherein d = l, characterized in that the synchronization word starts with a sequence of bits "01" and ends with a sequence "10".

30. The device according to claim 28 or 29, characterized in that q = 2k-l.

31. The device according to claim 28 or 30, characterized in that q = 15.

32. The device according to claim 28, 29, 30 or 31, characterized in that the synchronization word is equal to 010000000010010.

33. The device according to claim 28, wherein d = l, characterized in that the word The synchronization starts with a sequence of bits "01" and ends with a sequence "100".

34. The device according to claim 33, characterized in that q = 16.

35. The device according to claim 33 or 34, characterized in that the synchronization word is equal to 0100000000100100.

36. The device according to claim 28, wherein d = l, characterized in that the synchronization word begins with a sequence of bits "01" and ends with a sequence "1000".

37. The device according to claim 36, characterized in that q = 17.

38. The device according to claim 36 or 37, characterized in that the synchronization word is equal to 01000000001001000.

39. The device according to claim 28, wherein d == l, characterized in that the synchronization word begins with a sequence of bits "01" and ends with a sequence "10000".

The device according to claim 39, characterized in that q = 18.

41. The device according to claim 39 or 40, characterized in that the synchronization word is equal to 010000000010010000.

42. The reproducing device for reproducing an image channel signal of a track on a carrier of registration, the player device is characterized in that it comprises a coding device according to any of claims 28 to 41, and in that it comprises reading means for reading the channel signal of the track on the record carrier, for supplying the channel signal to the decoder device for decoding.

43. A method for encoding a data bitstream of an original binary signal into a data bit stream of a binary channel signal satisfying a predetermined constraint (d, k), wherein the bitstream of the signal original is divided into n original words of n bits, the method comprises the steps of: converting the original words of n bits into corresponding n-bit channel words, so that the block of p original words of n consecutive bits is converted into a corresponding block of p channel words of n consecutive bits, so that the conversion of each block of p original words of n consecutive bits retains the parity, where n, m and p are integers, m > n > 1, p = 1, and where p can vary, characterized in that the method further comprises the step of generating a q-bit synchronization word that also satisfies the restriction (d, k), the synchronization word begins with a "0" bit and ends with a "0" bit, and comprises the step of merging the synchronization word in the data bit stream of the binary channel signal, and because q is an integer value greater than k.

44. The method according to claim 43, characterized in that it also comprises the step of registering the channel signal on a track on a record carrier.