MXPA99007750A - DEVICE FOR ENCODING/DECODING n-BIT SOURCE WORDS INTO CORRESPONDING m-BIT CHANNEL WORDS, AND VICE VERSA - Google Patents

Abstract

A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (y1, y2, y3). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity preserving (table I) (Fig. 1). The relations hold that m>n=1, p=1, and that p can vary. Preferably, m=n + 1. The device is adapted to convert the 8-bit bitsequence'00010001'in the source signal into the 12-bit bitsequence'100010010010'and to convert the 8-bit bitsequence'10010001'into the 12-bit bitsequence'000010010010', in order to limit the repeated minimum transition runlength in the channel signal. Also other 8-bit sequences require a specific encoding into 12-bit bitsequences in order to limit the k-constraint of the channel signal to 7. Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

Description

DEVICE FOR CODING / DECODING ORIGINAL WORDS OF n BITS IN CORRESPONDING M BITS, AND VICEVERSA CHANNEL WORDS The invention relates to a device for encoding a data bit stream of an original binary signal and a data bit stream of a channel bit signal, wherein the bit stream of the original signal is divided into original words of n bits, device which comprises conversion means adapted to convert the original words into corresponding m-bit channel words, the conversion means are adapted to convert a block of p original words of n consecutive bits into a corresponding block of p words of channel of consecutive m bits, so that the conversion of each block of p original words of n consecutive bits substantially preserves the parity, where n, m and p are integers, m > n > 1, p = l, and where p can vary. The invention also relates to a recording device comprising the encoding device, for recording the channel signal on a record carrier, with the record carrier itself, with a coding method, and a device for decoding a stream of data. data bits of a channel binary signal obtained by means of an encoding device, to obtain a data bitstream of an original binary signal. A coding device mentioned above is known from ÜSP 5,477,222 (PHN 14448). The document describes a device for encoding a data bitstream of an original binary signal in a data bit stream of a channel bit signal, which satisfies a constraint of the differential coordinate (1, 8). This means that, in a serial data stream of the channel signal, at least one "zero" and a maximum of eight "zeros" are present between two consecutive "ones" in the channel signal. It should be noted in this regard that an additional precoding step, such as a 1T precoding, is normally applied to the restricted sequence (1, 8), resulting in a limited sequence in the differential coordinate with a minimum differential coordinate of 2 and a maximum differential coordinate of 9. It is known that the conversion preserves parity. "Preserve parity" means that the parity of the original words of n bits to be converted equals the parity (after the addition of module 2) of the corresponding m bit channel words, in which they are converted. As a result, the conversion device from n to m as claimed, does not influence the polarity of the signal.

Since the conversion preserves parity, efficient DC control can be applied, such as by inserting DC control bits into a data stream of the original words. The object of the invention is to provide an improved device for coding original words of n bits in the corresponding m-bit channel words. The device according to the invention is characterized in that the conversion means are adapted to convert the 8-bit bit sequence "00010001" into the bit stream of the original binary signal in the 12-bit bit sequence "100010010010" of the channel binary signal. The device according to the invention is also characterized by any of claims 2, 5, 6, 7 or 8. The invention was based on the recognition that, the coding according to the known coding device, where the sequences relatively long comprise only the transition differential coordinate that may occur, leading to a deterioration of the bit detection in a bit detector in a receiver, after the subsequent transmission and decoding of the channel signal in the receiver. In a channel signal that satisfies a specific differential coordinate constraint, such as (1, 7) or (1, 8), this means that relatively long sequences "0101010101" occur, resulting in relatively long sequences "001100110011" in the sequence after 1T precoding. The device according to the invention restricts the lengths of those sequences, so that improved bit detection in a receiver can be obtained. The encoding device according to the invention can be used in combination with a bit adding unit, in which a bit is added to the code words of a certain length in the original signal. The signal obtained can be applied to the coding device of the present invention. The channel signal of the encoding device is applied to a precoder 1T. The purpose of the adding unit of bits, is to add a "0" or a "1" to the consecutive code words included in the input signal of the converter, to obtain an output signal of the precoder, which is free of DC, or it includes a pilot tracking signal that has a certain frequency. The output signal of the precoder is registered on a record carrier. The addition of a "0" bit in the input signal of the converter, results in the polarity of the output signal the precoder 1T remaining the same.

The addition of a bit "1" results in a reversal of the polarity in the output signal of the precoder 1T. The converter, therefore, has an influence on the output signal of the precoder 1T, so that the value of the digital sum of the operation of the output signal of the precoder 1T can be controlled so that it has a desired pattern as a function of time. . The invention will be further described in the following description of the figures, in which Figure 1 shows a first embodiment of the encoding device, Figure 2 shows a second embodiment of the encoding device, Figure 3 shows a third embodiment of the encoding device, Figure 4 shows a fourth embodiment of the encoding device, Figure 5 shows the application of the device in an array for inserting a bit at equidistant positions in the original serial signal, Figure 6 shows a first embodiment of the encoding device, and Figure 7 shows a second embodiment of the encoding device.

Figure 1 shows an encoding device that is capable of converting 2-bit original words into 3-bit channel words. The device described herein is, in fact, the device also described in USP 5,477,222, with further modifications to achieve the objectives of a minimization of the minimum repeated transition coordinate differential. The device has an input terminal 1, for receiving a data bit stream from an original binary signal S. The terminal 1 is coupled to an input of a shift register 2 having eight cells Xi to X », in the present example, to receive eight consecutive original bits of the original signal S. The shift register 2 functions as a serial-in-parallel converter. The outputs of the cells are coupled to the corresponding inputs ii to i8, respectively, of an LC logic circuit, to supply the logical values (xx,, xß) of the original bits present in the cells.

The LC logic circuit is part of the CM conversion means. The device further includes a second shift register 4 having twelve cells Yi to Yi2. The LC logic circuit has twelve outputs Oi to? 2. Those outputs of the logic circuit LC are coupled to the corresponding inputs of the twelve cells Yi to Y? 2, respectively, of the shift register 4. An output 6 of the shift register 4 is coupled to an output terminal 8. The registration of offset 4 operates as a parallel-serial converter, to obtain the binary signal of channel C. In addition, a detector unit 10 is available to detect specific sequences in the serial data stream of the original signal S. For that purpose, the outputs of the eight cells Xi to X8 of the shift register 2 are coupled to the corresponding inputs, denoted 12, of the detector unit 10. In the present embodiment, the detector unit 10 has three outputs, denoted as O, 02 and o3, to generate a first, second and third control signals, respectively. Those outputs are coupled to the corresponding control signal inputs Ci, c2 and C3, respectively, of the LC logic circuit. The operation of the logic circuit LC in response to the control signals applied to its inputs Ci, c2 and c3, is as follows. The LC logic circuit is capable of converting original 2-bit SW words into 3-bit channel words, so that the conversion of each original 2-bit word preserves parity. This means that the number of "ones" in the original word to be converted is equal to the number of "ones" in the corresponding channel word, an addition of module 2 is carried out in the "ones" in the channel word . 0, in other words: if the number of "ones" in the original word is even, the number of "ones" in the channel word will be even. Y: if the number of "ones" in the original word is odd, the number of "ones" in the channel word will be odd. As an example, the LC conversion means are adapted to convert the original 2-bit SW words into 3-bit CW channel words according to the following table: TABLE I original word (Xl / 2) channel word (yi, y2, _ / 3) S i 00 CWi 101 SW2 01 CW2 100 SW3 10 cw3 001 SW4 11 CW4 000 It should be noted here that the first bit in the original word was first applied to the shift register 2 and that the first bit in the channel word was first supplied from the output 6 of the shift register 4. It should also be noted here that the logic circuit LC converts the original 2-bit words stored in cells Xi, X2 into 3-channel words and stores those channel words in cells Yi, Y2, Y3, of shift register 4, in response to an absence of any control signal at the control signal inputs Ci, c2, and c3. Each conversion in this way is followed by a displacement of two positions to the left in the shift register 2, and a shift of three positions to the left of the shift register 4. The displacement of two positions in the register offset 2 to make the shift register 2, and thus the converter, ready for a subsequent conversion. The displacement of three positions in the shift register 4 is required to transmit the generated 3-bit word of the word. The device of Figure 1 can be used to generate a C-channel signal in the form of a sequence (d,) that satisfies the constraint of d = l. This means that at least one "zero" is present between two subsequent "ones" in the serial data stream of the channel signal. That is, a concatenation of two or more "ones" in the channel signal is prohibited. It may happen that unmodified conversion, such as by means of the device of Figure 1, of combinations of two subsequent 2-bit original words have the constraint d = l. Those combinations are the combinations; "00 00", which, by unmodified conversion would lead to the two 3-bit channel words "101 101"; "00 01", which, by unmodified conversion would lead to the two channel words "3-bit" 101 100";" 10 00", which, by unmodified conversion would lead to the two 3-bit channel words "001 101" and "10 01", which, by unmodified conversion would lead to the two 3-bit channel words "001 100." The occurrence of such combinations should be detected, so that a modified coding can take place. of blocks of two original 2-bit words, in blocks of two 3-bit channel words.Therefore, the device of Figure 1 is also capable of "normal" encoding of original 2-bit words in 3-bit channel words, capable of detecting the combinations identified above, and is capable of performing a modified coding, so that the restriction d = 1 on the channel signal is still satisfied.

Due to the fact that the outputs of the cells Xi to X4 of the shift register 2 are coupled to the corresponding inputs of the detector unit 10, this detector unit 10 is able to detect the position in the serial bitstream of the signal original, where the encoding of original 2-bit words unique in the bitstream in the corresponding single 3-bit channel words, lead to a violation of the constraint d = 1 in the C-channel signal, and are adapted to supply the control signal at its output I heard in response to such detection. More specifically, the detector unit 10 detects whether the cells Xi to X4 comprise one of the 4-bit sequences given in table II, and generates a first control signal at its output oi. As soon as the detector circuit 10 detects a combination of two original 2-bit words present in the four cell positions xi, x2, x, x4, combination which is equal to one of the combinations given in the column on the left of Table II, the LC logic circuit converts the combination according to the modified coding as given in Table II: TABLE II As can be seen from the table, the unmodified conversion of the two original 2-bit words leads to a violation of the restriction d = 1, since two "ones" occur at the boundary between the two obtained channel words. The LC logic circuit is, therefore, adapted to convert in a modified coding mode, the blocks of two original 2-bit words given in the left column of the previous table, into blocks of two 3-word words. bits as given in the column on the right in Table II above. As can be seen, a violation of the constraint d = l does not occur anymore. In addition, the modified coding in the same way preserves parity. In addition, one of the two original 2-bit words, the second of which is in the previous table, is coded to a 3-bit channel word, which is not equal to one of the four channel words in the table I. The reason for this is that on the receiving side, a detection of this 3-bit channel word is possible, which does not belong to the set of four 3-bit channel word of Table I, so that a corresponding decoding, which is inverse to the coding defined with reference to table II. The block of two words of channel of 3 bits obtained by means of the coding according to the table II, is supplied by the logic circuit LC to its outputs ?? a oß, channel words which are supplied to the six cells Yi to Ye of the shift register 4. It should be further clarified that, a conversion of two original 2-bit words into two 3-bit channel words by the LC converter unit is followed by a shift of four positions to the left in the shift register 2 and a shift of six positions to the left in the shift register 4. The displacement of four positions in the shift register 2 is required to make the shift register 2, and thus the converter, is ready for a subsequent conversion. The displacement of six positions in the shift register 4 is required to transmit the two generated 3-bit channel words. The restriction of k in a sequence (d, k) means that a concatenation of at most k "zeros" between two subsequent "ones" in the channel signal is allowed. It may happen that the unmodified conversion of three subsequent 2-bit original words may violate the restriction of k. As an example: the sequence of original words "11 11 11", lead by unmodified conversion to the three 3-bit channel words "000 000 000". If a sequence (d, k) must be obtained, where k is equal to 6, 7 or 8, such a combination of three 3-bit channel words should not occur. Another example is the sequence of original words "11 11 10", which, by unmodified conversion, will lead it to the three 3-bit channel words "000 000 001". This combination of three 3-bit channel words does not satisfy a restriction of k = 6 ok = 7. In addition, this combination of three 3-bit channel words can follow a previous channel word ending with a "0", so that it can lead to a violation of the restriction of k = 8. In addition, the combination ends with a "1", so that it can lead to a violation of the constraint of d = 1, if the combination is followed by a 3-bit channel word, which starts with a "1". An equivalent reasoning is valid for the sequence of the original channels "01 11 11". A further example is the sequence of original words "01 11 10", which, by unmodified conversion, will lead to the three 3-bit channel words "100 000 001". This combination may, in the same way as previously, lead to a violation of the restriction of d = 1. The occurrence of such a combination shall be detected, so that a modified coding may take place. Thus, the device of figure 1 is, in addition to coding in a "normal" way original 2-bit words in 3-bit channel words, as well as coding in a modified manner, according to table II, capable of detecting the combinations previously identified, and is capable of performing a modified coding, so that the restriction of k on the channel signal is still satisfied. Due to the fact that the outputs of the cells Xi to X6 of the shift register 2 are coupled to the corresponding inputs of the detector unit 10, this detector unit 10 is able to detect the position in the serial bitstream of the detector. original signal, where the unmodified coding will lead to a violation of the restriction of k in the C-channel signal, and are adapted to supply a control signal at its output or 2 in response to such detection. More specifically, the detector unit 10, detects whether the cells Xi to X6 comprise one of the 6-bit sequences given in table III, and generates a second control signal at its output o2. As soon as the detector circuit 10 detects a combination of three original 2-bit words present in the six positions of the cell xi, x2, x3, x4, x5, x6, combination which is equal to one of the combinations given in FIG. column on the left of table III, the logical circuit LC converts the combination according to the modified coding as shown in table III: TABLE III The LC logic circuit converts in the second modification of the coding mode, the blocks of three original 2-bit words given in the column on the left of the previous table III, into the blocks of three 3-bit word words as given in the column on the right in the previous table. By performing the modified coding as for Table III, a channel signal has been obtained, which satisfies the restriction of k = 8. In addition, the coding modified in the same way preserves the parity. This means in the present situation that, if the number of "ones" in the combination of three original 2-bit words is odd (even), the number of "ones" in the combination of three three-bit channel words obtained is Odd Couple) . In addition, two of the three original 2-bit words, the second of which is in the previous table and one in the third, is encoded in a 3-bit channel word, which is not equal to one of the four words of the channel in Table I. The reason for this is that on the receiving side, it is possible to detect those two consecutive 3-bit channel words that do not belong to the set of four 3-bit channel words in Table I, but a corresponding decoding can be performed, which is inverse to the coding defined with reference to table III. The block of three words of channel of 3 bits obtained by means of the coding in accordance with Table III, is supplied by the logic circuit LC to its output, oi to 09, channel words which are supplied to the nine cells Yi to Yg of the shift register 4. It should be further clarified that, a conversion of three original 2-bit words into three 3-bit channel words by the LC converter unit, is followed by a shift of six positions to the left of the shift register 2 and a displacement of nine positions to the left in the shift register 4. The displacement of six positions in the shift register 2 is required to make the shift register 2, and thus the converter, ready for a Subsequent conversion The displacement of nine positions in the shift register 4 is required to transmit the three generated 3-bit channel words. A further requirement to encode the original signal is that the minimum transition differential coordinate repeated in the channel signal should be limited. The minimum repeated transition differential coordinate is defined as the length of the sequence of subsequent transitions between "0" and "1", or: a sequence "01010101010 ...", in the case where the restriction of d equals 1. As an example, the sequence of bits "00 01 00 01" results, after the conversion modified using Table II, the sequence of bits "101 010 101 010". In the same way, the sequence of bits "10 01 00 01" results, after the modified conversion using Table II, the bit sequence "001 010 101 010". Such sequences impair the detection of bits of a receiver. A restriction on the length of the sequences of 01 is thus required. Due to the fact that the outputs of the cells Xi to X8 of the shift register 2 are coupled to the corresponding inputs of the detector unit 10, this detector unit 10 is capable of detecting the position in the serial bit stream of the original signal where the unmodified coding will lead to a violation of the requirement that the minimum repeated transition differential coordinate be limited and be adapted to supply a control signal to its output o3 in response to such detection. More specifically, the detector unit 10 detects that the cells Xi to X8 comprise one of the 8-bit sequences given in table IV, and generate a third control signal at its output o3. As soon as the detector circuit 10 detects a combination of four original 2-bit words present in the eight positions of the cells xi, x2, x3, x4, x5, x6, x7, x8, combination which is equal to one of the combinations given in the left column of table IV, the LC logic circuit converts the combination according to the modified coding as given in Table IV, into a 12 bit bit sequence as given in the column of the right of table IV.

TABLE IV The modified conversion as for table IV again preserves the parity. It should be noted that the bitstream of the channel words is in NRZI notation (no return to the inverse of zero), which means that a "one" results in a transition in the current write to record the channel signal on a magnetic record carrier. In the above, situations where a modified coding was required are detected by the detector unit 10 of the original words. It should be noted, however, that the detection could be carried out on the generated channel words. In this respect, reference is made to Figure 2b in USP 5,477,222. Figure 2 shows another embodiment of the coding device, in which the detection of situations where a modified coding is required is carried out based on the channel words generated by an unmodified coding as for table I. The device of the figure 2 includes a detector 10 'having 12 inputs to receive the four subsequent 3-bit channel words obtained by means of unmodified coding as for table I in the LC circuit. The detector 10 'detects whether the two subsequent 3-bit channel words at the outputs o to a or of the LC circuit, obtained using the unmodified coding, are equal to one of the four 6-bit sequences given in the middle column. under the "unmodified coding" of Table II. If so, the detector 10 'emits a switching signal at its output 12 and a direction signal AD at its output 12'. The switching signal is applied to a switching signal input 45 of the shift register 4 '. The address signal AD is applied to an address signal input 46 of a ROM 47. The detector 10 'generates one of four possible direction signals AD1 to AD4, in response to the detection of a corresponding one of the four sequences of 6. bits in the middle column of table II. As an example, the address signal AD1 is generated when the detector 10 'detects the sequence "101101" and generates the address signal AD4 after detection of the 6-bit sequence "001100". ROM 47 has the 6-bit sequences shown in the right column of the stored table II. After reception of the address signal AD1, the ROM supplies the 6-bit sequence "100 010" to its outputs at 05, and after reception of the address signal AD2, the ROM supplies the 6-bit sequence "101 010" to those outputs. After reception of the address signal AD3, the ROM supplies the 6-bit sequence "000 010" to those outputs, and after reception of the address signal AD4, the ROM supplies the 6-bit sequence "001 010"to those exits. Each location of the memory of the shift register 4 'now has two inputs, one of which is coupled with a corresponding output of the logic circuit LC, the other being coupled to a corresponding output of the ROM 47. In response to the switching signal applied to input 45, the shift register accepts the information supplied to its lower inputs and shifts its content six positions to the left. As a result, a 6-bit sequence modified by the shift register 4 'to output 8 is supplied.

The detector 10 'also detects whether the three subsequent 3-bit channel words at the outputs O to Og of the LC circuit, obtained using the unmodified coding, are equal to one of the four 9-bit sequences given in the column of medium under the "unmodified coding" of Table III. If so, the detector 10 'issues the switching signal at its output 12 and a direction signal AD at its output 12'. The detector 10 'generates one of four possible direction signals AD5 to AD8, in response to the detection of a corresponding one of the four 9-bit sequences in the middle column of Table III. As an example, the address signal AD5 is generated when the detector 10 'detects the sequence "000 000 000" and generates the address signal AD8 after the detection of the 9-bit sequence "100 000 000". ROM 47 has the 9-bit sequences shown in the right column of table III stored. After reception of the address signal AD5, the ROM supplies the 9-bit sequence "000 010 010" in its outputs ?? to Og, and after reception of the AD6 signal, the ROM supplies the 9-bit sequence "001 010 010" to those outputs. After reception of the AD7 signal, the ROM supplies the 9-bit sequence "101 010 010" to those outputs, and after the reception of the AD8 direction signal, the ROM supplies the 9-bit sequence "100 010 010"to those exits.

In response to the switching signal applied to the input 45, the shift register accepts the information supplied to its lower inputs and shifts its content nine positions to the left. As a result, a 9-bit sequence modified by a shift register 4 'is supplied to the output 8. The detector 10' also detects whether the four subsequent 3-bit channel words in the outputs heard from the 2? LC circuit, obtained using the unmodified coding, are equal to the following two 12-bit sequences: "101 010 10 010" or "001 010 101 010". If so, the detector 10 'emits a switching signal at its output 12 and a direction signal AD at its output 12'. The detector 10 'generates one of the two possible direction signals AD9 and ADIO, respectively. In response to detection a corresponding one of the two 12-bit sequences given above. As an example, the address signal AD9 is generated when the detector 10 'detects the sequence "101 010 101 010" and generates the address signal ADDITIONAL after detection of the 12-bit sequence "001 010 010 101". ROM 47 has the 12-bit sequences shown in the right column of table IV stored. After reception of the AD9 address signal, the ROM supplies the 12-bit sequence "100 010 010 010" to its outputs or? at 0? 2, and after receiving the address signal ADDITION, the ROM supplies the 12-bit sequence "000 010 010 010" to those outputs. In response to the switching signal applied to the input 45, the shift register accepts the information supplied to its lower inputs and shifts twelve positions to the left are contained. As a result, a 12-bit sequence supplied by the shift register 4 'to output 8 is supplied. In the normal situation, when neither of the two restrictions is violated, the unmodified conversion is carried out according to the table I, and the switching signal is absent, so that the shift register accepts the bits supplied by the LC logic circuit, via the upper inputs of the shift register 4 '. It has been said above that other conversion rules are possible to convert single 2-bit original words into single 3-bit channel words. Those conversion rules are given in the following three tables.

TABLE IV TABLE V TABLE VI TABLE VI (continued) It is evident that extensions of those conversion rules can be obtained to code blocks of two or three original 2-bit words in blocks of two or three 3-bit channel words using the teachings given above. Figure 3 shows a modification of the device of figure 1. The device of figure 3 is capable of generating a channel signal with a lower restriction of k, more specifically, a restriction of k, k = 7. The modification is found in the addition of an additional shift register 70, which has three storage locations 70.1, 70.2 and 70.3, which have inputs 72 coupled to output 6 of shift register 4 and output 74.1, 74.2 and 74.3, being the outputs of the storage places 70.1, 70.2 and 70.3, respectively. In addition, a detector 76 having the inputs 78.1, 78.2 and 78.3, coupled to the outputs 74.1, 74.2 and 74.3, respectively, of the shift register 70, and having an output 82 is present. The outputs 74.1 of the shift register 70 it is also coupled to a control input C5 of the conversion circuit LCm, and the output 82 of the detector 76 is coupled to a control input c4 of the conversion circuit LCm. In addition, the detector 10 in FIG. 1 is slightly modified in the detector 80 in FIG. 3. In the meanwhile the conversion of original 2-bit words into 3-bit channel words, the conversion of two original 2-bit words into two 3-bit channel words, and the conversion of three 2-bit words into three 3-bit channel words, is related, this conversion is the same as explained above with reference to the device of Figure 1. The modification is specifically in the conversion of the 8-bit bit sequences of a specific form that occurs in the original signal. The detector 80 is, in addition to detecting the 4-bit bit sequences of Table II and the 6-bit bit sequences of Table III (as explained with reference to the modality in the figure 1), capable of detecting the 8-bit bit sequences given in Table VII below. In response to such detection, the detector 80 generates a control signal at its output o3, control signal, which is applied to the control input c of the LCm logic circuit. The shift register 70 has the last three bits of the channel signal generated so far, stored in its storage locations 70.1, 70.2 and 70.3, where the storage location 70.1 has the last bit of the channel signal generated so far, stored in it. The last bit of the channel signal, which is either a "0" or a "1" bit, was used as an additional control signal for the LCm logic circuit, and was supplied to a LCm logic circuit via the input of control c. In addition, the detector 76 is adapted to generate a control signal at its output 82, when the shift register 70 has the 3-bit bit sequence "010" stored in its storage locations 70.1, 70.2 and 70.3. This control signal is supplied to the LCm logic circuit via its control input c5. According to Table VII, the LCm logic circuit converts the 8-bit bit sequence "00 01 00 01" into its corresponding 12-bit bit sequence "100 010 010 010", in response to the control signal applied to its control input c3, and regardless of the control signals that appear in its inputs c4 and C5. In addition, the LCm logic circuit converts the 8-bit bit sequence of "10 01 00 01" into the 12-bit bit sequence "100 000 010 010", in response to the control signal at its input c which is equal to "0", and converts the 8-bit bit sequence into the 12-bit bit sequence "000 010 010 010", in response to the control signal that is equal to "1". When the 8-bit bit sequence "11 10 00 00" appears at inputs ii to i8 of the logic circuit, a control signal is generated by the detector 80 at its output o3. Further, when the content of the shift register 70 is equal to the 3-bit sequence "010", a control signal is generated by the detector 76. In response to both control signals, the LCm logic circuit converts this sequence of bits 8 bits in the 12-bit bit sequence "000 001 010 010", as shown in table VII. When the 8-bit bit sequence "11 10 00 10" appears at inputs ii to i8 of the logic circuit, a control signal is generated by the detector 80 at its output or. Further, when the content of the shift register 70 is equal to the 3-bit bit sequence "010", a control signal is generated by the detector 76. In response to both control signals, the LCm logic circuit converts this sequence. of 8-bit bits in the 12-bit bit sequence "100 001 010 010", as shown in Table VII. When the 8-bit bit sequence "11 10 00 01" appears at inputs ii to i8 of the logic circuit, a control signal is generated by the detector 80 at its output o3. Further, when the content of the shift register 70 is equal to the 3-bit bit sequence "010", a control signal is generated by the detector 76. In response to both control signals, the LCm logic circuit converts this sequence. of 8-bit bits in the 12-bit bit sequence "001 010 010 010", as shown in Table VII. When the 8-bit bit sequence "11 10 00 01" appears at inputs ii to i8 of the logic circuit, a control signal is generated by the detector 80 at its output o3. Further, when the content of the shift register 70 is equal to the 3-bit bit sequence "010", a control signal is generated by the detector 76. In response to both control signals, the LCm logic circuit converts this sequence. of 8-bit bits in the 12-bit bit sequence "101 010 010 010", as shown in Table VII.

TABLE VII TABLE VII (Continued) With this conversion, the channel signal satisfies k = 7, and limits the minimum transition differential coordinate to 6. Figure 4 shows a modification of the modality of Figure 2, modified to allow conversion according to Table VII previous. The embodiment of Figure 2 was modified to the embodiment of Figure 4, by adding the shift register 7 to the detector unit 76, which supplies its control signals to the control inputs c4 and c5 of the ROM 47 '. No further description of the mode will be given, as with the above description of the embodiment of Figure 2 with explanation of the modified coding of a number of 8 bit bit sequences in the original signal, it is clear to one skilled in the art. technique as developing a construction for the embodiment of Figure 4, without employing any inventive step. As said above, the devices described above are very suitable for being included in the coding array, where a bit is inserted after each q bits in a serial data stream to perform a polarity conversion, or not. Each coding arrangement is shown schematically in Figure 5, where the encoder 40 is followed by the encoding device according to the present invention 41, and a precoder 1T 42, well known in the art. The output signal of the precoder 1T is applied to a control signal generator 43, which generates a control signal for the converter 40, to control whether a "0" or a "1" is inserted in the data stream in series applied to the converter 40. The coding device 41 can be inserted between the converter 40 and the precoder 1T 42 without any modification, since the encoder 41 has no influence on the polarity of the signal generated by the converter 40. By means of the arrangement shown in Figure 5, it is possible to include a tracking tone of a certain frequency in the serial data stream, or to keep the DC content of the data stream at zero. Further, when the device 41 is adapted to generate a sequence (d, k) as explained above, it causes the output signal of the array of Figure 4 to be an output (d, k) RLL. The embodiments of the converter 40 are given in Bell System Technical Journal, Vol. 53, No. 6, pp. 1103-1106. The output signal of the precoder 42 1T is supplied to a writing unit 21 for writing the signal on a track on a record carrier 23. The record carrier 23 can be a magnetic record carrier in longitudinal or disk form. The record carrier could also be the optical record carrier, such as an optical disk 23 '. The writing unit 21 comprises a writing head 25 ', which is a magnetic writing head, when the signal is recorded on a magnetic record carrier or an optical writing head, when the signal is recorded on a record carrier optical. Figure 6 shows an embodiment of a decoding device, for decoding the serial data stream, obtained by the decoder device of figure 1 or 2, to obtain an original binary signal. The decoder device has an input terminal 50 for receiving the channel signal, input terminal 50, which is coupled to an input 56 of a shift register 51, which comprises twelve cells Yi to Y? 2. The shift register 51 functions as a serial-parallel converter, so blocks of four 3-bit channel words are applied to the inputs ii ai 2 of a logic circuit 52. The logic circuit 52 comprises the four Parts I, II, III and IV. The outputs O to a8 of the logic circuit 52 are coupled to the inputs of the cells Xi to X8 of a shift register 54, which has an output 57 coupled to an output terminal 55. A detector circuit 53 having inputs is present. ii to i9, indicated schematically by the reference number 60, coupled to the output of the cells Y4 to Yi2, respectively, of the shift register 51, and outputs Oi, o2 and o3 coupled to the control inputs Ci, c2 and c3, respectively, of the logic circuit 52. The detector circuit 53 is capable of (a) detecting a bit pattern "010 010 010" in the cells Y to Y? 2 of the shift register 51, (b) detecting a bit pattern "010 010"in cells Y4 through Y9 of shift register 51, while the bits in cells Y? o, n and Y12 are not equal to" 010", and (c) detect a bit pattern" 010"in cells Y4, Y5 and Y6, while the bits in cells Y7, Y8 and Y9 are not equal to "010". After detection of the bit pattern "010 010 010", the detector circuit 53 generates a control signal at its output oi, after detection of the bit pattern" 010 010"in the cells Y4 through Y9, the detector circuit 53 generates a control signal at its output o2, after detection of pattern "010" in cells Y4 through Y6, detector circuit 53 generates a control signal at its output o3, whereas, when there is no "010" bit pattern in cells Y4 through Y12, no control signal is generated at its outputs In the absence of the control signals, logic circuit 52 converts the 3-bit channel word stored in cells Yi, Y2 and Y3 into its corresponding 2-bit original words, as for the conversion table I, and supplies the original 2-bit word in cells Xi and X2.In the presence of the control signal at input c3, logic circuit 52 converts the block of two stored 3-bit channel words in the cells Yi to Y? in a block of two words originates 2 bits, as for the conversion table II, and supplies the two original 2-bit words in cells Xi to X4. In the presence of the control signal at input c2, logic circuit 52 converts the block of three 3-bit channel words stored in cells Yi to Y9 into a block of three original 2-bit words, as for the table conversion III, and supplies the three original 2-bit words in cells Xi to X ^. In the presence of the control signal at the input Ci, the logic circuit 52 converts the block of four 3-bit channel words stored in the cells Yi to Y12 into a block of four original 2-bit words, as for the table IV conversion, and supplies the four original 2-bit words in cells Xx to X8.

In this way, the serial data stream of the channel signal is converted to the serial data stream of the original signal. The coded information supplied to the input 50 could have been obtained from the reproduction of the information of the record carrier, such as a magnetic record carrier 23, or an optical record carrier 23 '. The device in FIG. 6 so far comprises a reading unit 62 for reading the information of a track on the record carrier, where the unit 62 comprises a read head 64 for reading the information of such a track. Figure 7 shows one embodiment of the decoder for decoding the channel signal generated by the decoders of Figures 3 or 4. From Table VII, it is clear that the specific 12-bit bit sequences in the channel signal that could be detected according to table VII, they can not all be detected by the sequence "010 010 010". Therefore, the detector 53 'requires feeding the 12-bit bit sequence to identify all seven 12-bit bit sequences included in Table VII. Although the invention has been described with reference to the preferred embodiments thereof, it should be understood that these are not limiting examples. Thus, various modifications may be apparent to those skilled in the art, without departing from the scope of the invention, as defined in the claims. As an example, the decoder device of Figure 6 could be modified in a device in which the detector 53 detects the different situations of modified decoding of the decoded information, instead of the encoded information, as described in Figure 6. In addition, the invention underlies each and every one of the features or combination of novel features.

Claims (36)

CHAPTER CLAIMANT Having described the invention, it is considered as a novelty and, therefore, the content is claimed in the following CLAIMS:

1. A device for encoding a data bit stream of an original binary signal in a data bit stream of a channel bit signal, where the bit stream of the original signal is divided into n bit original words, which device comprising conversion means adapted to convert the original words into corresponding m-bit channel words, the conversion means are adapted to convert a block of p original words of n consecutive bits into a corresponding block of p consecutive m-word channel words , so that the conversion of each block of p original words of n consecutive bits, substantially preserves the parity, where n, m and p are integers, m > n > 1, p = 1, and where p may vary, characterized in that the conversion means are adapted to convert the 8-bit bit sequence "00010001" into the bit stream of the original binary signal in the 12-bit bit sequence "100010010010" of the channel binary signal.

2. A device for encoding a data bit stream of an original binary signal and a data bit stream of a channel bit signal, where the bit stream of the original signal is divided into original words of n bits, device which comprises conversion means adapted to convert the original words into corresponding m-bit channel words, the conversion means are adapted to convert a block of p original words of n consecutive bits into a corresponding block of p words of m-channel. consecutive bits, so that the conversion of each block of p original words of n consecutive bits substantially preserves the parity, where n, m and p are integers, m > n > 1, p = 1, and where p can vary, characterized in that the conversion means are adapted to convert the 8 bit bit sequence "10010001" into the bit stream of, the original binary signal into the bit sequence of 12. bits "000010010010" of the channel binary signal.

The device according to claim 2, characterized in that the conversion means are adapted to convert the 8-bit bit sequence "10010001" into the bit stream of the original binary signal in the 12-bit bit sequence ". 000010010010"of the channel binary signal, in case the last bit of the channel signal generated up to this bit sequence is a" 1"bit.

The device according to claim 3, characterized in that the conversion means are adapted to convert the 8-bit bit sequence "10010001" into the bit stream of the original binary signal in the 12 bit bit sequence ". 100010010010"of the channel binary signal, in case the last bit of the channel signal generated up to this bit sequence is a" 0"bit.

5. A device for encoding a data bit stream of an original binary signal in a data bit stream of a channel bit signal, where the bit stream of the original signal is divided into original words of n bits, device which comprises conversion means adapted to convert the original words into corresponding m-bit channel words, the conversion means are adapted to convert a block of p original words of n consecutive bits into a corresponding block of p words of m-channel. consecutive bits, so that the conversion of each block of p original words of n consecutive bits substantially preserves the parity, where n, m and p are integers, m > n > 1, p > 1, and where p may vary, characterized in that the conversion means are adapted to convert the 8-bit bit sequence "11100000" into the bit stream of the original binary signal in the 12-bit bit sequence "000001010010" of the channel binary signal, at. case that the last 3 bits of the channel signal generated up to this bit sequence is "010".

6. A device for encoding a data bit stream of an original binary signal in a data bit stream of a channel bit signal, where the bit stream of the original signal is divided into original words of n bits, device which comprises conversion means adapted to convert the original words into corresponding m-bit channel words, the conversion means are adapted to convert a block of p original words of n consecutive bits into a corresponding block of p words of m-channel. consecutive bits, so that the conversion of each block of p original words of n consecutive bits substantially preserves the parity, where n, m and p are integers, m >; n > 1, p = 1, and where p may vary, characterized in that the conversion means are adapted to convert the 8-bit bit sequence "11100010" into the bit stream of the original binary signal in the 12-bit bit sequence "100001010010" of the channel binary signal, in case the last 3 bits of the channel signal generated up to this bit sequence is "010".

7. A device for encoding a data bit stream of an original binary signal and a data bit stream of a channel bit signal, where the bit stream of the original signal is divided into original words of n bits, device which comprises conversion means adapted to convert the original words into corresponding m-bit channel words, the conversion means are adapted to convert a block of p original words of n consecutive bits into a corresponding block of p words of m-channel. consecutive bits, so that the conversion of each block of p original words of n consecutive bits substantially preserves the parity, where n, m and p are integers, m > n > 1, p = 1, and where p can vary, characterized in that the conversion means are adapted to convert the 8-bit bit stream "11100001" into the bit stream of the original binary signal in the 12-bit bit sequence "001010010010" of the channel binary signal, in case the last 3 bits of the channel signal generated up to this bit sequence is "010".

8. A device for encoding a data bit stream of an original binary signal and a data bit stream of a channel bit signal, where the bit stream of the original signal is divided into original words of n bits, device which comprises conversion means adapted to convert the original words into corresponding m-bit channel words, the conversion means are adapted to convert a block of p original words of n consecutive bits into a corresponding block of p words of m-channel. consecutive bits, so that the conversion of each block of p original words of n consecutive bits substantially preserves the parity, where n, m and p are integers, m > n > 1, p = 1, and where p may vary, characterized in that the conversion means are adapted to convert the 8-bit bit sequence "11100011" into the bit stream of the original binary signal in the 12-bit bit sequence "101010010010" of the channel binary signal, in case the last 3 bits of the channel signal generated up to this bit sequence is "010".

The device according to any of the preceding claims, characterized in that m = n + l.

10. The device according to claim 9, characterized in that n = 2.

The device according to claim 10, characterized in that the device is adapted to convert unique original words into corresponding single channel words, according to the following table

12. The de according to claim 10 or 11, wherein the conversion means are adapted to convert original 2-bit words into corresponding 3-bit channel words, to obtain a channel signal in the form of a sequence (d, k) , where d = l, the de further comprises means for detecting the position of the bit stream of the original signal, where the encoding of unique 2-bit original words into corresponding single channel words, will lead to a violation of the restriction d in the limits of the channel word to supply a control signal in response to detection, characterized in that, in the absence of the control signal, the conversion means are adapted to convert single 2-bit original words into words of channel of corresponding single 3 bits, so that the conversion of each original 2-bit word preserves parity.

The de according to claim 12, wherein, in the presence of the control signal, which occurs during the conversion of two consecutive original words, the conversion means is adapted to convert a block of two consecutive 2-bit original words. in a block of two corresponding 3-bit channel words, so that one of the two original words in the original word block is converted to a 3-bit channel word, which is not identical to one of the four words of channel C ia CW4, to preserve the constraint d = l, characterized in that, in the presence of the control signal, the conversion means are further adapted to convert the block of two subsequent 2-bit original words into a corresponding block of two subsequent 3-bit channel words, so that the conversion of such a block of two subsequent 2-bit original words, preserves parity.

The de according to claim 13, characterized in that the conversion means are adapted to convert blocks of two consecutive 2-bit original words into blocks of two consecutive 3-bit channel words, according to the coding given in the following table:

15. The de according to claim 13 or 14, wherein k has a value greater than 5, the de is further provided with means for detecting the position in the bit stream of the original signal, where the coding of original words of 2 unique bits in single 3-bit channel words would lead to a violation of the restriction of k and to supply a second control signal in response to such detection, characterized in that, in the presence of the second control signal, which occurs during the conversion of three consecutive 2-bit original words, the conversion means are adapted to convert a block of three consecutive 2-bit original words into a block of three corresponding consecutive 2-bit channel words, so that the conversion of such block of three original 2-bit words preserves parity, the conversion means are also adapted to convert two of the three words s originals in a block in corresponding 3-bit channel words not identical to the four channel words C i to CW4, to preserve the restriction of k.

The de according to claim 15, characterized in that the conversion means are adapted to convert blocks of three consecutive original 2-bit words into blocks of three consecutive 3-bit channel words, in accordance with the coding given in FIG. next table: block of 3 original words block of 3 words of channel 11 11 11 000 010 010 11 11 10 0001 010 010 01 11 10 101 010 010 01 11 11 100 010 010

17. The de according to any of the preceding claims, characterized in that the de also comprises, means for detecting 8-bit bit sequences "00010001" and "10010001" in the bit stream of the original signal and means for detecting the value of the last bit of the generated channel signal from the original binary signal up to the sequence of 8 bit bits, the conversion means are adapted to convert the 8 bit bit sequences into the 12 bit bits of the channel signal, according to the coding given in the following table, depending on the value of the last bit of the Chanel: 8 bits bit sequence in the signal 12 bits original bit sequence in the channel signal 00 01 00 01 100 010 010 010 10 01 00 01 (last channel bit = "0") 100 000 010 010 10 01 00 01 (last channel bit = "1") 000 010 010 010 to limit a repeated minimum differential coordinate in the channel signal.

18. The device according to any of the preceding claims, characterized in that the device further comprises means for detecting a sequence of bits of 8 bits in the bit stream of the original binary signal and means for detecting the value of the latter. 3 bits of the channel signal generated from the original binary signal up to the original 8-bit bit sequence at "010", the conversion means are adapted to convert the 8-bit bit sequences given in the following table, in 12-bit bit sequences in the channel signal after detection of the 3-bit sequence "010" in the channel signal, according to the coding given in the following table:

19. The device according to claim 18, characterized in that the conversion means are adapted to convert the 8-bit sequences according to the table, to limit the restriction of each site.

20. A recording device for recording a channel signal on a track on a record carrier, the recording device is characterized in that it comprises the encoding device according to any of the preceding claims and in that it comprises writing means for writing the signal channel on the track of the record carrier.

The recording device according to claim 20, characterized in that the writing means comprises precoder means for performing a precoding step on the channel signal before registering in the track on the record carrier.

22. The record carrier, characterized in that it is obtained with the recording device according to claim 20 or 21.

23. The record carrier according to claim 22, characterized in that the record carrier is an optical record carrier. .

24. A device for decoding a data bit stream of a channel binary signal in a data bit stream of an original bit signal, where the bit stream of the channel signal is divided into words of m bit channels , device which comprises deconversion means adapted to deconvert m-bit channel words in original words of corresponding n bits, the deconversion means are adapted to deconvert a block of p n-bit consecutive channel words in a block of original words of corresponding n consecutive bits, so that the conversion of each block of p channel words of m consecutive bits preserves the parity, where n, m and p are integers, m > n = 1, p > 1, and where p may vary, characterized in that the conversion means are adapted to convert at least one of the 12 bit bit sequences in the following table, which appears in the bit stream of the channel bit signal in the sequence of 8-bit bits corresponding to the original binary signal, according to the table:

25. The device according to claim 24, characterized in that the device further comprises means for detecting the 12-bit bit sequences as given in the table.

26. A method for encoding a data bitstream of an original binary signal into a data bit stream of a channel bit signal, where the bitstream of the original signal is divided into n bit original words, the The method comprises the step of converting the original words into corresponding m-bit channel words, so that with the conversion of a block of p original words of n consecutive bits into a corresponding block of p channel words of m consecutive bits, the conversion of each block of p original words of n consecutive bits substantially preserves parity, where n, m and p are integers, m >; n > 1, p > 1, and where p may vary, characterized in that the conversion step comprises the sub-step of converting the 8-bit bit sequence "00010001" into the bit stream of the original binary signal in the 12-bit bit sequence "100010010010" of the channel binary signal.

27. A method for encoding a data bit stream of an original binary signal into a data bit stream of a channel bit signal, where the bit stream of the original signal is divided into n bit original words, the The method comprises the step of converting the original words into corresponding m-bit channel words, so that with the conversion of a block of p original words of n consecutive bits into a corresponding block of p channel words of m consecutive bits, the conversion of each block of p original words of n consecutive bits substantially preserves parity, where n, m and p are integers, m > n > 1, p > 1, and where p may vary, characterized in that the conversion step comprises the sub-step of converting the 8-bit bit sequence "10010001" into the bit stream of the original binary signal in the 12-bit bit sequence "000010010010" of the channel binary signal.

The method according to claim 27, characterized in that the sub-step of converting the 8-bit bit sequence "10010001" into the bit stream of the original binary signal in the 12-bit bit sequence "000010010010" of the channel binary signal is carried out in the case where the last bit of the signal generated up to this bit sequence is a "1" bit.

The method according to claim 28, characterized in that the sub-step of converting the 8-bit bit sequence "10010001" into the bit stream of the original binary signal in the 12-bit bit sequence "000010010010" of the channel binary signal, is carried out in the case where the last bit of the signal generated nasta this sequence of bits is a bit "0".

30. A method for encoding a data bitstream of an original binary signal in a data bit stream of a channel bit signal, where the bit stream of the original signal is divided into n bit original words, the The method comprises the step of converting the original words into corresponding m-bit channel words, so that the conversion of a block of p original words of n consecutive bits into a corresponding block of p channel words of m consecutive bits, the conversion of each block of p original words of n consecutive bits substantially preserves the parity, where n, m and p are integers, m > n > 1, p > 1, and where p may vary, characterized in that the conversion step comprises the sub-step of converting the 8-bit bit sequence "11100000" into the bit stream of the original binary signal in the 12-bit bit sequence "000001010010" of the channel binary signal, in case the last three bits of the channel signal generated up to this bit sequence are "010".

31. A method for encoding a data bit stream of an original binary signal into a data bit stream of a channel bit signal, where the bit stream of the original signal is divided into n bit original words, the The method comprises the step of converting the original words into corresponding m-bit channel words, so that the conversion of a block of p original words of n consecutive bits into a corresponding block of p channel words of m consecutive bits, the conversion of each block of p original words of n consecutive bits substantially preserves the parity, where n, m and p are integers, m > n > 1, p > 1, and where p may vary, characterized in that the conversion step comprises the sub-step of converting the 8-bit bit sequence "11100010" into the bit stream of the original binary signal in the 12-bit bit sequence "100001010010" of the channel binary signal, in case the last three bits of the channel signal generated up to this bit sequence are "010".

32. A method for encoding a data bit stream of an original binary signal into a data bit stream of a channel bit signal, where the bit stream of the original signal is divided into n bit original words, the The method comprises the step of converting the original words into corresponding m-bit channel words, so that the conversion of a block of p original words of n consecutive bits into a corresponding block of p channel words of m consecutive bits, the conversion of each block of p original words of n consecutive bits substantially preserves the parity, where n, m and p are integers, m >; n > 1, p > 1, and where p may vary, characterized in that the conversion step comprises the sub-step of converting the 8-bit bit sequence "11100001" into the bit stream of the original binary signal in the 12-bit bit sequence "001010010010" of the channel binary signal, in case the last three bits of the channel signal generated up to this bit sequence are "010".

33. A method for encoding a data bit stream of an original binary signal into a data bit stream of a channel bit signal, where the bit stream of the original signal is divided into n bit original words, the The method comprises the step of converting the original words into corresponding m-bit channel words, so that the conversion of a block of p original words of n consecutive bits into a corresponding block of p channel words of m consecutive bits, the conversion of each block of p original words of n consecutive bits substantially preserves the parity, where n, m and p are integers, m > n > 1, p > 1, and where p may vary, characterized in that the conversion step comprises the sub-step of converting the 8-bit bit sequence "11100011" into the bit stream of the original binary signal in the 12-bit bit sequence "101010010010" of the channel binary signal, in case the last three bits of the channel signal generated up to this bit sequence are "010".

34. The method according to any of claims 26 to 33, characterized in that it further comprises the step of registering the channel signal in a track in a record carrier.

35. The method according to claim 34, characterized in that the registration carrier in an optical record carrier.

36. The method according to claim 34 or 35, characterized in that it comprises the method further comprises a pre-registration step in the channel signal, before registration of the channel signal in a record carrier.