DK194191D0 - TOLERANT SYSTEM WITH A MULTI-USER TREATMENT UNIT AND PROCEDURE FOR MANAGING THIS - Google Patents
TOLERANT SYSTEM WITH A MULTI-USER TREATMENT UNIT AND PROCEDURE FOR MANAGING THISInfo
- Publication number
- DK194191D0 DK194191D0 DK911941A DK194191A DK194191D0 DK 194191 D0 DK194191 D0 DK 194191D0 DK 911941 A DK911941 A DK 911941A DK 194191 A DK194191 A DK 194191A DK 194191 D0 DK194191 D0 DK 194191D0
- Authority
- DK
- Denmark
- Prior art keywords
- managing
- procedure
- treatment unit
- tolerant system
- user treatment
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Computing Systems (AREA)
- Quality & Reliability (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900019648A KR920010472A (en) | 1990-11-30 | 1990-11-30 | Tolerant system with multi skin |
Publications (2)
Publication Number | Publication Date |
---|---|
DK194191D0 true DK194191D0 (en) | 1991-11-29 |
DK194191A DK194191A (en) | 1992-05-31 |
Family
ID=19306881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DK194191A DK194191A (en) | 1990-11-30 | 1991-11-29 | TOLERANT SYSTEM WITH A MULTI-USER TREATMENT UNIT AND PROCEDURE FOR MANAGING THIS |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPH04268662A (en) |
KR (1) | KR920010472A (en) |
DK (1) | DK194191A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998041927A1 (en) * | 1997-03-19 | 1998-09-24 | Hitachi, Ltd. | Parallel computer |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0821025B2 (en) * | 1986-09-29 | 1996-03-04 | 株式会社東芝 | Multiprocessor system and method of initializing the system |
JPH0766368B2 (en) * | 1986-10-21 | 1995-07-19 | 日新電機株式会社 | Boot processor determination method |
JPS63131258A (en) * | 1986-11-20 | 1988-06-03 | Fuji Electric Co Ltd | Multiprocessor system ipl system |
JP2754211B2 (en) * | 1988-06-20 | 1998-05-20 | 富士通株式会社 | Multiprocessor control method |
-
1990
- 1990-11-30 KR KR1019900019648A patent/KR920010472A/en not_active Application Discontinuation
-
1991
- 1991-11-28 JP JP3314480A patent/JPH04268662A/en active Pending
- 1991-11-29 DK DK194191A patent/DK194191A/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
JPH04268662A (en) | 1992-09-24 |
DK194191A (en) | 1992-05-31 |
KR920010472A (en) | 1992-06-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
AHB | Application shelved due to non-payment |