DK169883B1 - Method for securing secret code data stored in a data store and circuit arrangement for carrying out the method - Google Patents

Abstract

The invention relates to a method and circuitry for securing code data stored in a code data memory (1a) prior to analysis, in which the signals at the code data memory outputs provide an indication of the contents of the code data memory. According to the invention, a blocking circuit (4), controlled by a blocking logic circuit (9), is provided at the code data memory outputs, which it blocks as soon as entered control data fails to match the code data. <IMAGE>

Description

in DK 169883 B1

The invention relates to a method for securing secret code data stored in a data store against an analysis in which analysis from the signals on the storage outputs can be joined to the storage content, according to the preamble of claim 1, and an integrated circuit with a data storage for carrying out the method.

A similar method as well as a corresponding integrated circuit for practicing the method is known in principle from EP-OS 0 207 320.

Such an integrated circuit, for example, constitutes an essential element of a so-called chip card which can be used in security and access systems, in billing or registration systems and in debit and credit systems. Connection to the integrated circuit and data storage takes place via external contacts on the card surface in a card reader.

In many use cases, in a storage area referred to as code data storage, the storage card data stored as secret code data is stored on the individual cards for identification or authorization of the card user or card. System security depends on how well this code data is protected against an abusive analysis. Therefore, very high demands are placed on the security of fraud for the cards and reading devices. Due to security measures similar to the current state of experience, a direct attempt to analyze the contents of the code repository, which usually consists of an EE-PROM repository and, in particular, a subarea of 30 said repository in the card, is unlikely to succeed.

However, it is possible to retract to these storage data based on the indirect influence of the code data on the code data outputs, ie. on the connected peripheral logic.

35 From FR-PS 23 11 360 it is known, in connection with the provision of an access right, to allow the operator 2 a certain number of code entries, and to store all unauthorized attempts in a stored storage until the entire storage area is filled up . Then the unit to be protected is put out of operation.

EP-OS 0 127 809 discloses a circuit arrangement in which data comparisons are performed between stored code data and externally entered control data, and in which the address area of the code data recording storage area is subdivided into a plurality of sub-sets of sample logic with each several addresses and where the address lines determining the subsets are associated with an address control unit from which a release signal can be extracted when at least one address has been selected from each subset during the comparison process 15.

EP-OS 0 128 362 discloses a storage arrangement with storage and security logic, where after comparing an entered control word with a stored password, at least one storage cell is written in an operational data area whose address depends on the comparison result. Hereby, access attempts with erroneous control data entries are recorded, while only deleting the operation data after the access release after successful completion of the release procedure. Thus, with the limited size of the operational data store, the number of permissible incorrect entries is limited.

However, in the circuit arrangements described above, the code data stored in the data storage is to a great extent transferred protected to the comparator in which they are compared with the entered control data.

Especially when there is a comparison means for comparing code data with user-entered control data, and this code data is transmitted via a data transfer means such as e.g. a data line, i.e.

3 DK 169883 B1 a data bus for this comparator, e.g. a comparator, code data on this data transfer means can be read. In particular, a data transfer means used may contain the column lines "of the data store, as well as the column decoder and the data bus.

An integrated circuit described in EP-OS 0 207 320 contains a non-volatile code data store, preferably of the EE-PROM type, which stores the secret code. This code data store is connected via a data bus to an input to a comparison circuit whose second input is intended to be affected by the entered control data. The output from the code store, ie. The data bus is thus equipped with a controllable storage circuit, via a logic circuit, so that the outputs of the storage cells, usually the column lines from the storage field, are normally blocked from the peripheral logic. The lockout is only lifted for a short period of time, as the secret data is actually needed for the data comparison in the peripheral logic. The possibility of conducting an analysis of code data is thereby limited to a short period of time, but not absolutely excluded. Specifically, the output data of the code data store to be protected by activated blocking, independent of the stored information, is coupled to a fixed potential.

To further limit the number of possible assay attempts, the beginning of a code data entry process with a write process is initiated in a count store which is addressed along with the corresponding password. This 30 count store only becomes 0 when code data corresponding to control data is entered incorrectly and a control process is completed. In doing so, the size of the counter store determines the number of failed access attempts.

A further identification layer characterizes the cells in the data store that make up the code data store, so that the access bar is limited to this area.

4 DK 169883 B1

A circuit described in this publication also restricts the readout of code data from the code store to the data bus in time. An analysis of all code data is thereby only complicated, not 5 prevented.

The object of the invention is to provide a method of absolutely securing secret code data stored in a data store against an analysis.

This object is solved by a method according to the characterizing part of claim 1, as well as by an integrated circuit according to the characterizing part of claim 6.

Secret code data stored in a data store which is compared with encoded control data by means of a comparator and which must therefore be transmitted from the data storage output to the comparator via a data transfer means can be analyzed while on the data transfer means. Such an analysis can be prevented by not providing all secret code data, 20 after the initiation of a data comparison, to the data transferring means, but in accordance with the invention, a blocking circuit is activated at a first encoding of control data which does not match the code data, preventing a further readout of code data 25 to the data transfer means.

It turns out to be particularly advantageous if a further readout of code data from the repository to the data transfer means is also prevented after completing a correct data comparison of all the code data which constitutes a complete code.

Preferably, the readout of code data from the memory to the data transfer means should be possible only after recording a comparison process, for example by writing a counter bit. If the recording is done by writing a counter bit, it can further be ensured, by means of a logic circuit preceded, that the counter bit described previously was previously undescribed. The said record, in particular by means of writing a counter bit, may be intended both for permanent registration of all access attempts made as well as for registering erroneous access attempts. If the registration is to be done using an error counter, it must especially be ensured, by means of a logic circuit, that the error counter can only be O-positioned after a correct data comparison.

10 The security of the method can be further enhanced by the fact that even with byte-stored code data these are transmitted serially to the data bus and compared bit by bit with control data. As soon as the first control bit does not match the corresponding code bit, the readout of the next code bit to the data transfer means is prevented.

If there is an error counter for counting the erroneous control data, where each erroneous control data entry according to the invention requires a fresh start of the data comparison, it is advantageous for security reasons if the number of comparison operations required for a comparison cycle is so as large as possible in relation to the maximum permissible number of erroneous control data inputs. At least 25, the number of comparison operations required for a comparison cycle must be greater than the maximum permissible number of erroneous control data inputs.

The figure shows in the form of a block diagram a preferred embodiment of an integrated circuit for practicing a safety method according to the invention in accordance with the invention.

Here, block 1 represents a data storage unit which at least comprises a code data store 1a and in particular may comprise an identification storage. Block 2 comprises a release counter which can be used especially as a 6 counter 169883 B1 error counter, which is activated at the start of a comparison cycle, preferably by writing a free counter bit. Block 3 comprises a control loop circuit which checks whether a counter bit in the release counter 2 was previously unwritten and then written, and in this case transmits a corresponding release signal to a lock logic circuit 9 of the invention. Block 4 comprises are blocking circuits intended to prevent the readout of code data from the code data store to a data transfer means 6, and preferably in active mode, the data outputs of the code data store or the associated data lines attach to a fixed potential. Block 5 comprises a comparison means that compares the control data loaded to the input 7 with the code data located on the data transfer means 6 and which outputs the data corresponding to the comparison result to an output 8. Embodiments of the blocks 1, 1a, 2, 3, 4 and 5 and the data transfer means 6, 20 as well as their modes of operation are described in EP-OS 0 207 320.

In a monolithic integrable electronic circuit, in which a code data store 1a, via a blocking circuit 4 and a data transfer means 6, is connected to an input to a comparator 5, and wherein this comparator 5 has an additional input 7, as well as an output. 8 to provide the comparison result, the readout of additional code data to the data transfer means 630 is prevented by a blocking logic circuit 9 of the invention, as a result of the first negative comparison result on the output 8, activating the blocking circuit 4.

Preferably, the readout of code data from the code data store 1a to the data transferring means 6 by such a circuit, in particular via the interlock logic circuit * 7, is enabled by switching off the interlock circuit 4 after the writing of an already free release counter bit.

It turns out to be particularly advantageous if the blocking 5 circuit 9 comprises a switch-off logic circuit 10 which, when comparing correct control data with code data in a complete code, causes the activation of the lock circuit 4. Since the signal at the output 8a of this switch-off logic circuit 10 is dependent on a fully correct control data input, it can also be used for the 0 position of an error counter, and can be used together with the signal at the output 8 of the comparator 5 as a release signal for the entire security circuit. The switch-off logic circuit 10 15 preferably comprises a counter which, upon activation of the blocking circuit 4 or the release counter 20, is set and which, with each correct data comparison in the comparator 5, counts one further and which, after comparing the last code bit, activates the blocking circuit.

In the following, the operation of a circuit according to the invention is described with reference to the preferred embodiment shown in the figure.

The control logic circuit 3 monitors whether a previously undescribed counter bit in the release counter 2 is described. An output of this control logic circuit 3 is connected to the set input of an RS flip-flop 12 contained in the interlock logic circuit 9.

After correctly inscribing a counter bit into the release counter 2, this flip-flop 12 is set.

Flip-flop 12's inverting output QN is connected to the control input of the latch 4, and deactivates the latch when the flip-flop is set. Specifically, for each data line, the lock circuit 4 includes a contact T, which adds this data line to a fixed potential by activated lock circuit 4. A second embodiment according to the invention of the lock circuit 4 is realized by the column decoder for code. The data store 1a in the activated state for the blocking circuit 4 is made conductive for all columns. Thereby, all the outputs of the code data storage 1a are parallel, and a connection between the information in the code data to be protected and the information on the data transfer means 6 is not possible. If the blocking circuit 4 is deactivated, the code data from the code data 1a bit or byte 10 can be transmitted via the data transfer means 6 to a first input of the comparator 5. The comparator 5, which may in particular consist of a comparator of a known kind, compares it at its first input. standing code data with the corresponding control data entered on its second input 7, and, preferably in serial form, gives the comparison result on output 8.

If code data and control data are preferably where bit comparisons are preferred, then the 20 of the output 8 controlled by the comparator 5 controlled interlock logic 9 will only cause a block of the blocking circuit 4 when the corresponding data comparison is the last data comparison in a comparison cycle, ie. when the overall code in a last correct data comparison has been compared with correct control data. It is achieved, for example, that for each comparison result in a correct data comparison one counter circuit 10 is counted one unit further, that this counter circuit 10 is set from the start of a comparison cycle 0, can be obtained at a 0 position of the counter circuit 10 with the activating control signal of the blocking circuit 4, and the counter circuit 10, upon obtaining the counter state corresponding to the total number of comparison operations 5 of the code, gives a signal at its output 8a which causes activation of the blocking circuit 4. According to the invention, for example, counting circuit 10 may also be used, e.g. located in the integrated circuit address counter. The multifunction use of such a counter leads to a chip area saving.

This signal at output 8a of the counter circuit 10 may also be calculated as an O-position signal for a failure counter driven release counter 2, as well as a release signal for the code securing circuit. This release signal may further release a protected function and may also, for example, enable the release of a CPU contained in the microprocessor, in particular a release of the program decoder or data decoder.

If the code data differs from the corresponding control data, the first comparison operation in the comparator 5 with different data already causes an activation of the blocking circuit 4.

The activation of the blocking circuit 4 via the output signal of the switching logic circuit 10, as well as via the output signal of the comparator 5 20 in the presence of a negative data comparison, can be realized in particular by the output 8 of the comparator 5 being connected to the input of a logic circuit 11 8a from the disable logic circuit 10 is connected to the second input of this logic circuit 11 and that the output of this logic circuit 11 is intended to affect the reset input of the flip-flop 12 contained in the latch circuit 9.

If the blocking circuit 4 is to be activated when there is a high signal at the output 8 of the comparator 5, as well as at the output 8a of the disabling logic circuit 10, e.g. an OR gate function for the logic circuit li.

Claims (10)

A method for preventing the unreadable reading of a secret code consisting of a plurality of code data and stored in a code data store (1a), wherein said code data store (1a) is exclusively via a blocking circuit (4) by means of a data transfer means (6) communicates with a first input to a comparator (5), the second input of which receives control data, and the output of the comparator (5) over a latch logic circuit (9) controls the latch circuit 10 (4), characterized by the following steps: a ) reading a first code date from the number of code data of the secret code from the code store (1a) and printing a first check date on the second input to the comparator; 15 b) comparing the code date with the check date in the comparator (5); the code date read from the code data is matched to the control date, an additional code date is read from the code data (1a) and a further 20 control atum is applied to the comparator (5), to which step b) is repeated; d) when the code date read from the code store (1a) does not match the control date, further reading of code data is prevented by a signal 25 from the comparator (5) to the bar (4). ) via the blocking logic circuit (9). Method according to claim 1, characterized in that a further reading of code data from the code data store to the data transfer means (6) is prevented after the completion of a correct data comparison. * Method according to claim 1 or 2, characterized in that reading code data from the data storage (1a) to the data transfer means (6) is only possible after writing a counter bit. Method according to one of the preceding claims, characterized in that the code data is transmitted serially on a data bus (6) and compared bit by bit with the control data. Method according to one of the preceding claims, characterized in that an error counter (2) exists for counting the incorrect control data encodings, that the number of erroneous control data encodings in a known manner is limited by this error counter (2). ), and that the number of comparison operations required for a comparison cycle is greater than the maximum allowable number of encodings of faulty control data. An integrated circuit including a comparison means (5) having a first input, a second input and an output, a code data store (1a) with outputs, and the outputs of the code data store (1a) over a blocking circuit (4) by means of a data transfer means (6) communicates with the first input of the comparator (5), and the second input of the comparator (5) can be fed with control data, characterized in that the output of the comparator 25 (5) is connected to the blocking circuit (4). ) via a blocking logic circuit in such a way that upon first loading control data that does not match the code data passed from the code data store (1a) to the comparison means, further reading of 30 code data to the data transfer means (6) is prevented. Circuit according to claim 6, characterized in that the blocking circuit (4) has a contact transistor (T) on each storage output, the controlled stretch of the transistor connecting the storage output to be protected with a predetermined potential. Circuit according to claim 6, characterized in that the blocking circuit (4) in active state connects all code data outputs with each other. 12 DK 169883 B1 9. A circuit according to claim 6, 7 or 8, characterized in that a flip-flop (12) is provided for controlling the blocking circuit (4). > Circuit according to claims 6, 7, 8 or 9, 5, characterized in that a switch-off logic circuit (10) exists for recording the comparison processes with corresponding control data and code data and for blocking the blocking circuit (4) after the end of a comparison cycle. '· * «