DK0947050T3 - Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronisering i et digitalt transmissionssystem - Google Patents

Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronisering i et digitalt transmissionssystem

Info

Publication number
DK0947050T3
DK0947050T3 DK97950004T DK97950004T DK0947050T3 DK 0947050 T3 DK0947050 T3 DK 0947050T3 DK 97950004 T DK97950004 T DK 97950004T DK 97950004 T DK97950004 T DK 97950004T DK 0947050 T3 DK0947050 T3 DK 0947050T3
Authority
DK
Denmark
Prior art keywords
desynchronization
controlling
well
transmission system
digital
Prior art date
Application number
DK97950004T
Other languages
English (en)
Inventor
Per H Thomsen
Original Assignee
Tellabs Denmark As
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tellabs Denmark As filed Critical Tellabs Denmark As
Application granted granted Critical
Publication of DK0947050T3 publication Critical patent/DK0947050T3/da

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DK97950004T 1996-12-23 1997-12-22 Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronisering i et digitalt transmissionssystem DK0947050T3 (da)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DK150796A DK150796A (da) 1996-12-23 1996-12-23 Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronise
PCT/DK1997/000594 WO1998028849A1 (en) 1996-12-23 1997-12-22 A digital phase-locked loop and a method of controlling it, as well as a method and receiver circuit for desynchronization in a digital transmission system

Publications (1)

Publication Number Publication Date
DK0947050T3 true DK0947050T3 (da) 2003-08-18

Family

ID=8105562

Family Applications (2)

Application Number Title Priority Date Filing Date
DK150796A DK150796A (da) 1996-12-23 1996-12-23 Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronise
DK97950004T DK0947050T3 (da) 1996-12-23 1997-12-22 Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronisering i et digitalt transmissionssystem

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DK150796A DK150796A (da) 1996-12-23 1996-12-23 Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronise

Country Status (5)

Country Link
EP (1) EP0947050B1 (da)
AU (1) AU5311598A (da)
DE (1) DE69721563T2 (da)
DK (2) DK150796A (da)
WO (1) WO1998028849A1 (da)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3296297B2 (ja) * 1998-07-23 2002-06-24 ヤマハ株式会社 同期制御方式
DE19941445A1 (de) * 1999-08-30 2001-03-01 Thomson Brandt Gmbh Phasendetektor für eine Phasenregelschleife
US7262645B2 (en) 2002-12-19 2007-08-28 Broadcom Corporation System and method for adjusting the phase of a frequency-locked clock

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4947407A (en) * 1989-08-08 1990-08-07 Siemens-Pacesetter, Inc. Sample-and-hold digital phase-locked loop for ask signals
DE69227820T2 (de) * 1991-10-10 1999-05-12 Nec Corp., Tokio/Tokyo Sonet DS-N-Desynchronisiereinrichtung
US5479457A (en) * 1993-08-27 1995-12-26 Vlsi Technology Inc. Method and apparatus for attenuating jitter in a digital transmission line
US5563891A (en) * 1995-09-05 1996-10-08 Industrial Technology Research Institute Waiting time jitter reduction by synchronizer stuffing threshold modulation

Also Published As

Publication number Publication date
EP0947050B1 (en) 2003-05-02
AU5311598A (en) 1998-07-17
DE69721563D1 (de) 2003-06-05
DE69721563T2 (de) 2004-04-08
DK150796A (da) 1998-06-24
EP0947050A1 (en) 1999-10-06
WO1998028849A1 (en) 1998-07-02

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