DEI0008413MA - - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

Registration date: March 19, 1954. Advertised on May 3, 1956

GERMAN PATENT OFFICE

The invention relates to a correction device for memories of message contents iii telecommunication systems, in particular telephone systems preferably using drums driven at constant speed, which contain one or more magnetizable tracks as well as recording and playback heads, whereby the messages are stored in binary form in individual element sections of the webs will.

The use of magnetic drums to store message content can be used in Disruptions in the power supply lead to incorrect storage. Since now with magnetic Drums handle the storage processes so quickly that for a storage job the If the magnetic drum is ready for recording several times, this will prevent incorrect storage according to the invention proposed an arrangement in such a way that the individual tracks additional recording heads, so-called correction heads, are assigned which, after by the. Control device and the pick-up heads an incorrect storage was determined, a re-storage make: This is possible because the individual successive messages

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Contents are alternately stored by pulses of different currents. The re-storage becomes effective according to the invention in the cases when, for example, two consecutive Message content that feeds have been made in the same current direction. In this In this case, the control device is initiated, as already mentioned, via the additional recording head make the appropriate correction.

ίο The details of the invention are given below explained in more detail with the aid of the figures. Here shows

Fig. Ι a schematic overview of an arrangement for a storage device with a magnetic drum,

Fig. 2 shows one of the message channels as it is used for this device, in connection with a Number of electronic power gates each assigned to a channel,

Fig. 3 to 8 the other control devices through which the storage is achieved and through which the impulses are renewed,

9 through 11 are graphs showing the waveforms used in the circuit described to be used,

12 to 14 particular circuit details, 15 and 16 a magnetic network with static means,

17 shows a static network with ferroelectrics Switching elements.

In the embodiment, a magnetic drum or disk is used as an electric Storage device used. For example, it consists of one. Brass drum, which on its cylindrical surface has a magnetic coating. This coating has a number closely adjacent tracks or tracks, and each of these tracks is a memory and assigned to a pick-up head. The drum runs on a rotating shaft which runs at high speed is driven by an electric motor.

The message contents are in the form of successive magnetic impressions of each stored one of two identifying features. These identifying features are referred to in the familiar way with "o" and "1" or with "distance" and "marking". at The storage of digits is done on the binary system, although other encodings are also possible possible are.

Each lane or track is divided into a number of longitudinal sections. The details of this will be described later. The storage and pick-up heads are arranged separately from each other, so that two separate web sections form a storage section. If a pickup head If one section of a storage path taps off, the corresponding storage head is on the other Effective section of this web. Thus, the stored message content is tapped and stored in saved again in the corresponding section of the path.

In addition to the lanes on which news content is stored, there is a special lane provided, which stores each position of the storage elements. To this particular one Track is also provided a pick-up head, from which one pulse per message element is removed. The last-mentioned path is also called the time path and the associated pick-up head as Called time head. The latter device is used to each have a set of three closely spaced To produce pulses per message element. Another additional track has the Task of defining the position of the first message element on each memory section. This path is referred to as the marking path and the pick-up head assigned to it as Marking head. The latter gives a pulse cycle, which is the beginning of each memory section definitely. These two pulse cycles, namely the timing pulse cycle and the marking pulse cycle, are used to control all switching processes. The described device for storing messages is referred to in a well-known way as "memory renewer".

The simplest way of assigning the individual communication channels or lanes to the reminder, consists in assigning a certain path to each storage. However, since the Renewers only for receiving and then rebroadcasting message content is used and the latter only take a short period of time, must for the Allocation of the message content on the individual tracks made an appropriate division will. For this reason, the number of intended stores is less than the number of the channels. There are therefore provisions for the temporary allocation of storages to a Channel necessary if a renewal of the storage is desired.

The memories on a particular track form a group, which is a group of circuits is assigned, which is, for example, ten times greater than the number of storages. A single common connection and control circuit is provided, namely between the storage circuits and the railways. In a particular example, there can be a hundred storage circuits ten storages can be allocated. However, for the sake of simplicity it is in the The following description assumes that the memories of a lane are each of the ten channels be available.

In the timing diagrams of FIGS. 9, 10 and 11 is shown as a section of a path which forms a memory and forty-eight elements contains, is used for the assignment of a message channel to a storage and for the Storage and renewal of series of pulses during a series of runs of a storage under the tap head. The elements are labeled 1 through 48 and Figure 9 shows how these are grouped are. Some of these elements are individually and

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sometimes used in groups, depending on the purpose for which they are used. When a Group of successive element positions is used for the same purpose, so forms this group has a memory section. As already mentioned, every element is tapped and stored, either with or without modification in a specific position in a repeatable Cycle of time slots, which is determined by the rotation of the drum.

The time pulses, which are generated by the element track, are used to control the electronic gates and are denoted by the symbol T. Where an element forms part of the groups shown in FIG. 9, this letter is followed by a group of elements. The element identification follows the character T alone or in connection with a group identification. So has z. B. the gate G 16 in Fig. 4 to make the control TL 24, with which a time pulse in the group L and the element 24 are identified. ,

As already mentioned, the elements of the pulse cycle are also used in a known manner to define three cycles of closely spaced pulses, the pulses being staggered and each being one third of the duration of a pulse element. These closely spaced pulses are denoted ii, t2 and i3, and all of these pulses occur simultaneously within an element.

The above description has made it clear that the elements on a web lie close together and the memories are caused by overprinting an existing memory. If a storage is empty or free, its elements are positively excited, ie they have stored "1". The remaining elements of group R count the revolutions of the drum, which will be described in detail later.

For a better understanding it is again pointed out that each track of the drum has a number Has storage sections and each section consists of forty-eight elements. With the present Arrangement, two such memory sections form a memory, which with any the news channels can be connected. For the sake of simplicity it is assumed that that ten channels are served by storing one path. The control circuits are assigned to all memories of a path together.

A single section of a web will now be considered in particular. The first element of a section is used to mark the free or busy mark. The next group of elements is used to identify one of the channels to which the section is available. This element group contains the label storage. In the present case, the elements 2 to 11, which are designated by CC2 to CC τι , are intended to identify the channels 1 to 10.

The control circuit for the railroad has a register with enough stable layers to identify the various channels. Such a register consists essentially of an ordinary electronic counter, the only difference being that it can be stopped in every switching position by associated control means. It is controlled by impulses from the drum's timeline. These time pulses, which occur regardless of whether there is storage in the element concerned, are denoted by the letter T. The letters identify the element group to which they belong. Therefore, if no channel requires the servicing of a store, the pulses TCC2 through TCC Ii control the register over this pulse cycle. It then remains in the last switch position, namely TCCi I, until the pulse TCC 2 of the next section occurs on this path. At first glance it seems that this could lead to disturbances, but the type of storage which is carried out on the web sections is such that no disturbances occur.

It has already been established that a time slot TCC is assigned to each channel. Each channel can only store during its time slot TCC . During normal operation, ie during scanning by a register upon detection of a calling channel, are all the sections to "0", with the exception of sections 19 and 20 which are designated AE19 and L 20th The reasons for this are discussed in the following description.

It is assumed that channel 4 needs storage. The calling channel thus provides a switching state, which in the control circuit and thus in the register das Stopping the scanning process in a. Time slot which is assigned to channel 4, i. H. in the time slot TCC5. This causes the re-storage in the element 5, which becomes effective as a marking element. The register remains in the switch position for channel 4, while the portion of occupied storage passes the pickup and pickup head.

At the same moment that the scan of the register is stopped, the ringing state in the channel is released. This offers the security that the channel does not occupy multiple memories. Passing behind the heads takes place at switching point PN1 in FIG. 9.

It is necessary to ensure that the storage which has been carried out is not carried out by channels 1 to 3 will be detected on the next pass, d. H. through channels whose timing is ahead the channel for which the section was occupied and marked. For this reason becomes-der already mentioned auxiliary storage head used. He works in a time slot behind the time slots of all of them Channels. This auxiliary head stores a mark in the first element and identifies so that the whole element section is occupied.

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In the arrangement described, the auxiliary head becomes effective in the time slot X31. The choice of this time slot is arbitrary and is essentially a matter of mechanical design. At the end of the cycle (time slot PN 1), time slot T48 switches the entire control circuit to "o" so that it is available for other storage. As already mentioned, the possibility of malfunctions is prevented by the type of storage in the switch position PiVi. These memories indicate that the section is busy and identify the channel for which that section was occupied.
. At the beginning of the next pass PN 2 in FIG. 9, the first element is picked up and stored again as a marking element. Since there are two sections per lane, the second section begins after the drum has made half a revolution. As before, the register begins its cycle, but the TCC 5 marker is tapped and stopped in the fourth switch position, specifically for the channel which was reserved for storage. Since the register scans with each pass until it reaches the switch position which is marked as calling, the assignment is carried out by the calling channel. The mentioned marking is also saved. In this way, the control circuit picks up the stored message content with each pass and accordingly takes care of its switching operations. During the following runs, the markings in switch positions 1 and 5 will be continuous. tapped and saved again. However, these passes are counted in sections 15-19. In pass PiV 2, the marking is saved in switching position 14 and the distances are saved in switching positions 15 to 19. However, the switch position 20 has been saved again. The elements of the switch positions 21 to 47 are stored as distances, and a control mark is recorded in the switch position 48. The time pulse T 48 causes a control relay to respond in order to close the previous loop. At the switch position T14 of the PiV 2 throughput, the channel was marked as occupied by another relay. In the subsequent runs, namely until the first dialing pulse is received, these switching processes are repeated, ie the markings are picked up in switching positions i, 5, 14, 20 and 48 and stored again. These runs are counted in binary form at the switch positions 15 to 19, but this count has no effect. Since these miscounts have no influence whatsoever on other switching functions, they do not need to be switched off. The count is shown in Fig. 10 at PN 3 to PN 5. With each run, the count becomes effective by tapping all stored elements.

It is assumed that the first dialing digit pulses for the tap PiV 6 are received. During this cycle, the memories in the switching elements 14 to 19 are implemented at intervals. The distances are also stored in switch position 19 and switch positions 21 and 24, 25 to 30 and 31. The receipt of the first pulses causes a marking which is stored in the switch position 32, namely in the switch position 1 of the section D 1 of the occupied memory path. This means that the first pulses have been received. The switch positions 33 to 47 are newly saved as distances and 48 as markings.

The selection pulses are relatively long compared to the individual cycles, so that such a pulse lasts for several such cycles. The revolutions during which the first pulse occurs are counted in part R of the track section, specifically in switch positions 15 to 19. If the pulse has been received and an interruption pulse is too long, this is indicated by a marker which is stored in the switch position 19. When it is picked up, this then causes the circuit arrangement to be forcibly triggered, the track section being brought into its rest position. Thus, the time of an interruption is counted by counting the taps of a memory. If the interruption lasts so long that an error can be assumed, the storage made in switch position 19 is evaluated by the control circuit as an indicator for forced triggering.

In this case it is assumed that the pulse has a normal length, the counting of the rounds PN 7, PN 8 and PN 9 corresponds to a normal duration and it is determined on the first round PN 10 that the pulse has ended. This causes the storage of a marking in the switch position 14 and a distance in the switch positions 15 to 19. At PN 11, counting starts again at R and lasts until the second dialing pulse is received. This count limits the switching status for the channel.

The second selection pulse comes, as is assumed, in the pass PN 12 and is stored in the part D ι (switch position 32 to 35). This is done by adding 1 to the digit because in this case one is already stored in that part. The usual counting of the cycles for the duration of a dialing pulse takes place in the switch positions 15 to 19 during the passes PN 13 to PiV 15. This ends the dialing pulse and initiates the switching processes as previously described. , '

In the present example it is assumed that the first digit is a 2. Since the institution cannot know this, it checks. the fact that it detects the pauses between pulses. This is done by counting the number of passes between the pulses. The counting takes place in the section R (switching element 15 to 19) during the passes PN 16 to PiV 20. The pause between the digits is determined when a marking is in the switching position 17

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stores is. During the run during which these processes take place, markings become stored in the switch positions 20 and 21. The control circuit then assumes a switching state one from which the received digit can be transmitted further.

The stored digit is then newly stored in the section D ι as its complement, d. k, all binary elements are reversed. All digit current surges, which are then recorded, are then passed through the control circuit to section D 2 (switch position D 36 to D 39). After the count, which determines that there is a pause between the digits, the switch positions 15 and 18 are stored again with intervals, but the switch position 19 is held as a marker and remains until the next digit is received. These measures are taken so that no incorrect switching occurs.

When the first pulse of the second digit is received, the distances are saved in section R (switch positions 15 to 19). The receipt of the second digit is the same as the first, except that it is stored in section D 2. The third digit is included in Section D 3, etc.

The pulse is now transmitted over the loop, and as each pulse is sent, 1 is added to the digit in section D 1 so that when all elements of section D 1 are marked, the digit is completely transmitted. Each renewed pulse begins at the switch position T 48 of a cycle and lasts for four cycles. These runs are counted in a known manner, namely in section S, ie in switch positions 25 to 30. When a digit is transmitted, its storage in section L, ie in switch positions 20 to 24, is deleted.

The renewed pulse begins at the switch position T48 of the run-through, namely at path PiV 21. Here, the forward loop is interrupted and the element 48 is newly saved as the distance. This is a sign that an impulse has been transmitted. The next digit can be received during the following passes. Your pulses are stored in section D 2 (switch positions 36 to 39), with section R being counted, as is already known. During the first run of the renewed pulse, a marking is stored at the switch position 25, the switch positions 26 to 30 being recorded as distances.

In order to save the pulse transmission, a marking is held in the switch position 31, which is designated with SCM . This marking continues as long as the pulse is transmitted and its presence is used to ensure that only one is added to section D 4 for each transmitted pulse. This addition of 1 takes place in the usual way, ie by reversing all elements from section D 1 up to and including the first distance. During the following passes, the pulse count continues in section 6 ", with no change other than storage in section D 2 for the second digit. This count is shown in rounds PN 21 to PiV 24 in FIG. 11, in which none Storage for the second digit is shown.

At the end of the transmitted pulse, the switch position 27 is stored as a distance, and depending on this, the element 31 is also stored as a distance, the element 48 as a marker. The pulse is ended in time segment T48. During the next pass PN 25, the storage in section S is deleted, ie re-saved as intervals.

The second pulse is retransmitted in the same way, with a 1 being added to section D ι as before. These measures take place during pass PN 26 to PiV 29. During pass PN 28, the auxiliary memory already mentioned becomes effective to hold a marker in switch position 12 and thereby indicate that the transmitted pulse is the last. This is true when the circuit determines that all of the markings in section D 1 are in place. During the next run, the element 13 also receives a marking, which is also stored during the run PN 3ο. The section ^ indicates that the pulse duration has shifted and this causes the element 48 to be stored as a marker and also to cause the termination of the pulse.

After a digit has been completely transferred; a pause is inserted between two digits, and the passes during this pause are counted in the S section. A pause lasts at least thirty-six runs, and since a 4 was stored as the last digit in section 5, the pause is only ended after section 6 "has counted forty runs.

On the first pass for the pause between the digits, the switch position 31 is used as a spacing designated. From this point up to the pass PiV 65, a 1 is added to the count irri Section "S" is added for each pass.

When the marking appeared in the switch position 28 during the passage PN 66, a control device was actuated, and further control devices become effective when a marking is stored in the switch position 30 '. These together indicate that the correct procedure for this number has been carried out. When pass PN 66 occurs, element 12 is spaced and during pass PN 67 element 13 is also spaced. The same applies to the switch position 20, which indicates that the first digit has been sent, whereas the switch position 21 goes into the marking state. This informs the control device that the next digit to be sent is the second one stored

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Digit is. This pass clears the count in the

_: Section S.

As already described, other digits can be recorded and saved during the pause between the digits. The second digit is now released from storage just like the first, under the control of section D 2.

Forwarding the received digits to

ίο their places on the section is controlled by the counter in the control circuit by tapping the message content. A counter causes the received digits to be forwarded to the appropriate sections of the memory path, which switches step by step at the end of each digit. A second counter is used to determine what retransmission can take place and a third counter diverts the digits out. These counters are brought into switching positions that are suitable for storage and work together with the control circuits, specifically under control of the stored message contents in the individual sections of the storage path.

At the end of the receipt of the second digit, a marking is stored in switch position 22, and when the second digit is sent, the one previously stored in switch position 21 is saved Mark deleted.

In the same way, markings are embossed on the switch positions 23 and 24 as soon as the third and fourth digits are completely received. If at the end of the retransmission of these digits the switching operations are finished, the markings on the switching positions 22 and 23 turned off.

When the transmission is complete, element 1 is converted to a distance, and when the distance is tapped in time slot T 1, it causes element TCC 5 (the identifier for channel 4) to be relocated to a distance The storage can then be carried out for each of the channels 1 to 3 before the marking in switch position 5 is re-stored as the distance.

From the preceding description it can be seen that the functions of the control circuit play a subordinate role. The message content received from the user equipment were, d. H. the burst series from a communication channel to which storage is assigned should be, and the message, which identifies the switching state of the consumer device, as well as the sequence of the switching processes are recorded in the memory device, The control circuit handles all storage processes one after the other. When a save starts namely after the passage on the heads, the control device is tapped according to the Information is put into operation and then controls the necessary switching operations. While these switching processes take place, the control circuit causes new memory information, which initiate the further sequence of the switching processes. At the end of the run, the Control device free and available for new storage processes to disposal. <

It is recalled that all time-limiting operations are carried out by a counter with the help of Runs on. the heads are executed. If so, the establishment of a combined storage and Pick-up head as well as the corresponding circuit is required, the time limit is due Counting of whole revolutions of the drum carried out.

Before starting with the description of the details, the circuit diagrams, there are some explanations required with regard to the circuits.

The electronic gates, which are known to themselves, are shown as circles and the controls the same with the help of radial lines, the arrows of which touch the circles. The outputs of this Goals are also shown as radial lines, but their arrows point outwards. the Numbers within the circles indicate the total number of tax organs that must be effective so that a gate releases an output voltage. If z. B. four S expensive lines are available and the number inside the circle is a 2, then go releases the gate with an output voltage if two these control lines are effective.

If a short line is drawn across the control line, as is the case with the control line / 43 for the gate G 62 in FIG many of its other control lines are also effective. The excitation of such a control line can lock the door under certain circumstances. The names for all gates begin with the letter G.

The remaining known switching elements used in the arrangement described are electronic trigger circuits with two stable positions, counters and registers with several stable positions Locations.

A counter, which contains a number of individual steps, each of which is able to adopt one of two switch positions, namely "on" or "down", is represented as a series of rectangles lying next to one another, e.g. B. C 3 in Fig. 5. The counters shown all count to the end of their switching options and are then brought to the rest position. A register with several stable positions, for example F10 in Fig. 6, is shown exactly like a counter, only with the difference that the longer dimension of each rectangle runs in the vertical direction, while the longer dimension of the counters in the horizontal direction Dimension lies. A register with several stable positions is essentially constructed in the same way as a counter, but it usually does not run through all the switching positions. As with the counter, only one switching step is in operation in a time unit, and depending on the switching status, it can

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Activate the next step for each step, whereby the step previously activated is in an ineffective switching state occurs.

Essentially, an electronic flip-flop with two stable positions is a. Register with two stable positions. The above-mentioned devices, namely the flip-flops, are denoted by the letter F and the counters by the letter C. The individual switch positions

ίο the counters are named consecutively with i, 2, 3 etc.

If a flip-flop and other output circuits were connected to all of the ports they were to control, it would create an intricate network of wires that is difficult to miss. The lines have therefore been omitted, and short control lines on the gates indicate, with a /, which organ controls these gates. So z. B. the flip-flop Fn make the line f 111 or / 112 effective, the last digit 1 or 2 indicates which switching pitch of the flip-flop the control line in question can be effective.

To make it easier to understand the circuit diagram, certain parts of the circuits are included fully illustrated in Figures 12-14. These will be described after Figs. 1 to 8 are dealt with.

Before proceeding with the detailed description of FIGS. 2 through 8, let us know A description of the general arrangement is also given with reference to FIG.

This shows three message channels: which are the incoming. Connection lines Ti, T 2 and T3 included. These belong to the outgoing lines, TO i, TO 2 and TO 3. A circuit arrangement belongs to each channel, namely the circuit arrangements CCi, CC2 and CC 3 with regard to the presence of three communication channels.

The three connecting channels ■ are assigned an electronic scanning device SCB , which searches for that channel which requires pulse renewal. Such a scanning device can of course also scan more than three channels. In the individual description, one scanning device serves ten channels.

Furthermore, the magnetic drum MD is shown in FIG. Five of the closely spaced storage lanes of this drum are shown. The first of these tracks MT is the marking ban, which, as already described, receives a marking at the beginning of each storage section of all tracks. The marking track MT is assigned a marking pick-up head MH , which picks up the pulses and controls the counter BC via an amplifier MA , which in detail, later loaded

'wrote, will.

The next path is the element or time path ET, which has a magnetic impression in every switch position (element). The element or time header EH and an amplifier EA are assigned to this path. The output of this amplifier runs on the one hand to an element or time pulse counter EC, which has a number of switching positions which is equal to the number of elements on each track section. On the other hand, the output from the amplifier EA runs to a pulse circuit PF, which generates the pulses 1 1, the width of which is a third of the pulses from EA . The second output from the pulse circuit PF is fed to a delay circuit D 1, which delays one third of the pulses from EA and thus generates the pulses i2. The second output from the delay circuit D 1 leads to a further delay circuit D 2, which produces the pulses 1 3 in the same way. Set the individual outputs of the counter EC. Pulses in the individual switch positions.

The exit at the marking track. is designated with TM and is used to bring the counter EC into its rest position.

The devices associated with a single lane will now be described. These include a storage head SH, a tap head RH and an auxiliary storage head ASH, the purpose of which will be described later. All of these. Heads, amplifiers ■ are assigned, which are not specified. The S ρ eicherb ahn, which is now to be considered, is the middle one and is used for those communication channels which are reached via the scanning device SCB . This scanning device is connected to a device RSB which controls the tapping, storage, "insertion and deletion" of message contents.

There are still others schematically. Scanning and control devices, namely RSA, SCA, RSC and SCC, are shown which are assigned to other memory lanes.

The devices below the drum MD in Fig. 1 require no further explanation, so that the description of the details can now be made.

If no channel requests storage, the devices F 13 and F 15 in FIG. 3 have switched their elements 1. At this point in time, gates C 516 and C 517 are blocked, since element 1 of device F 1 (toggle circuit) in FIG. 4, which receives the outputs of the tapping device, is not switched during switch positions 1 to n, since storage is not desired will. Gate 511 in FIG. 3 and the corresponding gates for the other messages and channels are also blocked, since element 3 of device F1 7 is normally connected via br 2 (FIG. 2) and therefore no potential on control line / 172 located.

When a track section begins to run past the pick-up head, element 1 of toggle switch F 13 is actuated in switch position ι, so that potential is applied via control line / 131 with pulses TCC 2 to TCC 11 to open gates G 501 to C- S10 to open one after the other, so that the device F 14 its elements 1, 2, etc.

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operated one after the other. The device F 14 has as many switching positions as there are message channels assigned to the memory path. As can be seen from Fig. 3, it is assumed that ten such channels

. 5 niches are available. Thus, every free storage lends itself to every message channel. The outputs of the device F 14 are applied to the gates GMi to GM 5 of the corresponding communication channels in Fig. 2, but these gates remain closed because the S expensive line / 132 is not conductive. Likewise, three outputs "are applied to the gates, for example G512 and G520 in FIGS. 7 and 8, which are assigned to the flip-flop F 7 in FIG. 7. The flip-flop F 7 with its element 2 becomes effective, and for the duration of the selection elements 2 to 11. Gate 512 and the corresponding gates for other channels are opened by the pulses TCC , but gate G S19 is blocked by the control line / I32. However, gate G 520 and the corresponding, Open gates for the other channels and accordingly gate G 521 through control line / 131, so that gate G 99 opens at time 1 2 for each of elements 2 to 11 and thus switches element 2 of device F7, so that "o" is saved for the selection items.

It is now assumed that message channel 4 is put into operation and storage needed for the purpose of pulse renewal.

Initially, the device F 17 in Fig. 2 is connected with its element 3, but when the loop from is closed, a positive signal to the gate GR ι is placed, which in conjunction with the control line / 173, the opening of the gate Gi? 1 causes and thus the element 2 of the device F 17 switches. The potential applied to the control line / 172 in FIG. 3 causes the opening of the gate 511 in the time slot TCC 5, and since element 1 of the flip-flop F 15 is switched, the gates G 515 and G 513 are opened and thus cause the switching of the Element 2 of the trigger circuit Fi3. The element 1 of the flip-flop circuit Fi3, which is not actuated, blocks the gates G 501 to G 510, so that the device F 14, which at this point has switched its fourth element, remains in the same position during this section storage. This prevents other communication channels from being switched on before the busy element is stored in switch position 1. At the time * 3 is via the control line TCC 5 the gate GT? 2 opened in Fig. 2, so that the element 1 of the device F 17 is switched. The signal is removed from the control line / 172 and thus prevents other storages for this message channel.

The potential at the control line / 132 in the switching position TCC 5 causes the opening of the gate G 519 in FIG. 7 and the blocking of the gate 521 and, as a result, the opening of the gate G 98 and the actuation of the gate G 98 via the time slot TCC 5 and t2 Element, ι the flip-flop F 7. This means that "1" is impressed on element 5 of the memory section. Since the counter F 14 remains switched with its fourth element, the gate G 522 and then the gates G 523 and G 99 are opened in the next time slot TCC 6. The element 2 of the flip-flop F 7 is thus switched. This means that "o" is saved for the remaining selection elements, ie 6 to 11. The storage which was carried out for these switching operations corresponds to the line PiV 1 in FIG. B. G 512, G 520 and G 522 for the individual selection elements. These are denoted by the indices η, η + ι, η + 2 for the time slots - > r controls of the three gates shown. It is noted that the time pulse control for gate group G 522 is one time slot later than the corresponding gates G 520. The remaining gates, which correspond to gates G 522, are set by TCC3 and / 141, TCC 4 and / 142. . . as well as controlled by TCC 11 and / 149. This ensures that when "1" is stored for one of the message channel elements 2 to 11, the following pulse switches the flip-flop F 7 and thus makes element 2 effective. For the case in which 11 is the element for receiving a "1", it is not necessary to switch the flip-flop F 7 and make element 2 effective.

It is assumed that a memory section must be switched as occupied in switch position 1, because otherwise this section, if it is connected to circuit 4, could also be connected to section 1, 2 or 3. It is therefore necessary to change the electrical state of the element 1 after it has been guided past the heads (normal tapping heads). For this purpose, an auxiliary storage device is arranged in relation to the normal 100 storage device in such a way that element 31 is tapped when element 1 passes the auxiliary storage device. The switch position 31 has been selected for this purpose for conventional reasons, but any other suitable switch position after the switch position 11 could also be used for this purpose. In the switch position 31, potentials are applied to the expensive lines / 132 and / 162, as will be described later, and the potential passes the gate G5i4 (FIG. 3) in order to store the character "1" in the switch position 1. As a result of this measure, the memory section is switched as occupied before the section is detected again by the tapping device. A special timing control for gate G 514 determines the switch position of the auxiliary storage device, with T31 representing a possible switch position. From the switching operations between the toggle switch F 16 and the gate G 514 it is understandable why the switch position must be later than the twenty-fourth. The element 2 of the flip-flop F 16 is used for the following reason. When old message contents have been recorded and passed on, the section of memory should be freed. This condition is determined by the fact that elements 20 to 24,

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which form the group L , are all switched to "o" when the message content has been sent. Until this occurs, element ι of toggle switch F becomes effective for one or more of these switching positions, gate G 518 is opened and element 2 of toggle switch F 16 becomes effective. However, when the message content has been transmitted, element 1 of toggle switch F 1 is blocked in switch positions 20 to 24, and thus element 1 of toggle switch J ⁷ 16 also remains inactive, and gate G 514 is closed in switch position 31. As will be shown later, such a measure allows the storage to be released. The magnetic state of the path elements ι to 11 corresponds to the lines PN 2 to PN 35 in FIGS. 10 and 11 and is maintained until the passage according to line PN 36 in FIG. 11 occurs.
At the end of this particular memory section, the pulse T 48 is applied to the flip-flops Fi 5 and F 16 and thus causes the actuation of the elements 1 for the test process to the next memory section. The pulse T 1 of the next section reverses the flip-flop F 13 and makes the element 1 conductive.

When element 1 of the section under consideration is tapped again, since it is now magnetized to "1", and element 1 of flip-flop F 1 is active, gate G 517 in FIG. 3 is opened by pulse T 1 and the element 2 of the flip-flop Fi $ switched. Since element 1 of toggle circuit Fi 5 is no longer effective, gate G 515 remains closed so that this storage cannot encroach on other communication channels by actuating element 2 of toggle circuit Fi 3. If, however, the pulse TCC 5, which corresponds to the switched-on channel 4, is applied to the gate G 516, the element 1 of the flip-flop circuit F 1 and. the EIe; -ment 2 of the flip-flop circuit Fi5 becomes effective, so that the gates G 516 and G 513 open and the element 2 of the flip-flop circuit 513 becomes effective, so that the element 5 retains its memory marking. Element 4 of counter F14 also becomes effective, and since element 2 of flip-flop F 13 and element 4 of counter F 14 remain effective for the remainder of the section storage, gates GM 1 to GM 5 in FIG. 2 are prepared, so that the storage of the message elements can take place, as will be described later. The elements ι and 5 have of course been saved as "1" anew, as previously described, and are retained for the further cyclical switching processes. Thus, in the next pass, the switching state is the same as shown in line PN 2 in FIG. 9. Element 2 of toggle switch F15 switches via gate G517 in time slot Ti, since the busy state is marked in element 1. It has already been emphasized that the element 2 of the flip-flop Fi3 is actuated by TCC 5 and that the switching element 4 of the counter. F 14 is switched. As a result, potential on line STL causes gate GM1 to open.

In this case, potential is applied via line LP1 to gate G 4 (FIG. 4), which opens as soon as time slot T 14 occurs. According to the same approach, three out of four control lines are effective for the GM 2 gates. Since the gate GM ι is open, is applied via the gates G 4 and G 5 to the element 1 of the flip-flop F 2nd potential. As a result, potential is applied to lines / 21, so that gate G 54 in FIG. 7 opens in the same time segment, which gate G 98 follows in switching position 1 2 of Γ14. Furthermore, the element 1 of the toggle switch F 7 responds to give a positive sign to the drum in the switch position 14, as shown in the characteristics. PiV 2 of FIGS. 9 and 10 can be seen.

The flip-flop F1 in FIG. 4 follows the magnetic switching states on the drum track, namely element 1 for the positive state or "ι" and element 2 for the negative state or "o". In the time segment T14, the element 2 of the flip-flop F1 was actuated, and as a result, the gate G 12 is also opened by the control lines / 12 and / 21. This is followed by the gate G11, so that the elements of the flip-flop F 5 switches. \

. When the group of time slots TR (TR 1 5 to TR ig) begins, the gate G61 in Fig. 8 opens. This is followed by the opening of element 15 at i2. Gate G 99, so that the element 2 of the flip-flop F 7 becomes effective again, whereby a distance for the first and all subsequent switch positions, the time slot R , is stored. Thereafter, any positive storage that was effective in section R is deleted when the storage in question becomes free, as described later.

The element 1 of the flip-flop F τ is actuated when the elements R 19 and L 20 are tapped, since these two elements are normally positive. In the time segment TL 20, the gate G 112 in Fig. 5 opens due to the potential on the control line / 11, and element 1 of counter C1 responds. While the counter C 1 assumes the switching position 1 in the time segment TL 20, the gate G 74 and then the gate G 73 opens, since the device F 10 in FIG. 6 normally assumes the display position ι. The gate G 98 therefore opens in the position 1 2 of the period T 20, and the element 1 of the device F 7 responds to positive. tiv to save or to identify the element 20.

At the beginning of the time segment TL21, the switching state of the web changes to distance, and therefore the element 2 of the flip-flop circuit F τ responds, so that there is no longer potential on the common control line to the gates G112 ..., which control the device C 1, so that it remains in switch position 1. The gate G 91 in. Fig. 8 opens, and in connection with the time period TL21 opens the gate G95, so that in the position i2 the dead G 99 opens and thus causes element 2 of the toggle circuit F 7 to respond and the storage head to one Distance registered. Until the

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Switch position T 48 is reached, no other switching functions occur.

Returning to the message channel in Fig. 2, as soon as the switch position T 48 is reached, and with regard to the toggle switch F 8 in Fig. 6, which normally occupies the switch position 2, the gate GL2 and then GM 5 opens, so that the Element 1 of the. Toggle switch PA opens, whereupon the relay AR responds. The contact ar 1 thus closes the outgoing loop.

The relay BR was loaded in the time slot T 14. in which the goal GL 1 with the element 1

■ ■ · '· the flip-flop switch F 7 had opened. Closing contact br 1 switches the repeater as occupied: - occupied.

Also in the time slot T 48 and depending on the flip-flop F 8, which is in. The switch position 2, and the counter F 4, which is in the switch position 3, the gate G 87 opens in Fig. 7, where the dead G 98 follows, so that the element 1 of the flip-flop switch Fy becomes effective and thus a positive storage for the switch position 48 takes place. Up to the first, selection pulse, which was picked up by the repeater, successive passes of the section under consideration have been carried out to the pick-up head, which causes the same sequence of switching functions as before, the only difference being that these passes are counted to section R. This count has no meaning at this moment, but it is used for timing purposes and takes place in the pauses, between, the. Pulses instead to sample the periods between digits. Before the switching operations are described further, the timer will first be discussed.

During pass PiV 3, nothing occurs in time slots T 12, but in T 13. Element ο of counter Ci in FIG. 5 is actuated. One can see from this, that the time slot T 13 denotes. Counter C 1 always in position ο. wants to bring. The positive storage in element 14 is tapped off and stored again. As before, element 1 of flip-flop F 2 in FIG. 4 becomes effective in time slot Ti4. This causes the opening of the gate G 9, since the element 1 of the flip-flop F ι is actuated, so that the gate G 8 opens and the element 1 of the flip-flop F 5 becomes effective.

At the time slot TR 15 opens the dead G 14 in Fig. 4, and the element 2 of the flip-flop F 6 switches, and in connection with the. Element 2 of toggle switch Fi opens gate G57 in FIG. 7, since no marking has been stored in switch position 15. At the same time, the gate G 56 in Fig. 7 has opened under the control of the control line / 51 and TR , so that the gate G 60 opens and in the time position Ti? 15 and t ~ 2 - the gate G 98 opens and the element 1 of the flip-flop F 7 opens to a marker in the time slot. 15 to save.

In the section TR 15 and £ 3 and depending on the fact that the elements 2 of the flip-flop circuit F 1 and P 6 have switched, the gate G 15, which is connected to the gate G 3, opens so that the element 1 of the flip-flop circuit F 6 switches again . In the time slot Ti? 16 is element 2. the toggle switch F 2 is still operated, so that ß the gate G 64 in. Fig. 8 opens, which .das gate G 63 connects. In addition, the gate G 99 has opened in. T2, so that the element of the toggle switch F 7 responds and stores a distance in the switch position 16. In the remaining switch positions R and depending on element 2 of toggle switch F 1, gate G 64 opens in FIG. 8 and not gate G 59 in FIG. 7, so that element 2 of toggle switch Fy remains actuated and the distance storage over the whole. Section R is continued.

With each subsequent pass, the memories are changed in the switch positions R up to the first, spacer element. This change adds a 1 to the binary character already mentioned in the i? is stored. If you look at. z. B. the case when the switching position 15 and none, other contains a positive storage after the pass PiV 3, as just described. As before, element 2 of toggle circuit F 6 responds via gate G 14 in time segment TR 15, but since element 1 of toggle circuit F 1 is active, gate G 62 in FIG. 8 opens. Place of gate G 57. Gate G62 can open, there. the element 3 of the device F 4 in FIG. 4 is not actuated. The gates G63 and G99 open, and the element 2 of the flip-flop F y switches through in order to store the distance for the time slot 15 in place of the marking which was previously stamped there. Since element 1 of toggle circuit Fi is actuated, gate G15 in FIG. 4 cannot open, and element 2 of toggle circuit F 6 remains actuated.

In the .Zeitlage TR 16, the element 2 of the flip-flop F 1 is operated, and with the switched element 2 of the flip-flop F.6 opens the gate G 57 in Fig.- 7. The gate G 56 is also open, because of the Element 1 of the flip-flop circuit F 5 in Fig. 4, so that the gates G 60 and. G 98 are open and the element 1 of the flip-flop Fy responds to store a marker in position 16. The element 2 in the flip-flop F 1 is open during the time segment TR 16, so that at £ 3 the tones G 15 and G 3 open in order to open the element 1 of the flip-flop F 6 in FIG. This leads to a storage during the time segment TR 17, which in this case means the switching condition for the distance, depending on the opening of the gates G 64, G 63 and G 99. It can be seen that the toggle switch F 6 is the first Distance between the switch positions, in. The group i? scans. When the element 2 of the flip-flop F 6 is actuated, the opposite of what was tapped is stored. When element 1 of flip-flop F 6 responds again, the switch positions are saved as they were tapped. This results in adding ι to the binary character that is used in the time slots i? was saved with each run. The number of free revolutions is shown in FIG. 10 by the lines PN 3 to PN 5. During the

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The run PN 3 applies contact ar 2 in Fig. 2 via the gate GM 2 S feuerleitung- LP 2 to the gate G 16 in. Fig. 4, which therefore opens in the timing TL 24 to allow the actuation of the element ι the Initiate toggle switch F 2 zn . However, the measure has no immediate purpose.

When the first digit pulse has been received, which consists of opening the loop on wires a, b , this results in a change in the ίο potential on the line STL and thus closing the gate GMi. As a result of this, the gate G 4 in FIG. 4 cannot open in the time slot T 14 during the next run, and the element 2 of the toggle circuit F 2 remains actuated. It is necessary to delete the storage in the time slots R , from the period of occupancy to the first pulse. For this reason, the marking stored in element 14 must also be deleted. As soon as the time segment T 14 is reached, the element 1 of the flip-flop F 1 responds. This has no immediate effect, but the control line / 11 in conjunction with the control line / 22 opens the gates G 10 and Gn and also actuates the element 2 of the toggle circuit F 5. The control line / 22 in conjunction with the time slot T 14 opens the gate G 55 in FIG. 8 and at t2 the gate G99 in order to carry out a distance storage for the element 14.

At the beginning of the period Ti? 15 opens the gate G 61 in FIG. 8 depending on the control line / 52 'gate G 99, so that the toggle switch F 7 continues the distance storage. The flip-flop / ⁷ 7 remains for the other elements R in this position.

In the time slot TL 20, the element 1 of the flip-flop circuit F 1 in FIG. 4 responds. The counter C 1 in Fig. 5 is brought into the rest position in the time segment Γ 13, as previously described. Gate G 112 is now open and element 1 of counter Ci is switched through. The control lines C n and TL 20 open the gate G 74 in'Fig. 7. The element 1 of the toggle switch F 1 is actuated by the marker storage in the element 20. The control lines / n, TL20, / 103 open the gate 108 in order to actuate the element 1 of the toggle switch F 10 in FIG. As a result, the control line / 101 opens the gate G 73, since the gate G 74 is open. In the time slot TL 20 and i2, the gate G 98 opens and the element 1 of the flip-flop F 7 responds in order to store a marking in the element 20.

Via the control line TL 21 in connection with the counter C1 in the switch position 1, the gate G 91 opens in FIG. 8 and with the control line TL the gate G 95 opens to cause the opening of the gate G 99 and also the actuation of the element 2 the flip-flop F 7. The distance storage is continued over the time slots TL21 to TL 24, section ^ and time slot T31.

It is necessary to store a marker in the switch position 32 of the section Di in order to record the received pulse.

It can be seen from this that elements 1 and 2 of device F 4 in FIG. 4 are controlled by control lines / 11, T 14 and T 13, respectively. This means that during the 'previous runs with a marker stored in element 14, device F 4 switched from element 1 to element 2 and back during each run. In the case of the control line T 14 of the present run, element 1 of device F4 has responded again because a marking was tapped and element 1 of flip-flop F 1 is switched. ■

In the previous runs with potential at LP ι, element 1 of flip-flop F 2 A is actuated during section T 14, and gate G 9 is opened in connection with element 1 of flip-flop F ι. This period of time, but without potential at LP 1 as a result of the pulse interruption at loop a, b in Fig. 2, causes element 2 of flip-flop F 2 to remain actuated and, in conjunction with control line / 11, opens gate G10, to which gate Gn follows to operate the element 2 of the flip-flop F 5. When TD 32 is reached and when the counter C1 assumes switch position 1, gate G 18 opens and continues to open gate G 22 in connection with control lines / 41 and / 52, so that gate G 14 opens in time slot T 1 and the element 2 of the flip-flop F 6 becomes effective. The control lines / 12 and / 62 open the gate G86 in Fig. 7, so that the gates G85 (from T-D32 to TD35, ie TDi to TD4) and G98 open alternately. The element 1 of the flip-flop F 7 responds in order to store the marking in the element 32. The first element of group D 1 is used to store the first digit.

In the time interval T 32 and * 3, potential from element 2 of flip-flop F 6 opens gate G 15 and then gate G 3, so that element 1 of flip-flop F 6 is actuated. As a result, the remaining spacer elements 33 to 47 are picked up and stored again, via the control lines / 61, / 12 and gate G82 in FIG. 8. ■ · ■

In the time slot T 48 a marking is tapped, so that the element I of the flip-flop F ι becomes effective. It is desirable to retain a memory marker in element 48 until it is necessary to retransmit the stored pulses. This is controlled by the flip-flop circuit F 8 in FIG. 6, which has actuated its element 2 at the moment. As a result, the gate G 87 opens, which is followed by the gate G 98, whereupon a positive storage is carried out in the element.

The next function of the control circuit is to tap the end of the first dialing pulse, which is stored, and to measure the duration of the pulse. When the pulse is tapped, the flow counter for subsection R is brought to the rest position. In the next and the following iterations while

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whichever pulse is present, "i" is added to the binary character stored in subsection R in the same manner as described above for the post-seizure state before the first pulse was received. If there is an interruption in loop a, b in FIG. 2 until the last binary storage element R 19 is marked, a forced triggering takes place in the next cycle by actuating the third element of device P 4. This occurs because the second element of the flip-flop P1 has responded in section T 19, and the gate G 28 in FIG. 4 is actuated by the control line / 62 during the time slot TR 19. The element 3 of the device is then activated F 4 effective. A check now takes place as to whether all flip-flops have returned to the rest position and whether the communication channel is enabled by actuation of element 3 of device F 4. These operations are not described in detail.

It is now assumed that the first selection pulse ends within a normal period, so that the potential at LP 1 appears again.

The runs PiV 7, PN 8 and PiV 9 mark the counting of the runs for measuring the duration of the first pulse, while PN 10 shows what occurs after the potential at LP 1 reappears. In the time segment T 14, the gates G 4 and G 5 in FIG. 4 open alternately in order to actuate the element 1 of the flip-flop circuit F 2. The element 2 of the flip-flop F 1 is actuated during the time segment T14, so that the gates G 12 and GH open alternately to open the element 2 of the flip-flop F 5. Gate G 54 in FIG. 7 also opens in time segment T 14, followed by gate G 98 and element 1 of flip-flop circuit F 7, so that positive storage in element 14 is carried out. The elements R must be brought into the negative switching state. This is determined by opening the gate G 61 in FIG. 8, depending on the actuation of the element 2 of the toggle circuit F 5. In the next pass PN 11, the counting in the subsection R starts again and continues during the following passes until the next pulse appears.

The storage of the second pulse takes place during pass PN 12, namely by a series of switching operations which are essentially the same as those used to store the first pulse during pass PN 6. The only difference is that in subsection Di in Fig. 9 a "1" is added to a "1" instead of an "o".

It is assumed that the first digit is a 2 and that this digit is now fully incorporated would. However, the device cannot know this, and it must therefore know the switching state Determine by determining the deviation time, since the last dialing pulse is due to the count of sweeps was recorded and the last pulse was recorded and a mark in the Element L21 was inserted.

A pause between the digits is scanned when a marker has been inserted into element R 17 during the counting process. While still in the section Ti? 17, but after element 1 of flip-flop F 7 has been actuated, gate G 102 opens in the time segment TR 17, which is followed by gate G 104 and element 1 of flip-flop Fg switches. In order to receive the next digit, the counter C 1 must be switched to the second step, and in order to prepare the counting of the first digit, the storage in section D ι must be converted into the complement of the binary digit, which is achieved by converting each of the elements of the Section D 1 takes place.

The element 1 of the flip-flop F 6 is operated and the following elements R are stored. In the time interval TL 20, the element 1 of the flip-flop circuit P i switches, so that the gate G 112 in FIG. 5 opens, which causes the first element of the counter C 1 to be actuated. The gate G108 in Fig. 6 also opens, with regard to the control lines TL 20, / 11, / 103, so that the first element of the device P10 is actuated. Then the gate G 74 in FIG. 7 opens, which is followed by the gates G 73 and G 98, so that the marking is stored in the element 20.

Through the control lines TL 20 and £ 3, with the device C 2 in Fig. 5 on the step. O, and with the actuated element 1 of the toggle switch Fy , the first switch position of the device C 2 becomes effective. The gate G 137 in FIG. 5, which is followed by the gates G 136 and G 110, opens through the control line TL 21 and with regard to the actuated first switching position of the counter Ci. This causes the counter C 1 to switch to the second step, and at the same time the gate G103, which actuates the second element of the toggle circuit P 9, opens, whereby the gate Gi 10 is closed. The control lines TL21 and C12 open the gate G75 in FIG. 7, which together with the control line / 101 opens the gate G 73.

The last-mentioned gate in connection with the control line £ 2 opens the gate G 98 in order to actuate the element ι of the toggle switch P 7 and thus to store a marker in the switch position L 21. Via the control lines 21 and TL 1 3, the means C 2 switches to the element 5 \ This is in that the first digit has been completely received and that the transmission of this paragraph can be carried out in the -abgehende loop of the connection.

No switching operations take place up to the time segment TD 32. The complementary storage of the digits is controlled by the gates G 71, G 86, G 81, G83 and the associated auxiliary gates. It should be noted that the gate G 86, which controls the first element of the toggle switch Fy , is itself switched by the second element of the toggle switch P1, whereas the gate G 83, which controls the actuation of the second element of the toggle switch

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tang Fy controls, is made effective even by the first element of the toggle switch F ι. The storage is thus reversed in each element of the section D ι. The sequence of the inversion of the digit is controlled by the auxiliary store. The control lines TD determine which digit is reversed, while the counter C ι determines that only one digit in a time unit is converted in the correct sequence.

ίο Gate Gyi decides in which periods of the entire switching processes these conversions can take place, while gate G 86 controls the inversion of the elements. The first element of the flip-flop F 11 in FIG. 6 was actuated by the control line TL 20 through the first element of the flip-flop F 9 via the gate G 109.

It can be seen from this that, under the current switching conditions, gates G 65, G 71 and G 69, G 81 remain open during the entire section D 1, whereas gates G 86 and G 83 open alternately, taking into account the existing ones Memories in the elements of section D 1, in which spacing and marking are embossed. This causes the reverse re-storage. In the following runs, a coincidence occurs between TDi (TD 32) and the second element of the counter Ci before the next digit is received. Here, however, the first element of the flip-flop .Fn is not actuated because the first element of the flip-flop F 9 has not switched in the time period TL 20 (see gate G 109), because TR 15 ensures that the second element of the flip-flop F 9 switches. The gate G 102 is through Ti? 17 is not open for most of the following runs because the second element of the flip-flop circuit F 6 is not actuated. During the remainder of the time counting through the section R , the switching state is obtained that the elements R 15 and i? I6 both contain markings and the sections? 17 represents a distance, but only if the sections R 18 and R 19 are included. If, at the end of the complete count, all the elements R denote spaces, then the elements R 15 and R 16 denote markings and the elements R 17, i? I8 and i? I9 denote distances. In order to prevent the element R 19 from containing a marker at the end of the count, it is waited until the next interruption of the voice line occurs.

The element R 18 or i? I9 opens the gate Gioi as a marker in order to actuate the element 2 of the toggle switch F 9 and also to leave the element 1 inactive, so that at a point in time TL 20 and the gate G 109 does not open.

After the complete count in section R , elements R 15 and i? I8 are negative in the next run because element 2 of flip-flop F 6 in time section Ti? 15 is not actuated. However, when the time segment TR 19 is reached, the gate G150 in Fig. 4 is opened in order to switch the element ι of the flip-flop F 6. As a result, the element 1 of the flip-flop F y is actuated in order to store a marking again in the element R 19. When the speech loop is broken, element 2 of flip-flop F 2 in FIG. 4 remains actuated, and since element T 14 had marked the loop state, gates G10 and Gn open to actuate element 2 of flip-flop Fs. As a result, the gate G 56 in FIG. 7 remains closed during the time segment TR , and the gate G 61 in FIG. 8 opens in order to cause the storage of a distance in the time segment TR.

It can be seen from this that when pulses are transmitted and by adding 1 to the binary characters in section D1, the first digit is completely transmitted for each transmitted pulse if all elements of section D1 contain markings.

Each pulse is started during the last element position of a pass and is maintained for four passes, which are counted ^{by section 5 1.} As each digit is sent out, its storage in section L is removed.

The transmission of the first pulse is initiated by converting element 48 from a marker to a distance. As previously explained, the element 5 of the counter C 2 becomes effective during the passage and as a result of this in the time slots TS 2y and 1 1 the gate G120 in FIG. 6 is opened, so that the element 1 of the toggle circuit F 8 is actuated. Thus, in the time segment T48, the gate G88 in FIG. 8 is opened by the control line ^ 81, as a result of which a distance is stored in the element 48. The same control combination T48, / 81 opens gate GL 3 in FIG. 2. As a result, potential is applied to gate GM 6. It will be recalled that the counter F 14 in FIG. 3 causes the identification of the message channel in FIG. 2 to be stored. At the moment the counter F 14 is in the switching position 4 and thus applies potential to the gate GM 6. Furthermore, the elements 2 of the flip-flop circuits Fi 3 and Fi 5 are still actuated, so that the gate GM 6 opens. This is followed by 105 gate GM 8 in order to actuate element 2 of flip-flop FA , which switches off relay AR in order to initiate a pulse transmission with contact ar 1.

In the following runs, further digit pulses can be received and stored, in the same way as previously described, with the only difference that the next digit is stored in section D 2, etc. Attention is now paid to the pulse transmission, which is initiated in the switching position 48, line PN 20 in FIG. The following runs are shown graphically in FIG. The counting processes in the lines PN 21. . . for section R are skipped so that the first switching we will consider is the counting of the first pass of section S. The drop in relay AR opens the contact ar 2 and thus removes negative potential from the line LP2 in FIG. 2. The element ι of the flip-flop circuit F 2 in FIG. 4 can

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be actuated by the line LP ι in the switch position T 14 via the gate G4, but in any case, the element 2 of the flip-flop F 2 is actuated again during the time segment TR. By removing the potential from line LP 2 , gate G 16 does not open in section TL 24, so that element 2 of flip-flop F 2 remains actuated and gate G 58 in FIG. 7 opens in time section TS. The element 2 of the flip-flop F ι is conductive, because the group is empty of elements positions 6 ", ie that all the elements are identified as distances. It was also by the potentials TS 25 and / 22, the gate G17 in Fig. 4 and 1 1 the gate .G 14 is opened in order to actuate the element 2 of the toggle switch F 6. As a result, the gate G 57 opens in FIG Time potential i2 and G 98 the element ι of the flip-flop! ⁷ 7 becomes effective and thereby a marking is stored in the element ^ 25. With the time potentials £ 3 and fi2 , the gate G 15 in Fig. 4 opens, so that the element 1 of the Toggle circuit F 6 responds again and thus prevents the markings from being stored in element positions 26 to 30. These time elements mark a distance so that the time potentials at / 12 and / 61 open gates G 64 and G 63 in FIG the element 2 of the flip-flop Fy to the spacing sp Re-register for these elements.

It is necessary to store the fact that a pulse has been sent out so that after a pulse has been added in section D 1 during the current cycle no further pulses are added in section D 1 until the transmission of the first pulse has been completed and the Transmission of the second pulse has started. This storage is carried out in element 31 between sections 5 ¹ and D 1. guided. ■

The time pulse combination TS and / 22 has activated the element ι of the flip-flop F 12 in Fig. 6 via the gate G 125, so that the gate G 89 open via the time potentials T 31, / 121 and / 22 and thus via i2, the gate G 98 the element j of the flip-flop F 7 is actuated in order to cause a marking to be stored in element 31. A pulse has now been added in section D 1. ,

In the time slot TD 32 and in the switch position 1 of the counter opens the gate G 23 in Fig. 4, and in connection with the time potential / 121 (Fig. 6) opens the gate G 27, so that with ii and TD 32 the gate G 14 opens and the second element of the trigger circuit F 6 is opened. It is now necessary to change every element of section D 1 including the first distance. When the element 32 has stored a distance, the element 2 of the flip-flop F 1 is actuated, and with the switched element 2 of the flip-flop F6 , the gate, G86, which is followed by the gates G85 and G 98, opens the element 1 of the flip-flop F. 7 to be pressed and thus to save a marking. Due to the time potentials TD 32 and ti , the element 2 of the flip-flop circuit F 6 responds again because the element 32 was tapped as a distance. This prevents any further changes in the re-storage of the elements TD 1. In a special case, which is shown in the line PN 21 in FIG. 11, the element 32 contains a marking and was relocated to a distance by opening the gate G 83 in FIG. This was done through the potentials / 11 and / 62, which acted on goals G 98 and G 99. Element 2 of the toggle switch! ⁷ 6 remains actuated, so that the element 33, in which a distance is stored, has been converted into a marking with the aid of the gate G 86, as already described. The element 1 of the toggle switch F 6 is now actuated to prevent the reversal, so that the elements 34 and 35, 'in which markings are already embossed, receive new memories through the gate G 24.

The remaining elements 36 to 48 are stored again as they were tapped off, with a view to the possibility of the digit storage in section D 2 continuing to be carried out.

In each of the next three passes, a pulse is added to the group with the element position ^ S ", but neither element 31 nor segment D 1 is changed because the transmission of the first pulse is still taking place.

On the line PN 22 in FIG. 11, when the section 6 * is reached, the element 1 of the flip-flop Fi responds, specifically in the time element 25. The element 2 of the flip-flop F2 has when it was necessary in the time slot TR , addressed again, so that in the time slot TS 25 the gates G17 and G 14 open and the element 2 of the flip-flop switch F6 operate. Gate G 62 opens via control lines f02 and / 11, followed by gate G 63, and element 2 of toggle switch F 7 responds in order to store a distance. The element 2 of the toggle circuit F 6 remains actuated, so that in the timing element 26 when element 2 of the toggle circuit Fi is actuated, the gate G 57 in FIG. 7 opens and in connection with the gate G 58, which was opened by the control lines TS and / 22 , the gate G 6 opens to cause the element 1 of the flip-flop F 7 to store a marker. Via £ 3, element 1 of flip-flop circuit F 6 responds again via gates G 15 and G 3, and the remaining elements of section 5 ¹ are newly stored as they were tapped.

During the passage PN 21 (FIG. 11), the element 1 of the flip-flop circuit F12 in FIG. 6 was actuated, specifically by the control potentials TS and / 22. Element 1 of flip-flop F12 remains addressed via element 31, which is referred to as element SCM , and beyond that up to section Di. While running along line FTV 22, element 2 of flip-flop F12 is actuated in time segment T 31, since the element 31 as

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Mark has been tapped and potential is on control line f 11, so that gate G 126 opens.

Likewise, in the time slot T 31, the gate G 89 in FIG. 7 has opened by the control potentials / 11 and / 22, so that the element 31 is again stored as a marker. Since element 2 of toggle circuit Fi2 is actuated, gate G 27 in FIG. 4 cannot be opened and element 1 of toggle circuit F 6 remains actuated. As a result, the gates G 84 and G 82 in the section D 1 store the elements as they were tapped.

In the line PiV 24 a total of four pulses are added so that the time element 27 is marked. Via the time potentials T 27 and ί ι in connection with the element 5 ″ of the counter C 2, which is still actuated, the gate G 120 in FIG. 6 opens in order to actuate the element 1 of the flip-flop F8 as before. However, as a result of the time potentials TS 27 and £ 3 and with regard to element 1 of the toggle switch F 7, which is actuated to store a marker, gate G 124 opens, followed by gates G 123 and G 122, so that element 2 of the toggle switch F 8 is operated again. the element 2 of flip-flop i ⁷ 6 in FIG. 4, during this cycle it is not operated, so that the time elements are stored to 47 so again 28 as they were picked up. However, opens at the timing T 48 and as a result of the actuated second element of the multivibrator FS goal G 87, and a mark is stored in the timing element 48. the control potentials / 82 and T 48 is also open the gate GL 2 in Fig. 2, so that the gate GM 5 opens to switch the FA toggle switch with its first Element and the relay AR to be excited so that the contact ar 1 closes to determine the first pulse. In addition, the contact ar 2. is closed, which applies voltage to the line GM 2, which replaces the potential on the line LP · 2. During the passage of PN 25, the first element of the flip-flop F 2 is actuated in the time slot TL 24 because the line LP 2 opens the gates G 16 and G 5. The gate G 17 in Fig. 4 is therefore locked in the time slot TS 25, and the element ι of the flip-flop F 6 remains actuated. It is now necessary to delete the marks stored in time slots 5 and T 31. The first element 5 ¹ in the time slot 25 is a distance, since the number 4 ^{is stored in the time slot, S 1} , and as a result the gate G 64 in FIG. 8 is also opened by the control potentials f6i and / 12. Then the two gates G 63 and G 99 come, and the second element of the toggle switch F 7 is actuated to re-store the distance. Since the first element of the flip-flop F 2 is active, the gates G 57, G 58, G 59 and G 89, which control element 1 of the flip-flop F 7 for the time slots ^ and T 31, can be the first element of the flip-flop F 7 do not operate, and a distance storage is therefore carried out over the time slot ^ for the time slot T 31. During the time slot TDi , the first element of the flip-flop F 6 remains actuated because the element 2 of the flip-flop F 12 is still actuated and the gate G 27 in FIG. 4 cannot open for this reason. The gates G 84 and G 82 now control the restoring of the elements of the section D 1 as they were tapped, since the control potential / 11 opens the gate G 84 in order to open the first element of the flip-flop F 7. The control potential / 12 opens the gate G 82 in order to actuate the second element of the flip-flop F 7. The time slot element 48 is stored again as a marker 75 'via the gate G 87, and the relay AR remains picked up.

Track PN 26 is used to remove the second pulse by removing the stored marker in timing element 48, as was done previously with track PN 20. In the time slots TS 27 and ii, the element 1 of the flip-flop circuit F 8 in FIG. 6 is activated as before, and it also remains activated, since in the time slots TS 27 and £ 3 neither the control potentials fji nor / 11 are effective so that gates G 124, G 123, G122 remain blocked. When the time slot element 48 is reached, the gate G 88 in FIG. 8 opens as a result of the control potentials / 81 and T 48, so that a distance storage takes place with element 2 of the flip-flop circuit Fy.

Furthermore, the control potentials / 81 and T 48 open the gates GL 3, GM 6 and GM 8 in order to actuate element 2 of the flip-flop circuit FA and thus throw off the relay AR. As a result, the second pulse is initiated by opening contact ar 1. As usual, the pulse is retained over the next four runs, namely in the tracks PN 26 to PiV 29. The processes described for the first pulse occur, only with the difference that section D ι receives an additional pulse which completely fills out the section, d. left, he leaves this section fully marked, which determines that the transmitted pulse is the last one for the digit. Accordingly, the time slot elements 12 and 13 are converted into a marker. In the track PN 27, the section D 1 is completely filled. As a result, the gate G 128 is not opened in the track PN 28 for timing TD 1, although the gate G is opened 129 in Fig. 5 by the control potentials TD 1 and C 31, because the control potential / 12 is not effective, so that the element 1 of the flip-flop circuit P 9 remains actuated. Tn time slot Γ48, gate G127 in Fig. 6 is opened by controlling the potential / 91 and actuates element 1 of flip-flop circuit P 23. The auxiliary memory registers a mark in time slot element 12, as described earlier for element 1 in track PiV ι . The flip-flop circuit P23 is reset to element 2, which was actuated by the control potential £ 3.

During the cycle P7V 29, the gate G ι in Fig. 4 is actuated by the element 1 of the flip-flop circuit P1 in the time slot T 12, which opens and the element 1 of the flip-flop circuit P 3 switches on. In the

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Time slot or in the element T 13 opens the dead G 5 ι in Fig. 7 as a result of the control potentials / 31 and T 13, whereby a marking in the element: 13 is stored. As before, gate G 127 opens in

'5 of the time slot T48 with an effective control line fgi.

This causes the auxiliary memory to insert a marker in the time element T 12.

- In the case of circulation PN 30, the tapping of the marking in time element 12 causes element 13 to pick up a marking again, and the auxiliary memory stamps a marking in time element T 12 at the required moment. In the meantime, the count 5 "has stored the fourth run for the pulse 2, so that the element 27 receives a marking. As with the circulation FiV 24, a marking has been made in the element 48, so that the relay AR in has attracted in order to end the regenerated second impulse and with it the first digit as well. 20 It is now necessary to measure a pause between the digits, which is formed by a group of the timing elements J?

As can be seen from FIG. 11, the recording of the second digit from the message channel in FIG. 2 has not yet been initiated, and the tracks PN 21 to PN 30 show the timing element R, which is used to count the runs up to reception the second digit is used. Section R counts more than once when the second digit is delayed for inclusion. The reception of the second digit has been omitted in FIG. 9 in order not to complicate the diagram unnecessarily. However, it is believed that the inclusion of the second digit with the similar. Switching functions is carried out, as shown in the: Tracks PN 6 to PN 20.

The smallest pause between two digits comprises thirty-six runs after the stored marking of the first digit in the element curve L is deleted, ie is newly stored as a permanent interval, in order to enable the second digit to be retransmitted after reception. The storage in, the time slot S is held, so that the counting of the pause is from 4 to 40. In the track PiV 31 the first element of the flip-flop circuit Pi is activated again, which is followed in the time slot T 12 by the first element of the flip-flop circuit F 3, so that in the time slot TS 25 the control voltage / 31 ^{opens the gates 1} G 17 and G14 to operate element 2 of flip-flop F 6.

The control voltages TS and / 31 open the gate G 58 in FIG. 7. Since the time element 25 acts as a spacing, the control voltages / 62 and / 12 open the gate G 57, so that the gate G 60 is then opened and a mark comes for storage. This adds a 1 to the storage in time slot 5. As before, the element 1 of the flip-flop F 6 is actuated in the time slots TS 25 and £ 3 in order to restore the memory for the. Allow rest of the time slots 5 *. Since the relay AR has responded again, potential is on. the line LP 2 laid in. Fig. 2 and 4, so that in the time slot TL 24 the first 6; Element of the flip-flop F 2 becomes effective. In the time slot iT3i, the gate G90 in FIG. 8 is opened by the control voltage / 21, and the element 31 is stored again as the distance. The remaining time elements are re-saved as they were tapped.

On the tracks PiV 32 to PiV 65 there is no change with the exception of the addition of ι in section 6 * for each pass. Since the marking was stored in element 28 during track PN φ , the control potentials or time slots open gate G 107 in FIG. 6, and gate G106 actuates element 2 of flip-flop F 10 , open the control, potentials / 71, T ^ 30 and / 102 dieTöTeGiii and G 103 to the second element of the flip-flop circuit Fg in. actuate.

As a result, no occurs in time slot T 48. Control potential on line / 91. The flip-flop circuit P 23 with its element 2 therefore remains actuated. In the time slots. TS 28 and TS 30 open gates G107 and Gin, one, distance, into the time element. 12 to, save. This is done by actuating the elements 2 of the flip-flops P 9 and Ρίο through markings in the. Timing elements, 28 and 30.

During the rotation PN 67, the time elements 12 and 13 have stored a distance, whereby the element 12 is tapped as a distance, but the element 13 is evaluated as a marker, since the control potentials 13 and the second element of the flip-flop P1 open the dead G 2, to operate the second element, the flip-flop P 3. Control potential / 32 opens gate G 52 in FIG. 8 in time slot T 13. Also in time slot Γ13, control potentials T 13, / 11 and / 32 open gates G 105 and G 106 around the time element. 2 of the flip-flop circuit P 10 in FIG. 6 to be satisfied. In the time slot TL 20, the gate G 95 in FIG. 8 is opened by the control voltages / 102 and TL20 to a distance instead of an earlier one. Save mark. The gate G 138 in FIG. 6 is opened by the control voltages / 102 and i3. The dead G.108 is then opened by the control voltages TL 20 and / 11, so that the element 1 of the flip-flop circuit P10 responds. The gate G 75 in Fig. 7 is therefore opened by the control voltages TL21 and c 12 and the dead G 73 through, the gate G75 and the control potential fioi, so that a marking in the time element 21 is stored. In the time slot TL 22, the gate G 92 is opened by the control potential c , which in turn the gate G 95 is opened to a. Save distance. The remaining time elements of the section L are newly stored as they were tapped.

It is now necessary to delete the markings stored in time segment 5 ".

In, the time slot TL 24 and LP 2, the gates G 16 and G 5 are opened to the element 1 of

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Toggle switch F2 to open. In the time slot TS 25, the gate G 58, which is controlled by the voltages / 22 or / 31, cannot open, so that the gate G 60 also remains blocked. In this way, the storage of a marker in the section 6 ^{1 is} prevented. A distance is therefore stored because the gate G 64 in FIG. 8 is opened by the control voltage / 12 and / 61. Furthermore, element 2 of toggle switch F 7 is actuated via gate G 63, which remains actuated beyond time segment 5 ″.

It is now important to describe in detail the storage and transmission of the following digits, but the successive switching functions controlled by the counters Ci, C2 and C3 will first be discussed. The second digit is received with the counter C 1 in time slot 2, and at the end of the storage, the counter C 1 is controlled by the gates G 137, G 133, G 134 and G 135, which one after the other in the individual counting positions cn to c 14 or in the time slots TL 21 to TL 24 are open.

The counter C 2 is used to determine whether the. Transferring another digit is feasible. The control gate G 118 can be opened in each of the two successive time slots TL in which the marking is stored by the control potential during a cycle of the counter C 2 in the switch positions ο and 1, so that the counter C 2 from. switching position ο switches to 1 and from 1 to switching position S, if the switching conditions require this. The counter C 2nd in the switch position S allows the next digit to be transmitted. The counter C 2 is set to ο in the time slot T 12 for each cycle, namely by a potential which is applied directly to the element ο of the counter C 2.

The counter C 3 counts the transmission of the digits.

4.0 The advancement of the counter C 3 to the next switch position in any time period depends on the existence of switching conditions, such as. B. are shown in the track PN 67 in Fig. 11, in which the first time slot L a

+5 distance represents.

The counter C 3 successively counts the switch position L from 20 upwards and is reset in each subsequent switch position T 12. In such switch positions, the control line / 72

so effective. As already mentioned, the counter C'2 is in the rest position, so that in the time slots 1 3 of the successive switching positions TL 20 to TL 24 when the control lines / 72 come into effect, the counter C 3 receives a pulse and advances it step by step. However, since the switching position TL 20 is free in the track PTV67, but the holding position TL 21 is occupied, in the switching position TL21 the control potential / 71 becomes effective instead of the control potential ^ 72, and the counter C 2 switches to position 1, so that the counter C 3 cannot switch to the later empty switch position L because of the effective control voltage / 72 (e.g. L 22 to L 24).

As before, the receipt of the second digit is stored. Since the counter C 1 is now in the switch position 2, the gate G 74 in FIG. 7 is not open in the time slot TL 20 of the next run after receipt, nor is the gate G 91 in FIG. 8 in the switch division TL 21, but the gate G 75 is opened in the time slot TL 21 by the control voltage c 12 in order to save a marking in the time slot L 21 ..

While in the case of the first digit the counter C 1 was in the time slot 1, so that in the time slot TD 32 the control voltage cn has opened the gate G18 in FIG. 4, in the case of the second digit the gate G 18 is not opened, but in the time slot TD 36 the control potential at ei2 opens the gate G 19, and in this way the first pulse of the second digit is stored in the switch position 36 instead of in the switch position 32, and the whole number is stored in the time slot group D. 2 , which contains elements 36 to 39.

At the end of the second digit, a marker is inserted into the time slot TL 22 after the counter C 1 has been brought into its third switching position, namely by opening the gates G 76, G 73 and G 98 in FIG. 7. The second The digit is sent the other way round and in the same way as the first digit, with the only difference that the time slots TD 36 to TD 39 are used instead of the time slots TD 22 to TD 35. The remaining digits are stored in a similar way and sent out again .

■ At the end of the transfer, the marking in switch position L 21 is removed. After receiving the third and fourth digits, marks are inserted into the time slots L 23 and L 24, while at the end of the transmission of the third and fourth digits, the marks in the time slots L 22 and L 23 are removed,

When all message contents have been received and sent, the storage is no longer required and must therefore for the assignment to another message channel, which one Storage wishes to be made free. The switching processes necessary for this develop as follows.

It can be seen later that the elements 20 to 23 of the section L are in the "o" state. As a result, the switching element 2 of the flip-flop F1 is effective when these elements pass through at this point in time. Consequently, the dead G 518 in FIG. 3 is not opened in the time segments TL 20 to TL 23, so that the element 1 of the flip-flop circuit 16 is left effective and the gate G514 remains closed in the time slot T31. Here, "o" (distance) is saved in element position 1, which indicates that the memory device is now free. It is now necessary to delete the storage in the time slot TCC 5. This is carried out during the next cycle, whether a calling channel 1, 2 or 3 is switched on in the meantime or not. The next time element 1 of the flip-flop -F1 is canceled.

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so that the second element of this flip-flop is effective. The gate G 517 is not opened, so that the element 1 of the flip-flop circuit F 1 S in. Fig. 3 remains actuated. If nothing else occurs before switching position TCC 5 is reached, Toi G 516 remains closed and element 1 of toggle switch F 13 remains effective, although element 1 of toggle switch F 1 wants to actuate element 2. Thus, the gates G520 and G 521 in FIG. 8 are opened, since the device F 14 is still in the switch position 4 and the element 2 of the toggle switch F 7 is actuated, so that the storage "0" occurs in the time slot 5. The storage is now for others: Message channels free.

If the channel 1, 2 or 3 has occupied the common device, the switching element 1, 2 or 3 of the device F 14 would be actuated, which is followed by the second element of the toggle switch F 13, namely by opening a gate, which the gate G511 is equivalent to. The gate G 522 is opened for the switching positions i, 2- or 3 of the device F 14 in the time slots 3, 4 or 5. Here, "o" is saved for time elements 5 to 11.

If the message channel is disconnected from the storage device after all storage contents have been transferred, the relays Bi? and AR in the actuated state, so that the elements 1 of the flip-flop FB and FA are conductive at this point in time.

If the connection is triggered under certain circumstances, the drop in relay RR in FIG. 2 actuates the release by closing contacts rr 1 and rr2, which open gates GM 7 and GM 8 and thus actuate elements 2 of flip-flop circuits FB and FA of the elements 1 of the trigger circuits FB and FA. The relays AR and BR are therefore released and the contact br 1 opens to remove the busy earth from the c-wire of the incoming \ /erbind.ungsleitung.

Three parts of the circuit arrangement have been selected for the description, since these parts are characteristic of the rest of the circuit arrangement. These are the gates G 62, G 63 and G 64 in FIG. 8, which are shown in detail in FIG. 12, and the flip-flop circuit, F8 with the associated circuits, of FIG. 6, which are shown in detail in FIG 13 are shown. Furthermore, the counter C 2 from FIG. 5 is shown in detail in FIG.

The three gates in FIG. 8, which for the purposes of description form part of an extremely complex gate network, are interconnected with the flip-flop circuit Fy- which controls the storage. The gate circuits used are simple rectifier coincidence gates in their basic configuration. In such gate circuits, a common point, which is generally the starting point of the circuits, is connected to a number of control points and to a source providing a positive bias potential. The connection to the voltage source contains a resistor and a connection to the control points, each of which contains a rectifier.

iThe potential of a control point can be two different Assume values, one of which prevents the activation of the gate circuit because it is at or is close to the earth potential, and the other value, which make the gate circuit 'effective can because it represents a positive potential. If, in the cases where many gates are used, the control point on the cathode is one If the cold cathode tube is located, the control potential is at the ineffective value when the tube is not ignited is, and at an effective value on discharge the 'tube.

The rectifiers are connected to pass in the forward direction from the bias source via the Guide rectifier to the control points. Thus, the effect of the rectifiers is to to keep the common point at a potential which is positive in relation to the control points is. The arrangement is made so that if the same positive or: effective potentials are at the same time at all control points of a gate circuit, the potential at the common Point is substantially equal to the potential of the control points. Thus one can see that the common point, d. H. the starting point of the ■ gate circuit, only assumes a positive potential, if positive potentials at the same time. all control points. As it was found is this potential at the common point is equal to the positive, potential of the control points.

The connection of the common. Point of a gate circuit to the next level of the arrangement sometimes includes a rectifier with the forward direction from the common point to next. Stage of the circuit arrangement. Such rectifiers serve as decouplers and are required where the same point in the circuit is controlled via any of several independent gates can be. They serve that one. Don't score a number of .other with this point can make connected gates ineffective.

Coming back to that. Fig. 12 it can be seen that the gate G 64 a. is a simple gate of this type, with two control lines, one from point / 11 and the other from point / 61. These two points lead to tubes F 1.1 and F6.1, which are not shown. When both of these tubes discharge, their cathode potentials are biased positive and rectifiers MR 1 and MR 2 are biased positive. This means that the common point assumes a positive potential which is applied to the grid of the cathode amplifier CFA via the decoupling rectifier MR 3. The grid of this tube is connected to a negative potential via a resistor, so that the tube CFA normally does not conduct. When the gate circuits G 64 or G 62 release an output voltage, the tube CFA becomes conductive, so that a positive potential appears at its cathode.

The second gate G 62 which controls the tube CFA is now considered. Fig. 8 shows

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that there are three control inputs, namely /1.1, /6.2 and /4.3, the last of which is a braking input, ie if the input /4.3 discharges, the gate is ineffective regardless of the status of the other inputs. To achieve this, the input voltage /4.3 is reversed and used for control. The reverse circuit uses a single triode V, the anode of which is connected to ground potential via a rectifier MR 4 and to a positive potential of approximately 60 volts via a resistor R 2. The cathode of the tube V is connected to a resistor branch J? 3, R4 , which is between a negative supply potential and earth. The control grid is connected to a point of the resistor branch R 5, R6 , which lies between a negative supply potential and the control point / 4.3, ie at the cathode of a tube F 4.3, not shown.

The circuit elements are dimensioned so that, when the tube F 4.3 has not ignited, its cathode voltage is at or near the earth potential, so that the tube V is switched off. This means that the anode voltage is determined by the positive source which is supplied via the resistor R 2. In these switching states, the coincidence of control lines / 11 and / 62 causes gate G 62 to release an output pulse. When the tube F4. 3 discharges, its cathode voltage becomes positive, so that the tube V conducts. The rectifier MR 4 then holds the anode potential to earth, which brakes the gate, regardless of the control lines / 1.1 and /6.2.

The resistor R 2 and the rectifier MR 5 can be omitted without the circuit malfunctioning. But the arrangement shown gives better results with the resistor R 2 and the rectifier NR S.

The relatively simple embodiment, which was extracted from FIGS. 7 and 8, gives a picture of how this goal network is actually constructed. The cathode amplifiers are similar to the CFA tube and are used at various points in the circuit to achieve the necessary relationships. However, with regard to FIG. 12, it is not a great difficulty to fully develop the network of FIGS. 7 and 8.

The circuit in Fig. 13 will now be described. The flip-flop, which has two gas-filled cold cathode tubes, is coupled to the capacitor C1 at the anode. The control electrodes are connected via resistors to a source of the bias voltage B , the value of which is lower than the normal supply voltage, e.g. B. 170 volts with a supply voltage of. 350 volts. The bias cannot ignite a tube. When a positive pulse is applied to the control electrode of a non-ignited tube, that tube will discharge. The anode circuit causes a sudden voltage drop at the anode of a freshly ignited tube, which is applied to the anode of the other tube via the coupling capacitor C i and extinguishes the previously ignited tube.

The gate G 120, which is connected to the tube F 8.1, is a simple three-gate gate. The tube .F8.2 is controlled by the gate G 122, which contains two rectifiers which together form a mixer or one-to-one. One input, which ^{can switch the tube i 7} 8.2, comes from TL 24, while the other input comes from gate G 123. The rectifier MR 6 works, as shown, as part of the gate G122 as a decoupler for the gate G 123. The gate G 123 is a three-gate, one input of which is denoted by £ 3. The inputs TS27 to TS 30 are switched during one of these four time slots so that the element pulses are applied to the four rectifiers, which together form a mixing port. A positive potential across any of these inputs biases the rectifier NR 7 so that the gate can operate. The other input circuit belongs to gate G 124, which represents a simple single or mixed gate with two inputs.

The last circuit to be described relates to the counter C 2, which uses the same tubes as the tube F 8. It is assumed that the pulse T 12 has brought the counter C 2 into the switching state , in which the tube C 2.0 discharges. The common feed line to the other tubes runs from the cathode of tube CFB, which will be described later. A coincidence gate of simple construction is located between the successive pairs of tubes. As soon as a positive feed pulse occurs, the rectifiers MR 10 and MR 11 are positively biased. However, at this moment the rectifier MR12 is positively biased because the counter stage C 2.0 is conducting. For this reason the gate MR 12-MR10 gives an output pulse via the capacitor shown, so that the counting stage C 2.1 ignites. The increased current, which runs in the common line across the load resistor R 5, causes an increased voltage drop, which causes the deletion of the counter stage C 2.0. Counting stage C 2.1 is now conductive.

Before the counting stage C 2.1 fired, its cathode potential was at or almost at earth ¹ , so that the capacitor C 5 was discharged. When the counting stage C 2. ι ignites, its cathode potential becomes positive and thus biases the rectifier MR 14. As a result, the capacitor C 5 is charged by a positive potential. This so-called slow-working output acts like a delayed output from counting stage C 2.1.

With the next pulse on the common feed line, both rectifiers MR 13 and Mi? 11 positively biased, whereby the switching stage C 2, S ignites and the switching stage C 2.1 goes out. This switching state lasts until the next pulse T 12 occurs, which brings the counter to its rest position.

The cathode follower tube CFB emits a positive output pulse when its control gate G118 *

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gives a positive impulse to the grid. This Goal. has two simple control lines ί 3 and / 71 and two mixed control gates.

The circuit examples shown give a sufficient idea of the real circuits if one adds the pulse diagrams also shown. However, a few additional remarks are necessary. There are three circuit arrangements made up of three elements, namely F 17, F 4. and F10 in FIGS. 2, 4 and 6, which must be viewed as if they were flip-flops. These circuit arrangements, which represent simple multi-stable registers, could consist of three tubes, the anodes of which are connected by rectifiers, i.e. a three-tube design similar to the arrangement F 8. The multi-stable register F 14 could be a conventional circuit, such as the counter in FIG. 14 , but with more complicated ones

ao gates between the tubes.

The five-stage counter C 3 could consist of gas-filled multi-cathode tubes. This would make a useful arrangement as such a tube can be considered economical.

Claims (5)

PATENT CLAIMS: i. Correction device for storage of message contents in telecommunications, in particular telephone systems, using drums driven at constant speed, which contain one or more magnetizable tracks and recording and playback heads, whereby the messages are stored in binary form in individual element sections of the tracks, characterized in that, that the individual tracks have additional recording heads (correction heads ASH in Fig. 1) which, after incorrect storage has been detected by the control devices (RSB in Fig. 1) and pick-off heads (SH in Fig. 1), carry out a re-storage. 2. Circuit arrangement according to claim 1, characterized in that the individual successive Message contents are alternately stored by pulses of different current directions. 3. Circuit arrangement according to claim 2, characterized in that when in succession two message contents with storage in the same flow direction is a faulty switching is present and thereby the control device is caused, via the additional 55-recording head make a correction storage. 4. Circuit arrangement according to claim 3, characterized in that the memory device works so fast that during the reception 6a Several checks and corrections can be carried out when the content of a message is contained. 5. Circuit arrangement according to claim 4, characterized in that the withdrawal only takes place after the test and, if necessary, a correction storage has ended. In addition 5 sheets of drawings © 609 508/158 4. 56