DEI0008412MA - - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

Registration date: March 19, 1954 Announced on May 3, 1956

GERMAN PATENT OFFICE

The invention relates to a test device for memories, which the message contents absorb and release by changing magnetic states in binary form.

Such storage devices are already in Form of magnetic drums and of ferromagnetic ones arranged according to coordinates or ferroelectric elements became known.

In order to avoid the possibility of incorrect storage due to failure of the According to the invention, a test device is used to avoid power supply or other disturbances provided in such a way that individual successive message contents each by a another magnetic state are characterized, each of which has a control device at its end which only allows the recording to take effect after checking the previous message content of the following. 2c

Due to the high speed of rotation of the magnetic drum used, "for example Dialing pulse of 60 ms duration to be saved several times during the saving process checked so that a subsequent correction 2; or a fault message is possible immediately.

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The arrangement according to the invention eliminates the possibility of incorrect storage without disturbance the storage process itself made practically ineffective.

The details of the invention are explained in more detail with the aid of the figures. Here indicates

Fig. Ι a schematic overview of an arrangement for a storage device having a magnetic drum ,.

Fig. 2 shows one of the news channels as it is for this device is used in conjunction with a number of electronic power gates, each one Are assigned to a channel,

Fig. 3 to 8 the other control devices through which the storage is achieved and through which the impulses are renewed,

9 through 11 are graphs showing the waveforms used in the circuit described to be used,

12 to 14 particular circuit details,

Figs. 15 and 16 show a magnetic network static means,

17 shows a static network with ferroelectric Switching elements.

In the embodiment which will now be described, a magnetic drum or disk is used as an electrical storage device. For example, it consists of one Brass drum, which has a magnetic coating on its cylindrical surface. This coating has a number of closely spaced lanes or tracks, and each a memory and a pick-up head are assigned to each of these tracks. The drum runs on one rotatable shaft, which is driven at high speed by an electric motor.

The message contents are in the form of successive magnetic impressions each of one of two identifying features is stored. These identifying features. are referred to in the familiar way with "o" and "1" or with "distance" and "marking". at The storage of digits is done on the binary system, although other encodings are also possible possible are.

Each lane or track is divided into a number of longitudinal sections. The details of this will be described later. The storage and pick-up heads are arranged separately from each other, so that two separate web sections form a storage section. If a pickup head If one section of a storage path taps off, the corresponding storage head is on the other Effective section of this web. Thus, the stored message content is tapped and stored in saved again in the corresponding section of the path.

In addition to the tracks on which news content is stored, there is a special track provided, which stores each position of the storage elements. To this particular one Bahn is still a pick-up head provided, from

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which one pulse is taken from each message element. The latter web will also referred to as time track and the associated pick-up head as time head. The latter The device is used to generate a set of three closely spaced pulses-per message element to manufacture. Another additional track has the task of steepening the first one To set the message element on each memory section. This path is called the marking path and the pick-up head assigned to it as a marking head. The latter gives a pulse cycle, which determines the beginning of each memory section. These two pulse cycles, namely the timing pulse cycle and the marking pulse cycle are used to control all switching operations used. The device 8c described for storing messages is known in FIG Wise referred to as "memory renewer".

The simplest way of assigning the individual communication channels or lanes to the reminder, consists in assigning a certain path to each storage. However, since the ' Renewers only for receiving and then rebroadcasting message content is used and the latter only takes a short period of time, must be used for the ■ Allocation of the message content on the individual tracks made an appropriate division will. For this reason, the number of intended stores is less than the number of the channels. There are therefore precautions for the temporary allocation of storage to - one channel is necessary if a renewal of the storage is desired.

The memories on a particular path form a group, which is a group of Is assigned to circuits, which is, for example, ten times greater than the number of storages. A single common connection and control circuit is provided, between the storage circuits and the Lanes. In a particular example, a hundred memory circuits can have ten memories be allocated. However, in the interest of simplicity, it is assumed in the following description that the memories of a path are available to each of the ten channels.

In the timing diagrams of FIGS. 9, 10 and 11 it is shown how a section of a path which forms a storage and contains forty-eight elements is used for the assignment of a message channel to a storage and for the storage and renewal of A series of pulses was the result of a series of passes through storage under the pick-up head. The elements sir) denoted by ι to 48, and FIG. 9 shows w these are grouped. These elements are te; wisely used individually and partially in groups,
depending on the purpose for which it is used. If a group of successive element positions are used for the same purpose
this group forms a reservoir

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section. As already mentioned, each element is tapped and stored, either with or without modification, in a specific position in a repeatable cycle of ¹ time slots, whichever

. «5 is determined by the rotation of the drum.

The time pulses generated by the element track are used to control the electrical

gates and are marked with the letter T

f draws. Where an element is part of the in

ίο Fig. 9 forms the groups shown, these letters are followed by a group of elements. The element identification follows the character T alone or in connection with a group identification. For example, the gate Gi6 in FIG. 4 has to carry out the control TL 24, with which a time pulse in the group L and the element 24 is identified.

As already mentioned, the elements of the pulse cycle are also used in a known manner to define three cycles of closely spaced pulses, the pulses being staggered and each being one third of the duration of a pulse element. These closely spaced pulses are denoted by ti, t2 and £ 3, and all of these pulses occur simultaneously within one element.

The above description has made it clear that the elements on a web lie close together and the memories are caused by overprinting an existing memory. If a storage is empty or frel ·, its elements are positively excited, that is, they have "!" Stored. The remaining elements of group R count the revolutions of the drum, which will be described in detail later.

For a better understanding it is pointed out again that each track of the drum has a number Has storage sections and each section consists of forty-eight elements. With the present Arrangement form two such storage tanks -

* Sections of a storage, which with any the news channels can be connected. For the sake of simplicity, it is assumed that ten channels are stored through the storage be served by a train. The control circuits are common to all memories of a track assigned.

A single section of a web will now be considered in particular. The first element a section is used to indicate whether it is free or busy. The next group of Elements is used to identify one of the ^ channels to which the section is available

• stands. This element group contains the label storage. In the present case, elements 2 to 11 are identified by CC 2 to

• CC 1 1 are designated to identify channels 1 to 10.

The control circuit for the railroad has a register with enough stable layers to identify the various channels. Such a register consists essentially of an ordinary electronic counter, the only difference being that it can be stopped in any switching position by assigned control means. It is controlled by impulses from the drum's timeline. These time pulses, which occur regardless of whether there is storage in the element concerned, are denoted by the letter T. The letters identify the element group to which they belong. Therefore, if no channel requires the servicing of a store, pulses TCC 2 through TCC 11 control the register over that pulse cycle. It then remains in the last switch position, namely TCC 11, until the pulse TCC 2 of the next section occurs on this path. At first glance it seems that this could lead to disturbances, but the type of storage which is carried out on the web sections is such that no disturbances occur.

It has already been established that a time slot TCC is assigned to each channel. Each channel can only store during its time slot TCC . During normal operation, ie during scanning by _a: register upon detection of a calling channel, are all the sections on the "o" with the exception of sections 19 and 20 which are designated rig and £ 20th The reasons for this are discussed in the following description.

It is assumed that channel 4 needs storage. The calling channel thus establishes a switching state which causes the scanning process to be stopped in the control circuit and thus in the register in a time slot that is assigned to channel 4, that is, in time slot TCC 5. This initiates the re-storage in the element, which is effective as a marking element. The register remains in the switching position for channel 4, while the section of the occupied memory passes the pick-up and pick-up head.

At the same moment that the scan of the register is stopped, the ringing state in the channel is released. This ensures that the channel does not occupy multiple memories. Passing behind the heads takes place at the switching point PNi in FIG. 9.

It is necessary to ensure that the storage which has been carried out is not carried out by . channels 1 to 3 will be detected on the next pass, d. H. through channels whose timing is ahead the channel for which the section was occupied and marked. Because of this, the already mentioned auxiliary storage head used. He works in a time slot behind the time slots of all channels. This auxiliary head stores a mark in the first element and identifies so that the whole element section is occupied. In the arrangement described, the Auxiliary head effective in time slot Γ31. The vote this timing is arbitrary and is essentially a matter of mechanical design.

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At the end of the cycle (time slot PiV ι) the time slot T 48 switches the entire control circuit to "o" so that it is available for other storage. As already mentioned, the possibility of malfunctions is prevented by the type of storage in the switch position PN1 . These memories indicate that the section is busy and identify the channel for which that section was occupied.

At the beginning of the next pass PiV 2 in FIG. 9, the first element is picked up and stored again as a marking element. Since there are two sections per lane, the second section begins after the drum has made half a revolution. As before, the register begins its cycle, but the TCC 5 marker is tapped and stopped in the fourth switch position, specifically for the channel which was reserved for storage. ¹ Since the register scans with each pass until it reaches the switch position, which is marked as calling ^; thus the assignment is carried out by the calling channel. The mentioned marking is also saved. In this way, the control circuit picks up the stored message content with each pass and accordingly takes care of its switching operations. During the following runs, the markings in switch positions ι and 5 are continuously picked up and stored again. However, these runs are counted in sections 15-19. In pass PN 2 , the marking is saved in switching position 14 and the distances are saved in switching positions 15 to 19. However, the switch position 20 has been saved again. The elements of the switch positions 21 to 47 are stored as distances, and a control mark is recorded in the switch position 48. The time pulse T48 causes a control relay to respond in order to close the previous loop. At switch position T14 of throughput PN 2, the channel was marked as occupied by another relay. In the subsequent runs, namely until the first dialing pulse is received, these switching processes are repeated, ie the markings are picked up in switching positions i, 5, 14, 20 and 48 and stored again. These runs are counted in binary form at switch positions 15 to 19, but this count has no effect. Since these miscounts have no influence whatsoever on other switching functions, it is not necessary to switch them off. The counting is shown in Fig. 10 at PIV3 to PN 5. With each run, the count becomes effective by tapping all stored elements.

It is assumed that the first dialing digit pulses for tap PN 6 are received. During this cycle, the memories in the switching elements 14 to 19 are implemented at intervals. The distances are also stored in switch position 19 and switch positions 21 and 24, 25 to 30 and 31. The reception

the first pulse causes a marking which is stored in the switch position 32, namely in the switch position 1 of the section D ι of the occupied memory web. This means that the first pulses have been received. The switch positions 33 to 47 are newly saved as distances and 48 as markings.

The election impulses are relatively long compared to the individual runs, so that such an impulse survives several such revolutions. The rounds during which the first Impulse occurs will be in the part P. of the track section counted in the switch positions 15 to 19. When the pulse is received and an interruption pulse is too long, this is indicated by a marker, which is stored in switching position 19. This then causes the forced release when it is picked up the circuit arrangement, the track section being brought into its rest position. Therewith the time of an interruption is counted by counting the taps of a storage. If the If the interruption lasts so long that an error can be assumed, the in the switch position 19 was saved by the control circuit as an indicator for forced tripping evaluated. go

In this case, it is assumed that the pulse has a normal length, the counting of the rounds PN 7, PN 8 and PN 9 corresponds to a normal duration and it is determined on the first round PN 10 that the pulse has ended. This causes the storage of a marking in the switch position 14 and a distance in the switch positions 15 to 19. At PN 11, counting starts again at R and lasts until the second dialing pulse is received. This count limits the switching status for the; Channel.

The second selection pulse comes, as is assumed, in the pass PN 12 and is stored in the t part D ι (switch position. 32 to 35). This is done by adding 1 to the digit, because in this case one is already stored in this part. The usual counting of the cycles for the duration of a dialing pulse takes place in the switch positions 15 to 19 during the passes PN 13 to PiV 15. This ends the dialing pulse and initiates the switching processes as previously described.

In the present example it is assumed that the first digit is a 2. Unable to know this, the facility checks the fact that it is detecting the pauses between the pulses. This is done by counting the number of passes between the pulses. The counting takes place in the section P (switching element 15 to 19) during 15p of the passes PN 16 to PiV 20. The pause between the digits is determined when a marking is stored in the switching position 17. During the cycle during which these processes take place, markings in the switch positions 20 and 21 are stored. The tax

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The circuit then assumes a switching state from which the received digit is transmitted can be.

The stored digit is then newly stored in section D ι as its complement, ie all binary elements are reversed. All digit current surges, which are then recorded, are then passed through the control circuit to section D 2 (switch position D 36 to -D 39). After the count, which determines that there is a pause between the digits, the switch positions 15 and 18 are stored again with intervals, but the switch position 19 is held as a marker and remains until the next digit is received. These measures are taken so that no incorrect switching occurs.

When the first pulse of the second digit is received, the distances are saved in section R (switch positions 15 to 19). The receipt of the second digit is the same as the first, except that it is stored in section D 2. The third digit is added to Section D 3, etc.

The pulse is now transmitted over the loop, and since each pulse is sent, ι is added to the digit in section D 1, so that when all elements of section D1 are marked, the digit is completely transmitted. Each renewed impulse begins at the switch position T 48 of a Durclilaufes and lasts four cycles. These passes are counted in a known manner, specifically in section S, ie in switch positions 25 to 30.

When a digit is sent out, its storage in section L, i.e. H. deleted in switch positions 20 to 24.

At the switch position T 48 of the run it begins the renewed pulse, namely on, the path PN21. This interrupts the forward loop and re-stores element 48 as the distance. This is a sign that an impulse has been transmitted. The next digit can be received during the following passes. Your pulses are stored in section D 2 (switch positions 36 to 39),. where, as already known, the section R is counted. During the first run of the renewed pulse, a marking is stored at the switch position 25, the switch positions 26 to 30 being recorded as distances.

In order to save the pulse transmission, a marking is held in the switch position 31, which is designated with SCM . This marking continues as long as the pulse is transmitted and its presence is used to ensure that only one is added to section D 4 for each transmitted pulse. This addition of 1 is done in the usual way, that is, by reversing all elements from section Di up to and including the first distance. During the following iterations, the pulse count continues in section 5 ¹ , with no change occurring other than storage in section D 2 for the second digit. This count is shown in circulations PN 21 to PN 24 in FIG. 11, in which no storage is shown for the second digit.

At the end of the transmitted pulse, the switch position 27 is stored as a distance, and depending on this, the element 31 is also stored as a distance, the element 48 as a marker. The pulse is ended in time segment T48. During the next pass PN 25, the storage in section J? deleted, ie re-saved as distances.

The second pulse is retransmitted in the same way, with a 1 being added to section D ι as before. These measures take place during pass PN 26 to PN 29. During pass PN 28, the auxiliary memory already mentioned is effective to hold a marker in the switch position 12 and thereby indicate that the transmitted pulse is the last. This is true when the circuit determines that all of the markings in section D 1 are in place. During the next run, the element 13 also receives a marking, which is also saved during the run PN 30. The section 6 * indicates that the pulse duration has shifted and this causes the element 48 to be stored as a marker and also to cause the termination of the pulse.

After a digit has been completely transmitted, a pause is inserted between two digits, and the runs during this pause are counted in section S. A pause lasts at least thirty-six runs, and since ^{a 4 was stored as the last digit in section 5 1} , the pause is only ended after section S has counted forty runs.

On the first pass for the pause between the digits, the switch position 31 is considered a Distance referred to. From this to the pass PJV 65, there is another 1 in addition to the count in the Section 6 "is added for each pass.

When. the marking occurred in the switching position 28 during the passage PN 66 , a control device was actuated, and further control devices become effective when a marking is stored in the switching position 30. These together indicate that the correct procedure for this number has been carried out. When pass PiV 66 occurs, element 12 is spaced, and during pass PN 67 , element 13 is also spaced. The same applies to the switch position 20, which indicates that the first digit has been sent, whereas the switch position 21 goes into the marking state. This informs the control device that the next digit to be sent is the second stored digit. This pass clears the count in section S.

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As already described, other digits can be recorded and saved during the pause between the digits. The second digit is now released from storage just like the first, under the control of section D 2.

The forwarding of the received digits to their places on the section is carried out by the Counter in the control circuit by tapping the

ίο Checked the content of the message. A counter causes the received digits to be forwarded to the appropriate sections of the memory path, which switches step by step at the end of each digit. A second counter is used to determine what retransmission can take place and a third counter directs the digits out. These counters are in switch positions. Bracht, which are suitable for storage and work together with the control circuits, under control of the stored message content in the individual sections of the storage path.

At the end of the receipt of the second digit, a marking is stored in switch position 22, and when the second digit is sent, the one previously stored in switch position 21 is saved Mark deleted.

In the same way, markings are embossed on the switch positions 23 and 24 as soon as the third and fourth digits are completely received.

When the switching processes are finished at the end of the further transmission of these digits the markings on switch positions 22 and 23 are deleted.

When the transmission is complete, element 1 is converted to a distance, and when the distance is tapped in time slot Ti it causes element TGC 5 (the identifier for channel 4) to be relocated to a distance. The storage can then be carried out for each of the channels 1 to 3 before the marking in switch position 5 is re-stored as the distance.

From the preceding description it can be seen that the functions of the control circuit play a subordinate role. The message content being sent by the user facility received, d. H. the rush current ranks from a communication channel, which is a storage is to be assigned, and the message indicating the switching status of the consumer device as well as the sequence of the switching operations are recorded in the memory device. the Control circuit handles all storage processes one after the other. When a save starts namely after the passage on the heads, the control device is tapped according to the Information is put into operation and then controls the necessary switching processes. As these switching operations take place, the control circuit initiates new ones Memory information which causes the further sequence of the switching processes. At the end of The control device becomes free and is available for new storage processes.

It is recalled that all time-limiting operations are carried out by a counter with the help of Passes are made on the heads. If the facility has a combined storage and pick-up head as well as the corresponding circuit is required, the time limit is carried out Counting of whole revolutions of the drum carried out.

Before beginning to describe the details of the circuit diagrams, there are some explanations required with regard to the circuits.

The electronic gates, which are known per se, are shown as circles and the controls the same with the help of radial lines, the arrows of which touch the circles. The outputs of this Gates are also shown as radial lines. however, their arrows point outwards. The numbers within the circles indicate the total number of tax organs that must be effective, so that a gate releases an output voltage. If z. B. four control lines are available and the number inside the circle is a 2, then the gate releases an output voltage if two these control lines are effective.

If a short line is drawn across the control line, as is the case with the control line / 43 for the gate G 62 in FIG many of its other control lines are also effective. The excitation of such a control line can lock the door under certain circumstances. The names for all gates begin with the letter G.

The remaining known switching elements used in the arrangement described are electronic trigger circuits with two stable positions, counters and registers with several stable positions Locations.

A counter which contains a number of individual stages, each of which is able to assume one of two switch positions, namely "on" or "down", is shown as a series of rectangles lying next to one another, for example C3 in FIG The counters shown count all to the end of their switching options and are then brought to rest. A register with several stable layers, e.g. B. F 10 in Fig. 6, is shown exactly like a counter, the only difference being that the longer dimension of each rectangle extends in the vertical direction, while the longer dimension of the counters is in the horizontal dimension. A register with several stable positions is essentially structured in the same way as a counter, but it usually does not cycle through all the switching positions. As with the counter, only one switching stage is in operation in a time unit, and depending on the switching status, each stage can operate the next, whereby the

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the previously operated stage enters an ineffective switching state.

An electronic flip-flop with two stable positions is essentially a register with two stable positions. The devices mentioned above, namely the flip-flops, are denoted by the letter F and the counters by the letter C. The individual switch positions of the counters are consecutively designated with i, 2, 3, etc.

If a flip-flop and other output circuits were connected to all of the ports they were to control, it would create an intricate network of wires that is difficult to miss. The lines have therefore been omitted, and short control lines at the gates give the relationship with an f, by which organ these gates are controlled. So z. B. the flip-flop Fn make the line / in or / 112 effective, the last digit 1 or 2 indicates which switch position of the flip-flop the control line in question can be effective.

To make the circuit diagram easier to understand, certain parts of the Circuits are fully illustrated in Figures 12-14. These will be described after Figs. i to 8 are dealt with.

Before with the detailed description Continuing with Figures 2 through 8, a description will be given of the general arrangement given with reference to FIG.

This shows three communication channels, which the incoming connection lines Ti, T2 and T 3 included. These belong to the outgoing lines TOi, TO2 and TO 3. For each channel includes a circuit arrangement, with consideration for the presence of three communication channels the circuit arrangements CCi, CC 2 and CC 3.

An electronic scanning device SCB is assigned to the three connecting channels, which searches for the respective channel which requires pulse renewal. Such a scanning device can of course also scan more than three channels. In the detailed description, one scanning device serves ten channels.

Furthermore, the magnetic drum MD is shown in FIG. From the closely spaced storage lanes of this drum.

five are shown. The first of these tracks MT is the marking track, which, as already described, picks up a marking at the beginning of each storage section of all tracks. The marking track MT is assigned a marking tap head MH , which taps the pulses and controls the counter EC via an amplifier MA , which is described in detail later.

The next path is the element or time path ET, which in every switch position (element)

has a magnetic imprint. The element or time header EH and an amplifier EA are assigned to this path. The output of this amplifier runs on the one hand to an element or time pulse counter EC, which has a number of switching positions which is equal to the number of elements on each track section. On the other hand, the output from the amplifier EA runs to a pulse circuit PF, which generates the pulses 1 1, the width of which is a third of the pulses from EA . The second output from the pulse circuit PF is fed to a delay circuit D ι, which carries out a delay of a third of the pulses from EA and thus generates the pulses i2. The second output from the delay circuit D 1 leads to a further delay circuit D 2, which produces the pulses £ 3 in the same way. The individual outputs of the counter EC send pulses in the individual switch positions.

The output on the marking path is labeled TM and is used to bring the counter EC to its rest position.

The devices associated with a single lane will now be described. These include a storage head SH, a tap head RH and an auxiliary storage head ASH, the purpose of which will be described later. All of these heads are assigned amplifiers, which are not specified. The memory path which is now to be considered is the middle one and is used for those communication channels which are reached via the scanning device SCB . This scanner direction is connected to a device RSB which controls the tapping, storage, insertion and deletion of message contents.

There are also shown schematically other scanning and control devices, namely RSA, SCA, RSC and SCC , which are assigned to other memory lanes.

The devices below the drum MD in Fig. Ι do not require any further explanation, so that the description of the details can now be made. ^:

If no channel requests storage, the devices -F13 and F15 in FIG. 3 have switched their elements 1. At this point in time the gates G 516 and G 517 are blocked, since element 1 of the device F 1 (flip-flop circuit) in Fig. 4, which receives the outputs of the pick-up device, is not switched during the switch positions 1 to 11, since there is no storage it is asked for. The gate 511 in FIG. 3 and the corresponding gates for the other communication channels are also blocked, since the element 3 of the device F ι j is normally connected via br 2, (FIG. 2) and therefore there is no potential on the control line / 172 .

When a web section begins to run past the tapping head, element 1 of toggle switch F 13 is actuated in switch position 1, so that potential is applied via control line / 131 with pulses TCC 2 to TCCn to gates G 501 to G 510 one after the other to open so that the device F 14 operates its elements 1, 2, etc. in succession. The device F 14 has as many switching positions as the message channels

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Storage lane are assigned. As can be seen from Fig. 3, it is assumed that there are ten such channels. Thus, every free storage lends itself to every message channel. The outputs of the device F 14 are applied to the gates GMi to GM 5 of the corresponding communication channels in FIG. 2, but these gates remain closed since the control line / 132 is non-conductive. Likewise, three outputs are applied to the gates, for example G512 and G520 in FIGS. 7 and 8, which are assigned to the flip-flop circuit Fy in FIG. The flip-flop Fy with its element 2 becomes effective for the duration of the selection elements 2 to 11. Gate.512 and the corresponding gates for other channels are opened by the pulses TCC , but gate G 519 is activated by the control line / 132 blocked. However, the gate G 520 and the corresponding gates for the other channels are opened and accordingly the gate G 521 through the control line / 131, so that at the time f 2 for each of the elements 2 to 11, the gate G 99 opens and thus the element 2 of the device F 7 switches so that "o" is stored for the selection elements.

It. it is now assumed that the message channel 4 is put into operation and requires storage for the purpose of pulse renewal. Initially, the device FI7 in Fig. 2 is connected with its element 3, but when the loop is closed off, a positive signal to the gate Gi? 1 placed, which in connection with the control line./173 causes the opening of the gate GRi and thus the element 2 of the device

. F iy switches. The potential applied to the control line / 172 in FIG. 3 causes the opening of the gate 511 in the time slot TCC 5, and since element ι of the flip-flop F 15 is switched, the gates G 515 and G 513 are opened and thus cause the switching of the Element 2 of the flip-flop I ⁷ 13. The element 1 of the flip-flop F13, which is not actuated, blocks the gates G 501 to G 510, so that the device F 14, which has switched its fourth element at this point in time, is in the same position during this Section storage remains. This prevents other communication channels from being switched on before the busy element is stored in the switch position ι. At the time * 3 is via the control line TCC 5 goal GJ? 2 opened in Fig. 2, so that the element 1 of the device Fiy is switched. The signal is removed from the control line / 172 and thus prevents other storages ¹ for this message channel. The potential at the control line / 132 in the switch position TCC .5 causes the opening of the gate G S19 in Fig. 7, .SOWIe the blocking of the gate 521 and as a result of this over time! age TCC 5 and 12 the opening of the gate G 98 and the actuation of the element ι of the toggle switch Fy. This means that “ι” is impressed on element 5 of the memory section. Since the counter F 14 remains switched with its fourth element, the next. Timing TCC 6 goal G the gates G 523 and G 522 opened and _{subsequently%} closing 99th The element 2 of the flip-flop circuit Fy is thus switched. This means that "o" is saved for the remaining selection elements, ie 6 to 11. The storage which was carried out for these switching operations corresponds to the line PNI in FIG. B. G 512, G 520 and G 522 for the individual selection elements. These are denoted by the indices n, n + i, ^_n:; +2 for the timing controls of the three gates shown. It is noted that the time pulse control for the gate group G 522 is one time slot later than the corresponding gates G 520. The remaining gates, which correspond to the gates G 522, are indicated by TCC3 and / 141, TCC4, and / 142 ... as well as controlled by TCC 11 and / 149. This means that when "1" is stored for one of the message channel elements 2 to 11, the following pulse switches the flip-flop circuit F 7 and thus makes element 2 effective. For the case in which 11 is the element for receiving a "1", it is not necessary to switch over the flip-flop Fy and make element 2 effective.

It is assumed that a memory section must be switched as occupied in switch position 1, because otherwise this section, if it is connected to circuit 4, could also be connected to section 1, 2 or 3. It is therefore necessary to change the electrical state of the element 1 after it has been moved past the heads (normal tapping heads). For this purpose, an auxiliary storage device is arranged with respect to the normal storage device in such a way that the element 31 is tapped when the element 1 passes the auxiliary storage device. The switch position 31 has been selected for this purpose for conventional reasons, but any other suitable switch position after the switch position 11 could also be used for this purpose. In switch position 31, potentials are applied to control lines / 132 and / 162, as will be described later, and the potential passes gate G514 (FIG. 3) in order to store the character “1” in switch position 1. As a result of this measure, the storage section is switched as occupied before the section is detected again by the tapping device. A special timing control for gate G 514 determines the switch position of the auxiliary storage device, with T 31 representing a possible switch position. From the switching operations between the toggle switch F16 and the gate G 514 it is clear why the switch position must be later than the twenty-fourth. Element 2 of flip-flop F16 is used for the following reason. When all message contents have been recorded and distributed, the section of memory should be freed. This state is determined by the fact that the elements 20 to 24, which form the group L , are all switched to "o" when the message content has been sent. Until this happens, that will

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Element ι of the toggle switch F is effective for one or more of these switching positions, in this case the dead G518 is opened and the element 2 of the toggle switch F 16 is effective. However, when the message content has been transmitted, element 1 of toggle switch F 1 is locked in the switching , _ ■ positions 20 to 24, and thus element 1 of toggle switch F 16 remains inactive, and gate G 514 is in the switching position 31 closed. As will be shown later, such a measure allows the storage to be released. The MA-

. ', the magnetic state of the track elements 1 to 11 corresponds to the lines PN 2 to PN 3 5 in FIGS. 10, 11 and remains until the passage according to line PN 36 in FIG. 11 occurs.

At the end of this particular memory section, the pulse T 48 is applied to the flip-flops F 15 and F 16 and thus causes the actuation of the elements ι for the test process to the next memory section. The pulse T 1 of the next section reverses the flip-flop F 13 and makes the element 1 conductive.

When element 1 of the section under consideration is tapped again, since it is now magnetized to "1" and element 1 of flip-flop Fi is active, gate G 517 in FIG. 3 is opened by pulse T 1 and element 2 the trigger circuit F 15 switched. Since the element ι of the flip-flop circuit F 15 is no longer effective, the gate G 515 remains closed, so that this storage cannot encroach on other communication channels by actuation of the element 2 of the flip-flop circuit Pi3. If, however, the pulse TCC 5, which corresponds to the connected channel 4, is applied to the gate G 516, the element ι of the flip-flop Fi and the element 2 of the flip-flop F 15 become effective, so that the gates G 516 and G 513 open and the element 2 of the Toggle circuit 513 becomes effective, so that the element 5 retains its memory marker. Element 4 of counter F 14 also becomes effective, and since element 2 of flip-flop F 13 and element 4 of counter F 14 remain effective for the remainder of the section storage, gates GMi to GM 5 in FIG. 2 are prepared so that the storage of the message elements can take place, as will be described later. The elements ι and 5 have of course been saved as "1" anew, as previously described, and are retained for the further cyclical switching processes.

Thus, the next time it is run through, the switching

■ state that as shown in the line PN 2 in FIG. Element 2 of flip-flop Fi5 switches via gate G517 in time slot Ti, since the occupied state is marked in element 1. It has already been emphasized that the element 2 of the flip-flop F 13 is actuated by TCC 5 and that the switching element 4 of the counter .F14 is also switched. As a result, potential on line 5TL causes gate GMi to open. Here, potential is applied via line LP ι to dead G 4 (Fig. 4), which opens as soon as the time T 14 occurs. According to the same approach, three out of four control lines are effective for the GM 2 gates. Since gate GMi is open, potential is applied to element 1 of flip-flop F 2 via gates G 4 and G 5. As a result, potential is applied to lines / 21, so that gate G 54 in FIG. 7 opens in the same time segment, which is followed by dead G 98 in switching position t2 of T 14. Furthermore, the element 1 of the flip-flop circuit Fj responds in order to give a positive sign to the drum in the switching position 14, as can be seen from the characteristic curves PN 2 in FIGS.

The toggle switch F 1 in FIG. 4 follows the magnetic switching states on the drum track, namely element 1 for the positive state or "ι" and element 2 for the negative state or "o". In the time segment T 14, the element 2 of the flip-flop F 1 was actuated, and as a result, the gate G 12 is also opened by the control lines / 12 and / 21. This is followed by the gate Gn, so that the element 2 of the flip-flop F 5 switches.

When the group of time slots TR (Ti? 15 to TR ig) begins, the gate G61 in FIG. 8 opens. This is followed by the opening of gate G 99 at i2 of the element 15, so that the element 2 of the flip-flop Fy becomes active again is, whereby a distance for the first and all subsequent switch positions of the time slot R is stored. Thereafter, any positive storage that was in effect in section R is deleted when the storage in question becomes free, as described later.

The element 1 of the flip-flop F ι is actuated when the elements Ä19 and L 20 are tapped, since these two elements are normally positive. In the time segment TL 20, the gate G 112 in FIG. 5 opens as a result of the potential. the control line / 11, and the element 1 of the counter Ci speaks. on. While the counter C 1 assumes the switch position 1 in the time segment TL20, the gate G 74 opens and then the gate G 73, since the device F10 in FIG. 6 normally assumes the switch position 1. The gate G 98 therefore opens in the position i-2 of the time segment T 20, and the element r of the device Fy responds in order to store positive or to identify the element 20.

At the beginning of the time segment TL 21, the switching state of the web changes to distance, and therefore the element 2 of the flip-flop circuit Fi responds, so that there is no longer potential on the common control line to the gates G 112 ... which control the device C 1 so that it remains in switch position 1. The gate G 91 in Fig. 8 opens, and in connection with the time period TL 2 1 opens the gate G 95, so that in the position t2 the gate G 99 opens and thus causes element 2 of the toggle circuit Fy to respond and the storage head registered a distance. No other switching functions occur until switching position T 48 is reached.

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Coming back to the news channel in

"Fig. 2, as soon as the switch position T48 is reached and with regard to the toggle switch F8 in Fig. 6, which normally occupies the switch position 2, the gate GL 2 and then GM 5 opens so that the element 1 of the toggle switch FA opens, whereupon the relay AR responds, so that the contact closes the outgoing loop.

The relay BR would be actuated in the time slot T14 in which the gate GLi with the element 1 of the toggle switch Frj \ had opened. Closing contact br 1 kept the repeater as busy. · ■ '■ << ■■

Also in the time slot T 48 and depending on the toggle switch F.8, which is in the switch position 2_, and the counter F 4, which is in the switch position 3. ^ opens the gate G87 in Fig.7, which the gate G 98 follows, so that element 1 of flip-flop F 7 becomes effective and thus positive storage takes place for switch position 48. Up to the first dialing pulse that was picked up by the repeater, successive passes of the section under consideration have passed the tapping head, which causes the same sequence of switching functions as before, the only difference being that these passes are counted at section R. This count has no meaning at this moment, but it is used for timing purposes and takes place in the pauses between the pulses to sample the periods between the digits. Before the switching operations are described further, the timer will first be discussed. When -PiV 3 is run, nothing happens in time slots T 12, but rather in T 13. Element ο of counter Ci in FIG. 5 is actuated. It can be seen from this that the time slot T13 always wants to bring the counter C 1 into position ο. The positive storage in element 14 is tapped and stored again. As before, element 1 of flip-flop F 2. in FIG. 4 becomes effective in time slot T 14. This causes the opening of the gate Gg , because the element 1 of the toggle switch F ι is actuated, so that the gate G 8 opens and the element 1 of the toggle switch F 5 becomes effective. ■ '■

At the time slot Ti? 15 opens the door G 14 in FIG. 4, and the element 2 of the toggle switch F 6 switches, and in connection with the element 2 of the toggle switch Fi the gate G 57 in FIG. 7 opens because there is no marking in the switch position 15 was saved. At the same time, the gate G 56 in Fig. 7 has opened under the control of the control line / 51 and TR , so that the gate G 60 opens and in the time position Ti? 15 and * 2 the gate G 98 opens and the element 1 of the flip-flop F 7 opens in order to save a marker in the time slot 15.

In the section Ti? 15 and £ 3 and depending on

that the elements 2 of the flip-flop circuit Fi and F 6 have switched, the gate G 15, which is followed by the gate G 3, opens, so that the element 1 of the flip-flop circuit F6 switches again. In the time slot TR 16, the element 2 of the flip-flop F 2 is still actuated, so that the gate G 64 opens in FIG. 8, which is followed by the gate G 63. In addition, the gate G 99 has opened in f2, so that the element 2 of the toggle switch F γ responds and stores a distance in the switch position 16. In the other switching positions i? and depending on the element 2 of the flip-flop F1 opens the gate G 64 in Fig. 8 and not the gate 'G 59 in Fig. 7, so that the element 2 of the flip-flop F 7 remains actuated and the distance storage over the entire section i? is continued.

With each subsequent run, the memories are made in the switch positions i? Changed up to the first spacer. This change adds a 1 to the binary character already mentioned in the i? is stored. If one considers z. B. the case when the switching position 15 and no other contains a positive storage after the passage PN 3, as just described. As before, the element 2 of the flip-flop circuit F 6 responds via the gate G 14 in the time segment TR 15, but since the element ι of the flip-flop circuit Fi is effective, the gate G62 in Fig..8 opens in place of this gate G 57. The Gate G 62 can open because element 3 of device F4 in FIG. 4 is not actuated. : The gates G 63 and G 99 open, and the element 2 of the toggle circuit Fj switches through in order to store the distance for the time slot 15 in place of the marking which was previously stamped there. Since element 1 of toggle switch F1 is actuated, gate G 15 in FIG. 4 cannot open, and element 2 of toggle switch F 6 remains actuated.

In the time slot TR 16, the element 2 of the flip-flop F 1 is actuated, and with the switched element 2 of the flip-flop F 6 opens the gate G 57 in FIG. 7. The gate G 56 is also open, because of the element 1 of Toggle circuit F 5 in Fig. 4, so that the gates G 60 and G 98 are open and the element 1 of the toggle circuit Fy responds to store a marker in the position .16. The element 2 in the flip-flop F ι is open during the period TR 16, so that at i3 the gates G15 and G 3 open in order to open the element 1 of the flip-flop F 6 in FIG. This leads to storage during the time period Ti? 17, which in this case means the switching condition for the distance, depending on the opening of the gates G 64, G 63 and G 99. You can see that the toggle switch F6 the first distance between the switching positions in group i? scans. When element 2 of flip-flop F6 'is actuated, the reverse of what was tapped is stored. When the element .1 of the flip-flop F6 responds again, the switch positions are saved as they were tapped. This results in adding ι to the binary character that is used in the time slots i? was saved with each run. The counting of the free revolutions is shown in FIG. 10 by the lines FiV 3 to PN 5. During the passage PN 3, contact ar 2 in FIG. 2 places the control line LP 2 via the gate GM 2 to the gate G 16 in FIG. 4, which is therefore in the

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Time slot TL 24 opens and thus cause the actuation of the element 1 of the flip-flop F 2 zn. However, this measure has no immediate purpose.

When the first digit pulse was received, which consists in opening the loop on wires a, b , this has a change in the

> Potential on the line 5TL and thus a closing of the gate GMi. The gate G 4 As a consequence, in the timing of T14 (at the next pass, in Fig. 4 does not open, and the element 2 of the flip-flop F 2 remains actuated. It is necessary to clear the storage in the timings of R, namely from the time

section of the occupancy up to the first impulse. For this reason, the stored in the element 14 must Marking can also be deleted.

As soon as the time segment T14 is reached, the element 1 of the flip-flop circuit F1 responds. Dijes has no immediate effect, but the control line / 11 in connection with the control line / 22 opens the gates G 10 and G 11 and also actuates element 2 of the flip-flop circuit F 5. The control line / 22 in connection with the Time slot T 14 opens the Tor.G SS in FIG. 8 and at 1 2 the gate G99 in order to carry out a distance storage for the element 14.

At the beginning of the time segment TR 15, the gate G 61 in FIG. 8 opens the gate G 99 depending on the control line / 52, so that the toggle switch F 7 continues the distance storage. The flip-flop Fy remains for the other elements R in this position.

Element 1 of flip-flop circuit F 1 in FIG. 4 responds in time slot TL20. The counter C 1 in FIG. 5 is brought to the rest position in the time segment T 13, as previously described. Gate G112 is now open and element 1 of counter C 1 is switched through. The control lines Cn and TL 20 open the gate G 74 in FIG. 7. The element 1 of the toggle switch F 1 is actuated by the marker memory in the element 20. The: control lines fii, TL20, / 103 open the gate 108 to to operate the element 1 of the flip-flop circuit Fio in FIG. As a result, the control line / 101 opens the gate G 73, since the gate G 74 is open. In the time slot TL 20 and £ 2, the gate G 98 opens and the element 1 of the flip-flop Fy responds in order to store a marking in the element 20.

Via the control line TL 21 in connection with the counter C 1 in the switching position 1, the gate G 91 opens in FIG. 8 and the gate G 95 with the control line TL opens the gate G 99

and also the actuation of the element 2 of the flip-flop circuit Fy. The distance storage is continued over the time slots TL 21 to TL 24, section S ^- and time slot T 31,.

It is necessary to store a marking in the switch position 32 of the section D1 in order to record the received pulse.

It can be seen from this that the elements 1 and 2 of the device F 4 in FIG. 4 are controlled by the control lines / 11, Γ14 and T 13, respectively. This means that during the previous runs with a marker stored in element 14, the device F 4 from element 1 to element 2 and. switched back during each run. In the control line T14 of the present run, element 1 of device F 4 has responded again because a marking was tapped and element 1 of flip-flop F1 is switched.

In the previous runs with potential at LP1 , element 1 of flip-flop circuit i ⁷ 2 is actuated during section T 14, and gate Gg is opened in connection with element ι of flip-flop circuit F 1. This period of time, but without potential at LP 1 due to pulse interruption. at the loop α, 6 in Fig. 2, causes permanent actuation of the element 2 of the flip-flop F 2 and, in conjunction with the control line / 11, opens the gate G 10, which is followed by the gate Gn, by ^1, the element 2 of the flip-flop Press F 5. When TD 32 is reached and when the counter C 1 assumes the stop position 1, the Toc G 18 opens and continues to open in connection with the. Control lines / 41 and / 52 gate G 22, so that gate G 14 opens in time slot T 1 and element 2 of toggle switch F6 becomes effective. The control lines fi2 and / 62 open the gate G86 in FIG. 7; so that the gates G 85 (from TD 32 to TD 35, ie TDi to TD 4) and G98 open alternately. The element ι of the flip-flop .F 7 responds in order to store the marking in the element 32. The first element of group D1 is used to store the first digit.

In the time interval 32 and £ 3 potential from element 2 of flip-flop F 6 opens gate G15 and then gate G 3, so that element 1 of flip-flop F 6 is actuated. As a result, the remaining spacer elements 33 to 47 are tapped and stored again, via the control lines / 6r, f 12 and gate G82inFig. 8th..

In the time slot Γ 48 a marker is tapped, so that the element 1 of the flip-flop F ι becomes effective .. It is desirable to hold a memory marker in the element 48 until it is necessary to transmit the stored pulses again. This is controlled by the flip-flop circuit F 8 in FIG. 6, which has actuated its element 2 at the moment. As a result, the gate G 87 opens, which is followed by the gate G 98, whereupon a positive storage in element 48 is carried out.

The next function of the control circuit is to tap the end of the first dialing pulse, which is stored, and to measure the duration of the pulse. When the pulse is tapped, the flow counter for subsection R is brought to the rest position. On the next and subsequent sweeps during which the pulse is present, will

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"I" is added to the binary character which is stored in subsection R in the same way as described above for the state after the seizure before the first pulse 'was received. If the interruption of the loop a, b in Fig. 2 exists until the last, binary storage element R ig is marked, a forced triggering takes place during the next cycle by actuating the third element of the device F 4. This occurs because the second element of the flip-flop F 1 has responded in section T 19, and the gate G 28 in FIG. 4 is actuated by the control line / 62 during the time slot Ti? 19. Element 3 of device F 4 then takes effect. There is now instead of a check whether all the flip-flops are returned to the home position, and whether the message channel of the device I ⁷ 4 iist released by actuation of the element. 3

These operations are not detailed described. - -

It is assumed that the first dial pulse ends within a normal period, so that the potential at LP 1 appears again.

· · The runs PN 7, PN 8 and PN 9 mark the counting of the runs for measuring the duration of the first pulse, while PN 10 shows what occurs after the potential at LP 1 reappears. In the time segment Γ14, the gates G 4 and G 5 open alternately in FIG. 4 in order to actuate the element 1 of the flip-flop circuit F 2. The element 2 of flip-flop F1 is pressed during the time period T 14, .so that the gates Gi2 and Gn alternately open to the element 2 to open the flip-flop F .5. Also in the time segment T 14, the gate G 54 in FIG. 7 opens, to which the gate G 98 and the element 1 of the flip-flop circuit FIG. follow, so that a positive storage in element 14 is carried out. The elements R must be brought into the negative switching state: This is determined by opening the gate G6t in FIG. 8, depending on the actuation of the element 2. of the tilting posture F 5. In the next pass PN 11, the counting starts again in the subsection R and continues like this during the following passes long until the next impulse appears.

The storage of the second pulse takes place during the pass PN12 , and. by a series of switching operations that are essentially the same as those used to store the first pulse during the cycle

'PN 6 were used. The only difference is that in the oil subsection in Fig. 9 a "1" is added to a "1" instead of an "o". .

It is assumed that the first digit is a 2 and that this digit is now fully incorporated would. However, the device cannot know this, and it must therefore know the switching state by determining the deviation time, since the last dialing pulse - by counting the Runs recorded and the last pulse recorded and a mark in the element L 21 was inserted.

A pause between the digits is scanned if a marking was inserted in the element RiJ during the counting process. While still in section TR 17 but after element r. of the flip-flop .F 7 has been actuated, the gate G102 opens in the time segment TR ij, which is followed by the gate G104, and the element 1 of the flip-flop F 9 switches. In order to receive the next digit, the counter C 1 must be switched to the second step, and in order to prepare the counting of the first digit, the storage in section R 1 must be converted into the complement of the binary digits, which is achieved by converting each of the elements of section D 1 takes place. '

The element 1 of the flip-flop F 6 is operated and the following elements R are stored. In the time period TL 20.-switches the element 1 of the flip-flop ^{circuit J 7} I, -so that the gate G112 in Fig. 5 opens, which causes the actuation of the first element of the counter C ι . The gate G 108 in Fig. 6 also opens, with regard to the control lines TL 20, / 11, / 103, so that the first element of the device F 10 is actuated. Then the gate G 74 in FIG. 7 opens, which is followed by the gates G 73 and G 98, so that the marking is stored in the element 20.

Through the control lines TL 20 and £ 3, the device C 2 in FIG. 5 being at step o, and with the actuated element 1 of the toggle switch Fj the first switching position of the device C 2 becomes effective. Through the control line. · TL 21 and with respect to the operated first operating position of the counter C1, the gate G137 5 opens in Fig., Which follow the gates G136 and Gi 10th This causes the counter C 1 to switch to the second step, and at the same time the gate G103 opens, which actuates the second element of the toggle circuit Fg , whereby the gate Gi 10 is closed. The control lines TL2i and C12 open the gate G 75 in FIG. 7 which, together with the control line / iord, opens the gate G 73.

The last-mentioned gate in connection with the control line 1 2 opens the gate. G 98 in order to actuate the EIe- ment ι of the toggle switch FJ and thus to store a marking in the switch position L 21. The device C 2 switches to the element 6 "via the control lines TL 21 and £ 3. This indicates that the first digit has been completely recorded and that this digit can be transmitted to the outgoing loop of the connection.

No switching operations take place up to the time segment TD 32. The complementary storage of the digits is controlled by the gates G 71, G 86, G 81, G 83 and the associated auxiliary store. It should be noted that the gate G 86, which controls the first element of the flip-flop FJ , is itself switched by the second element of the flip-flop F 1.

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is switched, whereas the gate G 83, which controls the actuation of the second element of the toggle switch F 7 , is made effective even by the first element of the toggle switch F ι. The storage is thus reversed in each element of the section D ι. The sequence of the inversion of the digit is controlled by the auxiliary gates. The control lines TD determine which digit is reversed, while the counter C 1 determines that only one digit in a time unit is converted in the correct sequence. Gate G 71 decides in which periods of the entire holding processes these conversions can take place, while gate G 86 controls the inversion of the elements. The first element of the tilting. Circuit F 11 in Fig. 6 was actuated by the control line TL 20 through the first element of the flip-flop Fg via the gate G 109.

It can be seen from this that under the current switching circumstances the gates G65, G 71 and G 69, G 81 remain open during the entire section D ι, whereas the gates G 86 and G 83 open alternately, with consideration for the existing Speidherungen in the EIemen th of section D 1, in which distance and marking are embossed. This causes the reverse restoring. In the following runs, a coincidence occurs between TD1 (TD 32) and the second element of the counter C 1 before the next digit is received. In this case, however, the first element of the flip-flop Fn is not actuated because the first element of the flip-flop Fg did not switch in the period TL 20 (see gate G109) because TR 15 ensures that the second element of the flip-flop Fg switches. The gate G 102 is not opened by TR 17 for most of the following passes because the second element of the toggle switch F 6 is not actuated. During the remainder of the time counting through the section R one obtains the switching state that the elements R 15 and 7? 16 contain both markings and section R 17 represents a distance, but only if sections R 18 and 7? 19 are there. If at the end of the complete count all the elements R denote spaces, then the elements R 15 and i? I6 signify markings and the elements R 17, R 18 and i? I9 signify spaces. In order to prevent the element Rig from containing a marker at the end of the count, the system waits until the next interruption of the voice line occurs.

The element R 18 or R19 opens the gate G 101 as a marker in order to actuate the element 2 of the toggle switch F 9 and also to leave the element 1 unactuated, so that the gate G 109 does not open at a point in time TL 20.

After the complete count in section R are the elements- ?? 15 and 7? I8 negative on the next run, because element 2 of the flip-flop! ⁷ 6 is not actuated in the time segment TR 15. However, if the period Ti? 19 is reached, the gate G 150 in Fig. 4 is opened in order to switch the element ι of the flip-flop F 6. As a result 'of this, the element 1 of the flip-flop F 7 is actuated to in the element i? 19 to save a marker again. When the speech loop is interrupted, element 2 of flip-flop F 2. in FIG. 4 remains actuated, and since element T 14 had marked the loop state, Tore.Gio and Gn open in order to actuate element 2 of flip-flop F 5 . As a consequence of this, the gate G 56 in FIG. 7 remains closed during the time segment TR , and the gate G 61 in FIG. 8 opens in order to cause the storage of a distance in the time segment TR.

It can be seen from this that when pulses are transmitted and by adding ι to the binary characters in section D 1, the first digit is completely transmitted for each transmitted pulse if all elements of section D 1 contain markings.

Each pulse is started during the last element position of a run and is maintained for four runs, which are counted ^{by section .S 1.} As each digit is sent out, its storage in section L is removed.

The transmission of the first pulse is initiated by converting element 48 from a marker to a distance. As previously explained, the element 6 * of the counter C 2 becomes effective during the passage and, as a result, the gate G120 in FIG. 6 is opened in the time slots TS 27 and ii, so that the element 1 of the toggle circuit F 8 is actuated. Thus, in time segment T 48, gate G 88 in FIG. 8 is opened by control line / 81, as a result of which a distance is stored in element 48 ¹ . The same control combination T 48 / / 81 opens gate GL 3 in FIG. 2. As a result, potential is applied to gate GM 6. It will be recalled that the counter F 14 in FIG. 3 causes the identification of the message channel in FIG. 2 to be stored. At the moment the counter F 14 is in the switch position 4 and thus applies potential to the gate GM 6. Furthermore, the elements 2 of the flip-flop circuits F13 and F 15 are still actuated, so that the gate GM 6 opens. This is followed by the gate GM 8 in order to actuate the element 2 of the tilting posture FA , which switches off the relay AR in order to initiate a pulse transmission with contact ar 1.

In the following passes, further digit pulses can be received and stored in the same way as previously described, with the only difference that the next digit is stored in section D 2, etc. Attention is now paid to the pulse transmission, which is initiated in the stop position 48, line PiV 20 in FIG. The following runs are shown graphically in Figure n. The counting processes in the lines PN 21. . . for the section i? are skipped, so that the first switching operation we are considering is the counting operation of the first cycle of section 5 ". The dropout from relay AR opens

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the contact ar 2 and thus removes minus potentials from the line LP 2 in Fig. 2. The element ι of the flip-flop circuit F2 in Fig. 4 can be operated by the line LP ι in the SehaltsteHung T 14 via the gate G4; but in any case element 2 of flip-flop F 2 is actuated again during time segment TR. By removing the potential from line LP 2 , gate G 16 does not open in section TL 24, so that Element.2 of flip-flop F 2 remains actuated and gate G 58 in FIG. 7 opens in time section TS. The element 2 of flip-flop F1 is conductive, because the group of elements positions S "is empty, ie, that all the elements are identified as distances. It was also by the potentials 25 and TS / 22 goal G.17 in Fig. 4 and with The gate G 14 is opened in order to actuate the element 2 of the toggle switch F 6. As a result, the gate G 57 opens in FIG the time potential i2 and G 98 the element ι of the flip-flop F 7 becomes effective and thereby a marking is stored in the element> S 25. With the time potentials £ 3 and / 12, the gate G15 in FIG Toggle switch F 6 responds again and thus prevents storage of the markings in the ■ element positions 26 to 30 ... These time elements mark a distance so that the time potentials an / 12 and f6i open gates G 64 and G 63 in FIG. So that the element 2 of the flip-flop F 7 responds to the Absta Register ndsspeidherung for these elements today.

It is necessary to store the fact that a pulse has been sent out so that after a pulse has been added in section D 1 during the current cycle no further pulses are added in section D 1 until the transmission of the first pulse has been completed and the Transmission of the second pulse has started. This storage is carried out in element 31 between sections 5 "and Di.

The time pulse combination TS and / 22 has actuated the element ι of the flip-flop F 12 in Fig. 6 via the gate G125, so that the gate G 89 open via the time potentials T 31, / 121 and / 22 and thus via ί 2, the gate G 98 the element 1 of the flip-flop F.γ is actuated in order to cause a marking to be stored in element 31. A pulse has now been added in section D 1.

In the time slot TD 32 and in the position 1 of the counter, the gate G 23 opens in Fig. 4, and in connection with the time potential / 121 (Fig. 6) the gate G 27 opens, so that with 1 1 and TD 32 the Gate G 14 opens and the second element of the toggle switch F 6 is opened. It is now necessary to change every element of section D 1 including the first spacing. When the element 32 has stored a distance, the element 2 of the toggle circuit Fi is actuated, and with the switched element 2 of the toggle circuit F 6, the dead G 86, which is followed by the gates G 85 and G 98, opens the element 1 of the toggle circuit Press Fy to save a marking. Due to the time potentials TD 32 and ii, the element 2 of the flip-flop circuit F 6 sprays on again because the element 32 was tapped as a distance. This prevents any further changes in the re-storage of the elements TD 1. In a special case, which is shown in the line PN 21 in Fig. Ί ι, the element 32 contains a marking and was' relocated to a distance by opening the gate G 83 in FIG. This was done through the potentials / 11 and / 62, which acted on goals G 98 and G 99. The element 2 of the toggle switch F 6 remains actuated, so d'a-ß the element 33, in which a distance is stored, has been converted into a marking with the help of the gate G 86, as already described. The element ι of the flip-flop F 6 is now actuated in order to prevent the reversal, so that the elements 34 and 35, in which markings are already embossed, receive new memories through the gate G 24.

The remaining elements 36 to 48 are stored again as they were tapped, with a view to the possibility of the digit storage in section D 2 being carried out further.

In each of the next three passes, a pulse is added to the group of element position 5 ", but there is no change either in element 31 or in section D 1 because the transmission of the first pulse still takes place.

On the line PN 22 in FIG. 11, when the section S is reached, the element 1 of the flip-flop Fi responds, specifically in the time element 25. The element 2 of the flip-flop F 2 has when it is in the time position Ti? was necessary, addressed again, so that in the time slot T.S25 the gates G 17 and G14 open and the element 2 of the toggle switch F 6 actuate. Gate G 62 opens via the S expensive lines / 62 and / 11, which is followed by gate G 63. and the element 2 of the flip-flop F 7 responds to store a distance. The element 2 of the flip-flop circuit F 6 remains actuated, so that in the timing element 26 when element 2 of the flip-flop circuit Fi is actuated, the gate G57 in FIG. 7 opens and in connection with the gate G 58, which was opened by the control lines TS and / 22 , the gate G 6 opened to cause the element 1 of the flip-flop F 7 to store a marker. The element 1 of the flip-flop circuit F 6 sprays over £ 3 via the gates G15 and G 3 again, and the remaining elements of the section 5 * are newly saved as they were tapped.

During the passage PN 21 (FIG. 11), the element 1 of the flip-flop circuit Fi2 in FIG. 6 was actuated, specifically by the control potentials HaIeTiT and / 22. Element 1 of the flip-flop circuit

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P 12 'remains addressed via element 31, which is referred to as element SCM , and beyond that up to section D 1. During the passage according to line PN 22, element 2 of flip-flop circuit P12 is actuated in time segment Γ31, since element 31 was tapped as a marker and the potential is applied to the control line / 11, so that the gate G 126 opens.

Likewise, in the time slot T 31, the gate G 89 in FIG. 7 has opened by the control potentials / 11 and / 22, so that the element 31 is again stored as a marker. Since element 2 of toggle circuit Fi 2 is actuated, gate G 27 in FIG. 4 cannot be opened and element 1 of toggle circuit F 6 remains actuated. As a result, gates G 84 and G 82 store in the section Di the elements as they were tapped.

On the PN24 line. turn a total of four pulses added so that the time element 27 is given a mark. Via the time potentials T 27 and 1 1 in connection with the element 5 * of the counter C 2, which is still activated, the gate G 120 in Fig. 6 opens in order to activate the element 1 of the toggle circuit F 8 , as before. However, due to the time potentials T5 "27. and £ 3 and with regard to the element ι dier flip-flop Fy, which is operated to store a marker, the gate G124, which the gates G 123 and G122 follow, so that the element 2, the flip-flop F 8 is operated again ,. the element 2 of flip-flop F6 in Fig. 4 is not actuated during this run, so that the time elements are stored to 47 so again 28 as they were picked up. However, opens at the timing T 48 and, as a result of the actuated second element of the toggle circuit -F 8, the gate G 8.7, and a marking is stored in the timing element 48. The control potentialsc / 82 and T 48 also open the gate GL 2 in FIG GM 5 opens to excite the multivibrator FA with its first element and the relay AR, so that the contact includes ar 1, to determine the first pulse. in addition, the contact is ar closed 2, which voltage to the line GM 2 lays which the P otential on the line LP 2 replaced.

During the passage of PN 25, the first element of the flip-flop F 2 is actuated in the time slot TL 24 because the line LP 2 opens the gates G16 and G 5. The gate G17 in Fig. 4 is therefore blocked in the time slot TS25 , and the element ι of the flip-flop F6 'remains actuated. It is now necessary to delete the stored markings in time slots 5 "and T 31. The first element 5" in time slot 25 is a distance, since the digit 4 is stored in time slot S, and consequently gate G is also 64 in Fig. 8 by the control potentials / 61 and: / 12 opened. Then the two gates G 63 and G 99 come, and the second element of the toggle switch Fy is actuated in order to re-store the distance. Since the first element of the flip-flop F2 is active, the gates G 57, G 58 and G 59 and G 89, which control element 1 of the Kippso hold Fy for the time slots S and Γ 31, cannot operate the first element of the flip-flop Fy, and a distance storage is therefore carried out ^{over time slot 5 1} for time slot T 31. During the time slot TD 1, the first element of the flip-flop circuit F 6 remains actuated because the element 2 of the flip-flop circuit Fi 2 is still actuated and for this reason the gate G 27 in FIG. 4 cannot open. The gates G 84 and G 82 now control the restoring of the elements of the section Di as they were tapped, since the control potential / 11 opens the gate G 84 to open the first element of the flip-flop Fy . The control potential / 12 opens the gate G 82 in order to operate the second element of the flip-flop Fy. The time slot element 48 is stored again as a marker via the gate G 87, and the relay AR remains activated.

Track PN 26 is used to remove the second pulse by removing the stored marker in timing element 48, as was done previously with track PN 20 . In the time slots TS 27 and 11 , the element 1 of the flip-flop circuit F 8 in FIG. 6 is actuated ^{by appropriate control potentials, as before, and 1} it also remains actuated, since neither the control potentials fyi nor / 11 are effective in the time slots TS 2y and i3 are so that the Tore.G 124, G 123, G 122 remain blocked. When the time slot element 48 is reached, the dead G 88 in FIG. 8 opens as a result of the control potentials / 81 and T48, so that a gap storage takes place with element 2 of the flip-flop Fy.

Furthermore, the control potentials / 81 and Γ 48 open the gates GL 3, GM 6 and GM 8 in order to operate the element 2 of the flip-flop FA and thus throw off the relay AR. As a result, the second impulse is initiated by opening the contact, ar 1. As usual, the pulse is retained over the next four runs, namely, in the tracks PN 26 to PiV 29. The processes described for the first pulse occur, only with the difference that the section D ι an additional pulse receives which completely fills the section, ie it leaves this section fully marked, whereby it is determined that the transmitted pulse is the last one for the digit. Accordingly, the timing elements 12 and 13 are converted into a marker. In the track PiV 27, the section D ι is completely filled. Consequently, at the timing TD 1, although the gate G129 in Fig.'S track PJV 28 5 is opened by the control potentials TDi and C 31, the gate G128 is not opened because the control potential fi2 is not effective, so that the element 1 of the Toggle switch Fg remains activated. In the time slot T 48, the gate G 127 in FIG. 6 is opened by controlling the potential / 91 and actuates the element 1 of the flip-flop circuit F 23.

The auxiliary memory registers a marking in the time slot element 12, as it was earlier for element 1

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described in the track PiV ι. The toggle switch P 23 is reset to element 2, which was actuated by control potential i3.

During rotation PiV29, gate G ι in FIG. 4 is actuated in time slot Ti2 by element 1 of flip-flop circuit F 1, which opens and element 1 of flip-flop circuit F 3 switches on. In the time slot or in the element T 13, the gate G 51 in FIG. 7 opens as a result of the control potentials / 31 and T 13, whereby a marking is stored in the element 13. As before, gate G127 opens in time slot T 48 when control line / 93 is active. This causes the auxiliary memory to insert a marker in time element T 12.

During the rotation PiV 30, the tapping of the marking in the time element 12 causes the element 13 to pick up a marking again, and the auxiliary memory stamps a marking in the time element P12 at the required moment. Meanwhile, the count has stored 6 "the fourth pass for the pulse 2, so that the member 27 is a mark such as obtained. In which circulation PN 24 is in the element 48 again, a mark has been made, so that the relay AR in Fig. 2 has tightened to end the regenerated second pulse and with it the first digit.

It is now necessary to take a break between the

To measure digits, which is formed by a group of the timing elements S.

As it is apparent from Fig. 11, is the inclusion of the second digit of the message channel in Fig. 2 not yet been initiated, and the traces PN 21 to PN 30 show the timing element R, which for counting of passes until the reception of the second digit is used. Section 7? counts more than once if the second digit is delayed for inclusion. The reception of the second digit has been omitted in FIG. 9 in order not to make the diagram unnecessarily complicated. However, it is believed that the inclusion of the. second digit is carried out with the similar switching functions, as shown in tracks PN 6 to PN 20.

The smallest pause between two digits comprises thirty-six runs after the stored marking of the first digit in the element curve L is deleted, ie is newly stored as a permanent interval in order to enable the second digit to be retransmitted after reception. The storage in the time slot 6 "is held so that the counting of the interval of 4 to 40 is. In the track PN 31, the first element of the flip-flop F 1 is operated again, the in the time slot T 12, the first element of the flip-flop P 3 follows, so that in the time slot TS 25 the Koritrollisspannung / 31 opens the gates G17 and G 14 in order to actuate the element 2 of the flip-flop circuit P 6.

The control voltages TS and / 31 open the gate G 58 in Fig. 7. Since the time element 25 is effective as a spacing, the control voltages / 62 and / 12 open the gate G 57, so that the gate 'G60 is then opened and a marking for Storage is coming. This adds a 1 to the storage in time slot 6 *. As _v before the element 1 of flip-flop P 6 is operated in the time slots TS 25 and 1 3, in order to allow re-recording for the rest of the time slots 6 ". Since the relay AR has been talking again, potential to the line LP 2 is in 2 and 4, so that the first element of the flip-flop circuit P 2 becomes effective in the time slot TL 24. In the time slot Γ 31, the gate G 90 in FIG The remaining time elements are saved again as they were tapped.

There is no change on tracks PN 32 to PN 65. Except for the addition of ι in section 5 "for each run. Since the marking storage was carried out in element 28 during track PN 46, the control potentials or time slots open gate G107 in FIG. 6, and gate G106 actuates element 2 of the flip-flop circuit P10. Since the marking is stored in the timing element 30, the control potentials / 71, TSj) O and / 102 open the gates Giii and G103 in order to actuate the second element of the flip-flop circuit P9 in FIG.

As a result, no control potential occurs on line / 91 in time slot Γ 48. The flip-flop circuit P 23 with its element 2 therefore remains actuated. In the time slots TS 28 and 7 \ S "3o, the gates G 107 and G 111 open in order to store a distance in the time element 12. This is done by actuating the elements 2 of the flip-flops P 9 and Ρίο through markings in the time slot elements 2 ' 8 and 30.

In the case of the PN 67 cycle, the time elements 12 and 13 have stored a distance, the element 12 being tapped as the distance, but the element 13 being evaluated as a marking ^! rd, since the control potentials T13 and the second element of the flip-flop P1 open the gate G 2 in order to operate the second element of the flip-flop P 3. The control potential / 32 opens the gate G 52 in Fig. 8 in the time slot Γ 13. Also in the time slot T 13, the control potentials T 13 »/ 11 and / 32 open the gates G 105 and G 106 to the time element 2 of Flip-flop circuit P 10 in Fig. 6 to satisfy. In the time slot TL 20, the gate G95 in FIG. 8 is opened by the control voltages / 102 and TL 20 in order to store a distance in place of an earlier marking. The gate G 138 in FIG. 6 is opened by the control voltages / 102 and i3. The gate G 108 is then opened by the control voltages TL 20 and / 11, so that the element ι of the trigger circuit P10 responds. The gate G 75 in FIG. 7 is therefore opened by the control voltages TL2 1 and ci2 and the gate G 73 is opened by the gate G 75 and the control potential / 101, so that a marking is stored in the time element 21. In the time slot TL 22, the gate G 92 is opened by the control potential c 1 2 , which in turn the gate G 95 is opened to a

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Save distance. The remaining time elements of the section L are newly stored as they were tapped.

It is now necessary to delete the markings stored in the period 'S'.

In the time slot TL 24 and via LP 2, the gates G 16 and Gs are opened in order to open the element 1 of the flip-flop F 2. In the time slot TS25 , the gate G 58, which is controlled by the voltages / 22 or / 31, cannot open, so that the gate G 60 also remains blocked. In this way, the storage of a marker in the section S is prevented. A distance is therefore stored because the gate G 64 in FIG. 8 is opened by the control voltage / 12 and / 61. Furthermore, the element 2 of the flip-flop circuit Fy is actuated via the gate G 63, which remains actuated beyond the time period S.

It is now important to describe the storage and transmission of the following digits in detail! But we will first deal with the successive maintenance functions controlled by the counters Ci, C2 and C3. The second digit is assigned to the counter C 1 in the time slot 2 received, and at the end of the storage, the counter C 1 is controlled by the gates G 137, G 133, G134 and G 135, which • one after the other in the individual counting points cn to c 14 or in the time slots TL 21 ibis TL 24 are open '.

The counter C 2 is used to determine whether the transmission of a different digit is feasible. The control gate G 118 can be opened in each of the two successive time slots TL in which the marking is stored by the control potential during a passage of the counter C 2 in the switch positions ο and, 1, so that the counter C 2 from the switch position ο incremented to 1 and from 1 to the switching position 6 ", when 'require the switching conditions, the counter C 2 in which Sehaltstellung S allows the transmission of the next digit of the counter C 2 is in the timing of T12 in;.. each pass set to ο by a potential that is applied directly to element ο of counter C 2 '.

The counter C 3 counts the transmission of the digits. The advancement of the counter C 3 to the next Switch position in any time segment depends on the existence of switching conditions

-50 gen from how they z. B. are shown in the track PN 67 in Fig. N, in which the first time slot L represents a distance.

The counter C 3 counts the switch position L from ¹ 20 to one after the other. upwards and is reset in each subsequent switch position T 12. The control line / 72 becomes effective in such switching positions. As already mentioned, the counter C2 is in the rest position, so that in the time slots £ 3 of the successive switch positions TL 20 to TL 24 when the expensive lines f 72 come into effect, the counter C 3 receives a pulse and increments it. However, since the switch position TL 20 is free in the track PN 67, alber the switch position. TL21 is occupied, the control potential / 71 becomes effective in the switch position TL21 instead of the control potential / 72, and the counter C 2 switches to position 1, so that the counter C 3 does not move to the empty switch position L later due to the active control voltage / 72 can switch (e.g. L 22 to L 24). , 70

As before, the receipt of the second digit is saved. Since the counter C 1 is now in the switch position 2, the gate G 74 in FIG. 7 is not open in the time slot TL 20 of the next run after receipt, but the gate G 91 in FIG. 8 is in the switch position TL 21, but gate G75 is opened in time slot TL21 by control voltage c \ 2 in order to save a ■■ marking in time slot L21.

While in the case of the first digit ι the tough-1 Series C was in the position 1 'in the timing so.daß TD 32, the control voltage cn goal G18.in Fig. 4 has opened, in the case deir second digit, the Gate C18 not open; but in time slot TD 36 the control potential at C12 opens gate G19, and in this way the first pulse of the second digit is stored in switch position 36 instead of switch position 32, and the number is registered as a whole in time slot group D2 , which contains elements 36 to 39.

At the end of the second digit, a marking is inserted into the time slot TL 22 after the counter C 1 has been brought into its third switching position by opening the gates G 76, G 73 and G 98 in FIG. 7. The second digit is sent, reversed and in the same way as the first digit, with the only difference that the time slots TD 36 to TD 39 are used instead of the time slots TD 32 to TD 35. The. other digits are stored in a similar way and sent out again.

. At the end of the transfer, the marking in the switch position L 21 is removed. After receiving the third and fourth digits, marks are inserted into the time slots L 23 and L 24, while at the end of the transmission of the third and fourth digits, the marks in time slots L 22 and L 23 are removed.

When all message content. received and are sent out, the storage is no longer necessary and must therefore for the assignment to another message channel, which desires to be stored, 'can be made free. the the switching operations required for this develop as follows. .

It can be seen later that elements 20 to 23 of section L are in state ¹ "o". As a result, the switching element 2 of the flip-flop Fi is effective when these elements pass through at this point in time. As a result, the gate G518 in FIG. 3 is not opened in the time segments TL20 to TL 23, so that the element 1 of the flip-flop circuit 16 is left effective and the gate G514 remains closed iri der.zeitlage, Γ31. Here is! "O" (distance) stored in the element position ι, which indicates that

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the storage device is now free. It is now necessary to delete the storage in time slot TCC 5. This is done: During the next run, whether a calling channel ι, 2, 5 or 3 is switched on in the meantime or not. The next time element ι of the flip-flop Fi is tapped, so that the second element of this flip-flop becomes effective. The gate G 517 is not opened, so that the element ι the

ίο toggle switch Fι 5 in Fig. 3 remains actuated. If nothing else occurs before the switch position TCC 5 is reached, the gate G 516 remains closed and the element 1 of the flip-flop circuit Fi3 remains effective, although the element 1 of the flip-flop circuit Fi wants to operate the element 2. Thus, the gates G 520 and G 521 in FIG. 8 are opened, since the device F 14 is still in the switch position 4 and the element 2 of the toggle switch F 7 is actuated, so that the storage "o" occurs in the time slot 5 . The storage is now for

other news channels free. . "

If the. Channel 1, 2 or 3 the common

Device has occupied, the switching element 1, 2 or 3 of the device F 14 would be actuated, the second. Element of flip-flop F 13 follows, by opening a gate that corresponds to gate G 511. Gate G 522 is opened for switching positions 1, 2 or 3 of device F 14 in time slots 3, 4 or 5. Here, "o" is saved for time elements 5 to 11.

If the message channel is separated from the memory device after all memory contents have been transferred, the relays BR and AR remain in the actuated state, so that the elements 1 of the flip-flop circuit FB and FA are conductive at this point in time.

If the connection is triggered under certain circumstances, the drop in relay RR in Fig. 2 actuates the release by closing the contacts rri and rr 2, which open the gates GMy and GM 8 and thus actuate the elements 2 of the flip-flop circuits FB and FA of the elements 1 of the trigger circuits FB and FA. The relays AR and; BR are therefore released and the contact br 1 opens in order to remove the busy line from the c-wire of the incoming connection line.

Three parts of the circuit arrangement have been selected for the description, since these parts are characteristic of the rest of the circuit arrangement. These are the gates G 62, G 63 and G 64 in FIG. 8, which are shown in detail in FIG. 12, and the flip-flop circuit F 8 with the associated circuits from FIG. 6, which are shown in detail in FIG Furthermore, the counter C 2 from FIG. 5 is shown in detail in FIG.

The three gates in FIG. 8, which for the purposes of description form part of an extremely complicated gate network, are connected to the flip-flop circuit Fy, which controls the storage. The gate circuits used are simple rectifier coincidence gates in their basic arrangement. In such gate circuits a common point, which is generally the starting point of the circuits, is connected to a number of control pulses and to a source which supplies a positive bias potential. The connection to the bias source contains a resistor and a connection to the control points, each of which contains a rectifier.

The potential of a control point can have two different values, one of which prevents the gate circuit from being operated because it is at or near earth potential, and the other value which can make the gate circuit effective because it represents a positive potential. If, in the cases where many gates are used, the control point at the Cathode of a cold cathode tube, the control potential is at the ineffective value, if the tube is not ignited and at an effective value when the tube is discharged.

The rectifiers are connected to in. The forward direction from the bias source via the Guide rectifier to the control points. Thus, the effect of the rectifiers is to to keep the common point at a potential which is positive in relation to the Control points is. The arrangement is as follows, go that if the same positive or effective potentials are simultaneously applied to all control points of a gate circuit lie, the potential at the common point is substantially equal to the potential the tax point is. Thus it can be seen that the common point, d. H. the starting point of the gate circuit, only assumes a positive potential, when positive potentials are present at all control points at the same time. As it was found this potential at the common point is equal to the positive potential 'of the control points.

The connection from the common point of a gate to the next stage of the arrangement sometimes includes a rectifier with the forward direction from the common point to next stage of the circuit arrangement. Such rectifiers serve as decouplers and are required where the same point in the circuit above any of several independent gates can be controlled. They serve to ensure that one goal doesn't score a number of others with this one Point connected gates can render ineffective.

Returning to FIG. 12, it can be seen that the gate G 64 is a simple gate of this type, with two control lines, one from point / 11 and the other from point / 61. These two points lead to tubes Fi.ι and F6.1, not shown. When both of these tubes discharge, their cathode potentials go positive and the rectifiers MR1 and Mi? 2 positively biased. This means that the common point assumes a positive potential which is applied to the grid of the cathode amplifier CFA via the decoupling rectifier MR 3. The grid of this tube is

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Ri was at a negative potential so that the CFA tube does not normally conduct. When the gate circuits G 64 or G 62 release an output voltage, the tube CFA becomes conductive, so that a positive potential appears at its cathode.

The second gate G 62 which controls the tube CFA is now considered. The Pig. 8 shows that there are three control inputs, namely /1.1, f6.2 and /4.3, the last of which is a braking input, ie if the input /4.3 discharges, the gate is independent of the state of the other inputs , ineffective. To achieve this, the input voltage /4.3 u> m is reversed and used for control. The reverse circuit uses a single triode V, the anode of which is connected to ground potential via a rectifier MR 4 and to a positive potential of approximately 60 volts via a resistor R 2. The cathode of the tube V is connected to a resistor branch Rj ,, R 4 , which is between a negative supply potential and earth. The control grid is connected to a point of the resistance branch i? 5, R 6 , which lies between a negative supply potential and the control point /4.3, ie at the cathode of a tube F4.3, not shown. The circuit elements are dimensioned in such a way that, when the tube -F4.3 has not ignited, its cathode voltage is at or near ground potential, so that the tube V is switched off. This means that the anode voltage is determined by the positive source which is supplied via the resistor R 2. In this switching state, the coincidence of control lines / 11 and f02 causes gate G 62 to release an output pulse. If the tube F 4.3 discharges, its cathode voltage becomes positive, so that the tube V conducts. The rectifier MR 4 then holds the anode potential to earth, which brakes the gate, regardless of the expensive lines fi.i and /6.2.

The resistor R 2 and deir rectifier MR 5 can be omitted without the circuit operating incorrectly. But the arrangement shown gives better results with the resistor R 2 and the rectifier MR 5.

The relatively simple exemplary embodiment, which was extracted from FIGS. 7 and 8, gives a picture of how this tour network is actually constructed. The cathode amplifiers are similar to the CFA tube and are used at various points in the circuit to achieve the necessary ¹ relationships. However, in view of FIG. 12, it is not a great difficulty to fully develop the network of FIGS. 7 and 8.

The circuit in Fig. 13 will now be described. The flip-flop, which has two gas-filled cold cathode tubes, is coupled to the capacitor Ci at the anode. The control electrodes are connected via resistors to a source of the bias voltage B , the value of which is smaller than the normal supply voltage, e.g. B. 170 volts: with a supply voltage of 350 volts. The bias cannot ignite a tube. When a positive pulse is applied to the control electrode of a non-ignited tube, that tube will discharge. The anode current circuit causes a sudden voltage drop at the anode of a freshly ignited tube, which is applied to the anode of the other tube via the coupling capacitor Ci and extinguishes the previously ignited tube.

Gate G 120, which is connected to tube F8.i , is a simple three-gate gate. The tube Z ⁷ 8.2 is through the gate. G 122 controlled, which contains two rectifiers, which together form a mixer or one-port. One input, which can switch the tube F 8.2, comes from TL 24, while the other input comes from gate G 123. The rectifier MR 6 works, as shown, as part of the gate G 122 as a decoupler for the gate G 123. The gate G 123 is a three-gate, one input of which is denoted by tj>. The inputs TS27 to 7 ^ 3O are switched during one of these four time slots, so that the element pulses are applied to the four rectifiers, which together form a mixing gate. A positive potential across any of these inputs biases the rectifier MRy so that the gate can operate. The other input circuit belongs to gate G 124, which represents a simple single or mixed · with two inputs.

The last circuit to be described relates to the counter C 2, which uses the same tubes as the tube F 8. It is assumed that the pulse T12 has brought the counter C 2 into the switching state in which the tube C2.0 discharges. The common feed line to the other tubes runs from the cathode of tube CFB, which will be described later. A coincidence gate of simple design is located between the successive pairs of tubes. As soon as a positive feed pulse occurs, the rectifiers MR 10 and MR 11 are positively biased. However, at this moment the rectifier MR 12 is positively biased because the counter stage C 2.0 is conductive. Because of this, the gate Mi? 12— MRio an output pulse via the capacitor shown, so that the counting stage C2.ι ignites. The increased current, which runs in the common line through the case resistance Rs , causes an increased voltage drop, which causes the deletion of the counter stage C2.0. Thus, the counting stage C2.ι is now conductive '.

Before the counter stage C 2.1 fired, its cathode potential was at or almost at ground, so that the capacitor C 5 was discharged. When the ZM stage C 2.1 ignites, its cathode potential becomes positive and thus biases the rectifier MR14 . As a result, the capacitor C 5 is charged by a positive potential. This so-called slow output acts like a delayed output from counter C2.1.

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At the next impulse on the common

Feed line will both rectifiers Mi? 13th

. and MR 11 positively biased, whereby the switching stage C2S ignites and the switching stage C 2.1 goes out. This switching state lasts until the next pulse T 12 occurs, which brings the counter to its rest position.

The cathode follower tube CFB emits a positive output pulse when its steamer G118 sends a positive pulse to the grid. This gate has two simple control lines f $ and fji and two mixed expensive gates.

The circuit examples shown give a sufficient idea of the real circuits if one adds the pulse diagrams also shown. However, a few additional remarks are necessary. There are three circuit arrangements made up of three elements, namely F 17, F 4 and F 10 in FIGS. 2, 4 and 6, which must be viewed as if they were flip-flops. These arrangements, which represent simple, more stable registers, could consist of three tubes, the anodes of which are connected by rectifiers, ie a three-tube design similar to the arrangement F 8. The more st from Me register

,: F 14 could be a common circuit, such as B. the counter in Fig. 14, but with more complicated gates between! the tubes,

The five-stage counter C 3 could consist of gas-filled multi-cathode tubes. This would make a useful arrangement as such a tube can be considered economical.
All of those arrangements which have yet to be described are particular embodiments of memory or storage devices which are shown schematically in FIGS. 15-17. These are matrix devices arranged in terms of coordinates.

Such a matrix arrangement contains a number of cores made of magnetic material, of which, each can be brought into one of two stable states, usually positive or negative magnetizations.

A core is required for each element. In the present case, ten memories must be provided, each of which consists of forty-eight elements. That would add up to four hundred and eighty cores. The cores are arranged in η rows, as shown, each row containing m cores, so that one has m X η cores arranged in such a way that the cores are m columns and η rows form.

Each core has three windings, and. two control windings and one tap winding. It can be seen from FIGS. 15 and 16 that the uppermost windings of all cores are connected to a line, which has a common output connection forms. These windings are the tap windings, and the common line is to be regarded as an exit line. The other windings are, as can be seen from the figures, connected to each other in terms of coordinates.

To select a certain impure core, e.g. core m + 2, the correct vertical conduction V and the corresponding horizontal conduction H must be detected. Each of the two coordinates absorbs half the current which is necessary to change the magnetic state of the core. The current direction is in the chosen one. Example chosen so that the core is positively magnetized. Thus, only the core m + 2 can be influenced, and it can obviously only be changed if it was already negatively magnetized. The magnetic change so produced causes a large change in the magnetic flux across the tap winding of the corresponding core, releasing an output pulse. The storage for this is described later :.

The three control impulses, i2 and if3, which have already been mentioned, are used for control processes. It is now considered how and when the pulses i2 are generated. The counter C 5 has η switch positions, specifically corresponding to the number of cores per column. The counter C 5 is switched with each cycle by the control lines, C $ m and £ 3 via gate G 401. In the present case, m = 48 is assumed, ie the number of element positions per storage. In this case the outputs from the counter C 5 can be used to produce timing pulses which are used for control purposes. Also η is equal to the number 10, ie the number of memories. It is clear that any other value for m and η can be accepted. An alternative is e.g. B. in 24 X 20 if, two rows for each: storage were necessary.

The outputs from the counter C 5 are on. die-gates are created which control the currents that flow in the column windings. The outputs of the counter C 6 are applied to those gates which control the series windings. is the amplitude of. the two currents, which act in an additive direction, are large enough to generate a force large enough to influence a core beyond the bend of the hysteresis loop. However, one of these currents alone is incapable of producing this force. The tapping process consists of magnetizing the selected core in a positive direction, and! although without regard to his previous one. State, if the previous ¹ state was a positive magnetization, no output pulse takes place, but if the previous state was negative, an output pulse is sent from the tap winding. It is further noted that the tap windings are arranged such that. in other cases, impulses from others. Polarity, which are able to overcome accumulated demagnetizing forces.

It is assumed that the distributor, which is represented by the 'counters C 5 and. C 6 is formed, the units w and, η excited. The pulse £ 3 of this egg length switches the counter C 5 to the

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Switching step ι, and at the same time the gate G 401 opens, so ¹ that the counter C 6 comes to the switching step ι. At time ii are; the gates G 402, G 403, G 404 and G 405 are opened so that the first column of the windings and the first row of windings each receive a current pulse. As already described, only the core 1 can be made effective, and since the direction of the pulse is intended for a positive magnetization, no output pulse comes about if this core was already positively magnetized. However, if this core was already negatively magnetized, an output pulse is emitted.

Although the connection in which this circuit effect is achieved is not shown, the output pulse produced in this way is applied both to the control circuit and to the input circuit of FIG. The input circuit is such that the core is positively magnetized if it is to be left in the interrogated state. No output pulse is sent. On the other hand, if the nucleus is to be left negative, a negative pulse - i2 is generated. In the last. In this case, gates G 407 and G 405 as well as G 406 and G 403 are open. Therefore, the pulses travel through the same windings in the reverse direction of the original tapping direction. As before, only core 1 can be influenced, and this core is brought into state N because of the direction of the pulse.

The next pulse t $ switches the counter C 5 to its second switch position and thus with the next pulse 1 1 the gates in the second column and the first row. Since the core 2 is magnetized positively or left positive, an output pulse is produced or not, depending on how the magnetic state of the core was previously. The switching functions continue to develop as described, one after the other for each core, as shown in FIG. The counter C 5 selects the column and the counter C 6 the rows. For the circuit arrangement in Fig. 15 it was assumed that m = 48, the core m + 1 is the first core of the second storage,

16 shows schematically the function of the auxiliary head. It is recalled that the auxiliary head is used to apply a busy memory to the first element: an occupied memory lane. This occurs at an appropriate time slot within the memory cycle. In the matrix arrangement, an additional pick-up gate G 449 is used, which is controlled by the pulse -i2 and corresponds to the pick-up gate G 406 for the normal column, but receives an additional control pulse via ARD .

If it is necessary to use a restoration, the expensive line ARD takes effect. This control line is controlled by the gate G 514 in Fig. 3 or by the flip-flop .F 23 in Fig. 6, if necessary. The only difference between this mode of operation and that which uses a drum for storage is essentially to ensure that the time slot ¹ used to switch the control line ARD is not also used to switch via the normal memory port. If these measures were not taken, incorrect storage of an undesired tap could occur if three or even four lines are excited at the same time.

In Fig. 16, there are two cores of the second row and two of the last, row shown. The gates G 450 and G 451 are the row gates for restoring, while the remaining gates are the normal ones as in FIG.

From Figs. 15 and 16 it can be seen that the symbols shown for the voltage gates are shown for the sake of simplicity. However, the current control used for the matrix is, for example, with the help of "hard" Tubes carried out.

In Fig. 17 there is schematically shown a coordinate matrix which is essentially the same as the arrangements shown in Figs. 15 and 16, but with the difference that so-called ferroelectric elements are used. Ferroelectric materials are dielectrics in which electrical dipoles occur and which adapt themselves through mutual relationships. The dielectric induction versus g ₀ electric field curves show a hysteresis loop similar to that represented by the BH curves for ferromagnetic materials. Barium titianaiti (BaTi 03) is considered the most common ferroelectric material today.

The function is in many respects the same as that for ferromagnetic matrices. a tap i _O o pulse on. Element in which a pulse is: - stored, brings it to the, other, stable state and thus emits a strong output pulse. If you use barium titanates you get one. Output pulse of 25 volts for

a memory state. or a mark,

when the input pulse is 30 volts for 5 ms compared to. 0.6 volts for none stored Switching state or a distance. In the present case, shorter pulses can be used which leads to correspondingly lower voltages.

The matrix of FIG. 17 contains a number m X η of ferroelectric elements which are arranged in rows and columns. According to the usual arrangement, m = 48, η = ίο or m = 24 and η = 20 and, as in FIG. 15, the same counter device can be used.

To select a particular element for storage or tapping, half of the required voltage is applied to the row line and the other half to. the column line is applied, whereby an element is made effective. How: in the previous arrangements, the storage is initiated with the pulses i2 and the tapping with the pulses 1 1.

609 508/157

J 8412 VIIIal21 a ^s

The individual elements each have a ■ capacitor and a rectifier connected in parallel connected in series. In FIG. 17, these switching elements are each common for one column.

The output lines are taken from the columns and connected to. an exit gate G 444 led.

. Furthermore, as in Fig. 15, arrangements are provided, to pick up a pulse.

A preferred embodiment of the matrix contains a single large crystal of barium titanate 0.1 to 0.2 mm thick: on which conductive strips are attached on each side, namely two sets of these strips in an orthogonal arrangement. Every crossing point represents! a single one Storage element.

Claims (15)

Patent claims: i. Circuit arrangement for test equipment ■ gen in memories, which: the message contents by changing magnetic states: in record binary form, characterized in that individual successive Each message content through a different one. magnetic. State, marked: are, the in each case at its end a control device can become effective, which only after testing of the previous message content Admission of the following respectively. 2. Circuit arrangement according to claim. 1, characterized in that a constant speed storage device driven drum with several magnetizable tracks as well as receiving and iö playback heads is used. 3. Circuit arrangement according spoke 2, characterized in that switching means are present to the stored message content through a; or several test processes 4.0 to be determined. . . 4. Circuit arrangement according to claim 3, characterized in that the beginning and the end of a certain. Message content through the respective change · the magnetic Imprint can be determined. 5. Circuit arrangement according to claim 2 and 4, characterized in that the magnetic storage and tapping device a electronic control device is assigned. 6. Circuit arrangement according to claim. 5, characterized in that in the control device Switching means are effective to change the applied, magnetic state to cause. 7. Circuit arrangement according to claim 6, characterized in that a modified one Message content is checked again with regard to its magnetic state. 8. Circuit arrangement according to claim 7, characterized in that the message content in binary form, d. H. by storing two different magnetic impressions will. 9. Circuit arrangement according spoke 8, characterized in that when there is a change of a stored message content dler the respective impressed magnetic state changed was. 10. Circuit arrangement according to claim 9, characterized in that switching means are present. Which after a certain Do not detect any magnetic change in the time period that is assigned to a message section, another check of the message content and, if necessary, a change initiate storage. 11. Circuit arrangement according to claim 10, characterized in that each storage has a certain number of individual time elements used, which are checked one after the other. 12. Circuit arrangement according to spoke 11, characterized in that the control and test device for a number of successive Saving is in effect. Circuit arrangement according to claims 2 and 12, characterized in that the magnetic tracks of the drums contain two separate sections and the recording and playback heads are arranged with respect to the sections of the tracks so that when the one section acts on the pickup heads ¹ the corresponding other sections of the paths are effective on the storage heads. 14. Circuit arrangement in particular according to claim 1, characterized in that for Storage ferromagnetic elements are used, which are connected in terms of coordinates are (Fig. 16). 15. Circuit arrangement in particular according to ioo Claim 1, characterized in that ferroelectric elements are used for storage which are interconnected in terms of coordinates (Fig. 17). In addition 6 sheets of drawings