DEI0008411MA - - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

Registration date: March 19, 1954. Advertised on June 28, 1956

GERMAN PATENT OFFICE

PATENT APPLICATION

CLASS 21a ³ GROUP 32oi

/ 8411 VIIIal'21a ³

Esmond P. G. Wright and Joseph Rice, London

have been named as inventors

International Standard Electric Corporation, New York, N.Y. (V. St. A.)

Representative: Dipl.-Ing. H. Ciaessen, patent attorney, Stuttgart-Zuffenhausen

Circuit arrangement for a pulse repeater in telecommunications, in particular telephone systems

The priority of the application in Great Britain of March 20, 1953 has been claimed

The invention relates to a circuit arrangement for a pulse repeater in telecommunications', in particular telephone systems, which the dialing pulses saves in binary form on individual element sections of the tracks.

An important prerequisite for the security of dialing processes, especially for remote dialing processes, consists in the fact that the dialing current surges given over the lines on the opposite side are temporal ίο be recorded without distortion. This is especially true for the transmission of such dialing pulses over longer lines, as pulses of different lengths can trigger various switching processes.

It is known that when transmitting a series of dialing pulses over long lines, distortions, i.e. a change in the individual pulse lengths, which is known as current surge equalization make necessary. These distortions can occur, especially if there are several rush current conversions add.

There are already known electrical surge equalizers which consist of several relays. You check

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the incoming pulses and represent possible distortions correct if they do not meet certain requirements. These equalizers can, for example only correct the pulse duration or the pause between two pulses or both.

However, mechanical surge equalizers have also become known which consist of a mechanism exist in the manner of a clockwork, which absorb the electric shocks and they in a new form

ίο play back just like the original Impulse generator.

Impulse equalizers or repeaters constructed from individual relays are proportionate expensive and do not perform the equalization process completely, because the relays used with their switching times are tolerance-dependent, albeit to a lesser extent. In contrast, a mechanical one works Impulse equalizer works fine, but is subject to mechanical wear and tear.

In order to avoid the defects mentioned, i.e. the relatively high effort and mechanical wear and tear and also to enable multiple use of a pulse repeater device according to the invention proposed an arrangement in the form that when connecting a selective current surges transmitting connection line to a pulse repeater after testing a part of this Pulse repeater of the current impulses sent by the connected connection line to Pulse repetition stores a switching criterion that characterizes the connecting line in this part is imprinted, which after the storage of the election surges, the deposition of the same , the outgoing end of the connected connection line and then the triggering of the pulse renewer caused. The storage of the elective current surges takes place here on a binary basis, whereby as Storage organs both magnetic drums with multiple lanes and storage and pick-up heads as well as coordinate-like interconnected ferromagnetic or ferroelectric elements are used can be.

The details of the invention will then be described with the aid of the following figures explained in more detail. Here shows

Fig. Ι a schematic overview of an arrangement for a storage device with. a magnetic drum,

Fig. 2 shows one of the communication channels as it is used for this device, in connection with a number electronic power gates, each assigned to a channel,

3 to 8 the other control devices by which the storage is achieved and by which the impulses are renewed,

9 to 11 graphical representations with the Waveforms as used in the circuit described,

12 to 14 particular circuit details,

FIGS. 15 and 16 show a magnetic network with static means,

17 shows a static network with ferroelectric Switching elements.

In the embodiment which will now be described, a magnetic drum or disk is used as an electrical storage device. It consists, for example, of a brass drum, which has a magnetic coating on its cylindrical surface. This coating has a number of closely spaced lanes or tracks, and each of these tracks is one of them a memory and a pick-up head are assigned. The drum runs on a rotatable shaft, which with high speed driven by an electric motor. -

The message contents are in the form of successive magnetic impressions of each one of two identifying features is stored. These identifying features are in the known way with "o" and "1", or with "distance" and "marking". When storing of digits, this is done on the binary system, although other encodings are also possible.

Each track or track is divided into a number of longitudinal sections divided. The details of this will be described later. The storage and pick-up heads are arranged separately from one another, so that two separate track sections form a storage section form. If a pick-up head picks up a section of a storage path, it is the corresponding storage head effective on the other section of this track. The stored message content is thus tapped and stored again in the corresponding section of the path.

In addition to the lanes on which news content is stored, a special lane is provided, which stores each position of the storage elements. About this particular train is a pick-up head is also provided, from which one pulse per message element is taken. The last-mentioned path is also referred to as the time path and the associated pick-up head as the time head. The latter device is used to each have a set of three closely spaced To produce pulses per message element. Another additional track has the task of each To determine the position of the first message element on each memory section. This web is called Marking track and the pick-up head assigned to it as a marking head. The latter gives a pulse cycle, which determines the beginning of each memory section. These two pulse cycles, namely the timing pulse cycle and the marking pulse cycle are used to control all switching operations used. The device for message storage described is known as "Memory Renewer" called.

The simplest way of assigning the individual news channels to the reminder is to that a certain path is allocated to each storage. However, since the renewer is only for the reception and the subsequent retransmission of message content is used and the latter only one take a short period of time, must for the assignment of the message content to the individual Appropriate division of the lanes

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be hit. For this reason, the number of intended stores is less than the number of the channels. There are therefore provisions for the temporary allocation of memories to a channel necessary if a renewal of the storage is desired.

The memories on a particular track form a group, which is a group of circuits is assigned which, for example, ten times

ίο is greater than the number of storages. It a single common connection and control circuit is provided, between the Storage circuits and the railways. In a particular example, there can be a hundred storage circuits ten storages can be allocated. However, in the interests of simplicity the following is made Description assumed that the memories of a lane are available to each of the ten channels stand.

In the timing diagrams of FIGS. 9, 10 and 11, shown how a section of a path which forms a 'store and contains forty-eight elements, is used for the assignment of a message channel to a storage and for the storage and'refreshing series of pulses during a series of passes of storage under the tap head. Die.Elemente are numbered 1 to 48, and Figure 9 shows how they are grouped. This Elements are sometimes used individually and sometimes in groups, depending on the purpose they are used. If a group of consecutive element positions. for the same Purpose, this group forms a memory section. As mentioned earlier, each will Element picked up and saved, either with or without • modification in a certain position in a repeatable cycle of time slots determined by the rotation of the drum will.

The time pulses generated by the element track are used to control the electronic gates and are denoted by the symbol T. Where an element forms part of the groups shown in FIG. 9, this letter is followed by a group of elements. The element identification follows the character T alone or in connection with a group identification. For example, gate G16 in FIG. 4 has to be controlled by TL 24, with which a time pulse in group L and element no. 24 is identified.

As already mentioned, the elements of the pulse cycle are also used in a known manner to define three cycles of closely spaced pulses, the pulses being staggered and each being one third of the duration of a pulse element. These closely spaced pulses are denoted by ti, ti, and t $ , and all of these pulses occur simultaneously within one element.

The above description has made it clear that the elements on a web lie close together and the memories are caused by overprinting an existing memory. If a storage is empty or free, its elements are positively excited, ie they have stored "1". The remaining elements of group R count the revolutions of the drum, which will be described in detail later.

For a better understanding it is pointed out again that each track of the drum has a number Has storage sections and each section consists of forty-eight elements. With the present Arrangement, two such memory sections form a memory, which with any the news channels can be connected. For the sake of simplicity it is assumed that that ten channels are served by storing one path. The control circuits are all Storages assigned to a path together.

A single section of a web will now be considered in particular. The first element of a section is used to indicate whether it is free or busy. The next group of elements is used to identify one of the channels to which the section is available. This element group contains the label storage. In the present case the elements 2 to 11, which are designated with CC 2 to CC 11, are intended to identify the channels 1 to 10.

The control circuit for the railroad has a register with enough stable layers to identify the various channels. Such a register consists essentially of an ordinary electronic counter, the only difference being that it can be stopped in any switching position by associated control means. It is controlled by impulses from the drum's timeline. These time pulses, which occur regardless of whether there is storage in the element concerned, are denoted by the letter T. The letters identify the element group to which they belong. Therefore, if no channel requires the servicing of a store, pulses TCC 2 through 11 control the register over this pulse cycle. It then remains in the last switching position, namely TCC 11, until the pulse TCC 2 of the next section on this path occurs. At first glance it seems that this could lead to disturbances; but the type of storage which is carried out on the track sections is such that no disturbances occur.

It has already been established that a time slot TCC is assigned to each channel. Each channel can only store during its TCC time slot. During normal operation, ie during scanning by a register when a calling channel is detected, all sections are set to 0, with the exception of sections 19 and 20, which are labeled R 19 and L 20. The reasons for this are discussed in the following description. ■ ■ ·

It is assumed that channel # 4 needs storage. The calling channel thus provides ! a switching state, which in the control

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' Circuit and thus in the register causes the scanning process to be stopped in a time slot which is assigned to channel no. 4, ie in time slot TCC 5. This causes the re-storage in element no. 5, which is effective as a marking element. The register remains in the switching position for channel no. 4, while the section of the occupied memory passes the pick-up and pick-up head.

At the same moment that the scan of the register is stopped, the ringing state in the channel is released. This offers the security that the channel does not occupy multiple memories. Passing behind the heads takes place at the peeling point PN τ in FIG. 9.

It is necessary to ensure that the storage which has been made is not detected by channels 1 to 3 on the next pass, ie by channels whose timing is before the channel for which the section was occupied and marked. For this reason, the aforementioned auxiliary storage head is used. He works in a time slot behind the time slots of all channels. This auxiliary head saves. a marking in the first element and thus marks the entire element section as occupied. In the arrangement described, the auxiliary head becomes effective in the time slot T 31. The choice of this timing is arbitrary and is essentially a matter of mechanical design. At the end of the cycle (time slot PNi) , time slot T 48 switches the entire control circuit to "o" so that it is available for other storage. As already mentioned, the possibility of malfunctions is prevented by the type of storage in the switch position PNi '. These memories indicate that the section is busy and identify the channel for which that section was occupied.

At the beginning of the next pass PN 2 in FIG. 9, the first element is picked up and stored again as a marking element. Since there are two sections per lane, the second section begins after the drum has made half a revolution. As before, the register begins its cycle, but the TCC 5 marker is tapped and stopped in the fourth switch position, specifically for the channel which was reserved for storage. Since the register scans with each pass until it reaches the switch position which is marked as calling, the assignment is carried out by the calling channel. The mentioned marking is also saved. In this way, the control circuit picks up the stored message content with each pass and accordingly takes care of its switching operations. During the following runs, the markings in switch positions i and 5 are continuously picked up and saved again. However, these runs are counted in sections 15-19. In pass PN 2 , the marking is stored in the switch position 14 and in the switch positions 15 and 19 distances. However, the switch position 20 has been saved again. The elements of the switch positions 21 to 47 are stored as distances, and a control mark is recorded in the switch position 48. The time pulse T 48 causes a control relay to respond in order to close the previous loop. At switch position T 14 of pass PN 2 , the channel was marked as occupied by another relay. In the subsequent runs, namely until the first dialing pulse is received, these switching processes are repeated, ie the markings are picked up in switching positions 1, 5, 14, 20 and 48 and stored again. These runs are counted in binary form at switch positions 15 to 19; but this count has no effect. Since these miscounts have no influence whatsoever on other switching functions, they do not need to be switched off. The count is shown in Fig. 10 at PiV 3 to PN 5. With each run, the count becomes effective by tapping all stored elements.

It is assumed that the first dialing digit pulses for tap PiV6 are received. During this cycle, the memories in the switching elements 14 to 19 are implemented at intervals. The distances are also stored in switch position 19 and switch positions 21 and 24, 25 to 30 and 31. The receipt of the first pulses causes a marking which is stored in the switch position 32, namely in the switch position 1 of the section D 1 of the occupied memory path. This means that the first pulses have been received. The switch positions 33 to 47 are newly saved as distances and 48 as markings.

The selection pulses are relatively long compared to the individual cycles, so that such a pulse lasts for several such cycles. The revolutions during which the first pulse occurs are counted in part R of the track section, specifically in switch positions 15 to 19. If the pulse has been received and an interruption pulse is too long, this is indicated by a marking displayed, which is stored in switch position 19. When it is picked up, this then causes the circuit arrangement to be forcibly triggered, the track section being brought into its rest position. Thus, the time of an interruption is counted by counting the taps of a memory. If the interruption lasts so long that an error can be assumed, the storage made in switch position 19 is evaluated by the control circuit as an indicator for forced triggering. ■.

In this case it is assumed; that the pulse has a normal length, the counting of the rounds PN 7, PN 8 and PN 9 corresponds to a normal duration and on the first round PN 10 it is determined that the pulse has ended. This causes the storage of a marking in the switch position 14 and a distance in the switch positions 15 to 19. At PN 11, counting starts again at R and lasts until the second dialing pulse is received. This count limits the switching status for the channel.

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The second dialing pulse comes, as is assumed, in pass PiV 12 and is stored in part D 1 (switch position 32 to 35). This is done by adding 1 to the digit because in this case one is already stored in that part. The usual counting of the cycles for the duration of a dialing pulse takes place in the switch positions 15 to 19 during the passes PN 13 to PN 15. This ends the dialing pulse and initiates the switching processes, as previously described.

In the present example it is assumed that the first digit is a 2. Unable to know this, the facility checks the fact that it is detecting the pauses between the pulses. This is done by counting the number of passes between the pulses. The counting takes place in section R (switching element 15 to 19) during passes PN16 to PN20. The pause between the digits is determined when a marking is stored in the switch position 17. During the cycle during which these processes take place, markings in the switch positions 20 and 21 are stored. The control circuit then assumes a switching state from which the received digit can be transmitted further.

The stored digit is then newly stored in section D ι as its complement, ie all binary elements are reversed. All digit current surges, which are then recorded, are then passed through the control circuit to section D 2 (switch positions 36 to 39). After the count, which determines that there is a pause between the digits, the switch positions 15 and 18 are stored again with intervals, but the switch position 19 is held as a marker and remains until the next digit is received. These measures are taken so that no incorrect switching occurs.

When the first pulse of the second digit is received, distances are stored in section R (switch positions 15 to 19). The receipt of the second digit is the same as the first, except that it is stored in section D 2.

The third digit is included in Section D 3, etc.

The pulse is now transmitted over the loop, and since each pulse is sent, 1 is added to the digit in section Di so that when all the elements of section D 1 are marked, the digit is completely transmitted on. Each renewed pulse begins at the switch position T 48 of a cycle and lasts four cycles. These runs are counted in a known manner, namely in the section S, ie in the switch positions 25 to 30. When a digit is sent out, its storage in the section L, i. h: in switch positions 20 to 24, deleted.

The renewed pulse begins at switch position Γ 48 of the cycle, namely at path PN21. This interrupts the forward loop and re-stores element 48 as the distance. This is a sign that an impulse has been transmitted further. The next digit can be received during the following passes. Your pulses are stored in section D 2 (switch positions 36 to 39), with section R being counted, as is already known. During the first run of the renewed pulse, a marking is stored at the switch position 25, the switch positions 26 to 30 being recorded as distances.

In order to save the pulse transmission, a marking is held in the switch position 31, which is designated with SCM . This marking continues as long as the pulse is transmitted and its presence is used to ensure that only one is added to section Z) 4 for each transmitted pulse. This addition of ι takes place in the usual way, ie by reversing all elements from section D 1 up to and including the first distance. During the following passes, the pulse count continues in section S, with no other change occurring except for the storage in section D 2 for the second digit. This count is shown in circuits P.ZV21 to PiV24 in FIG. 11, in which no storage is shown for the second digit.

At the end of the transmitted pulse, the switch position 27 is stored as a distance, and. depending on this, the element 31 is also saved as a distance, the element 48 as a marker. The pulse is ended in the period Γ 48. During the next pass PN 25, the storage in section 5 is deleted, ie re-saved as intervals.

The second pulse is retransmitted in the same way with a 1 added to section D1 as before. These measures take place during runs PN 26 to PN2g. During the pass PN28 the already mentioned auxiliary memory becomes effective to hold a marking in the switching position 12 and thereby to indicate that the transmitted pulse is the last. This is true when the circuit determines that all of the markings in section D 1 are in place. During the next run, the element 13 also receives a marking, which is also stored during the run PN 30. The segment indicates that the pulse duration has shifted and this causes element 48 to be stored as a marker and also to cause the pulse to terminate.

After a digit has been completely transferred, a pause is inserted between two digits, and the runs during this pause are counted in section 5. A break lasts at least thirty-six runs, and since the last digit in section S was a 4, is the break only ends after the section counted forty runs.

In the first pass for the pause between the digits, the switch position 31 is referred to as a distance. From this to pass PN 65, a 1 is added to the count in section S for each pass.

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When the marking occurred in the switch position 28 during the passage PN 66 , a control device was actuated, and further control devices become effective when a marking is stored in the switch position 30. These together indicate that the correct procedure for this number has been carried out. When pass PN 66 occurs, element 12 is spaced, and during pass PN 67, element 13 is also spaced. The same applies to the switch position 20, which indicates that the first digit has been sent, whereas the switch position 21 goes into the marking state. This informs the control device that the next digit to be sent is the second digit stored. This pass clears the count in section 5.

As already described, other digits can be recorded and saved during the pause between the digits. The second digit is now released from storage in the same way as the first, under the control of section D 2.

The forwarding of the received digits to theirs

Places on the section is determined by the counter in the control circuit by tapping the message content controlled. A counter causes the received digits to be forwarded to the appropriate ones Sections of the memory path, which switches step by step at the end of each digit. A second counter will used to determine what retransmission can take place and a third counter ■ directs the digits out. These counters are brought into switching positions that are suitable for storage and cooperate with the control circuits under control of the stored message contents in the individual sections of the storage lane.

At the end of the reception the second digit will be a marking is stored in the switch position 22, and when the second digit is sent, the Marks previously saved in switch position 21 have been deleted. . .

In the same way, markings are stamped on the switch positions 23 and 24 as soon as the third and fourth digits have been received in full. When the switching operations are completed at the end of the further transmission of these digits, the markings on the switching positions 22 and 23 are deleted. When the transmission is complete, element 1 is converted to a distance, and when the distance is tapped in time slot T i , it causes element TCC 5 (the identifier for channel 4) to be relocated to a distance. The storage can then be carried out for each of the channels 1 to 3 before the marking in switch position 5 is re-stored as the distance.

From the preceding description it can be seen that the functions of the control circuit are of secondary importance Role-play. The message contents received from the user equipment d. H. the burst series from a communication channel to which storage is assigned should, and the message that identifies the switching state of the consumer device, as well as the process the switching operations are recorded in the memory device. The control circuit is winding all storage processes one after the other. When a save starts, after the run on the heads, the control device is in operation according to the tapped information and then controls the necessary switching operations. While these switching operations handle, the control circuit causes new memory information, which the further process initiate switching operations. At the end of the run, the control device becomes free and is new Storage operations available.

It is recalled that all time-limiting operations are carried out by a counter with the help of Passes are made on the heads. If the device has a combined storage and pick-up head as well as the corresponding circuit is required, the time limit becomes whole by counting Rotations of the drum carried out.

Before beginning to describe the details of the circuit diagrams, there are some explanations required with regard to the circuits.

The electronic gates, which are known per se, are shown as circles, and the controls the same with the help of radial lines, the arrows of which touch the circles. The exits of these gates will be also shown as radial lines, but their arrows point outwards. The digits within the Circles indicate the total number of controls that must be effective for a gate to have an output voltage dismisses. If ζ. Β. there are four control lines and the number within the Circle is a 2, then the gate releases an output voltage when two of these control lines are effective are.

If a short line is drawn across the control line, as is the case with control line / "43 for gate G 62 in Fig. 8, this means that when this control line is active, this gate cannot release any output voltage, even if many of its other control lines are active. The excitation of such a control line can block the door under certain circumstances. The designations for all doors begin with the letter G.

The other known switching elements used in the arrangement described are electronic Trigger circuits with two stable positions, counters and registers with several stable positions.

A counter, which contains a number of individual steps, each of which is able to adopt one of two switching positions, namely "on" or "off", is shown as a series of adjacent rectangles, e.g. B. C3 in Fig. 5. The counters shown all count to the end of their switching options and are then brought to the rest position. A register with several stable layers, e.g. B. F το in Fig. 6, is shown exactly as a counter, only with the difference that the longer dimension of each rectangle runs in the vertical direction, while the longer dimension in the

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Counters in the horizontal dimension. A register with several stable layers is essentially constructed in the same way as a counter, but it usually does not run through all the switch positions. Just as with the counter, only one switching stage is in operation in a time unit, and depending on the Switching states, each stage can operate the next, whereby the previously operated stage becomes one ineffective switching state occurs.

ίο An electronic toggle switch with two stable positions is essentially a register with two stable positions. The above-mentioned devices, namely the flip-flops, are denoted by the letter F and the counters by the letter C. The individual switch positions of the counters are consecutively labeled 1, 2, 3, etc.

If a flip-flop and other output circuits were connected to all of the ports they were to control, it would create an intricate network of wires that is difficult to miss. The lines have therefore been omitted, and short control lines at the gates give the relationship with an f, by which organ these gates are controlled. So z. B. the flip-flop switch F 11 make the line / Ί11 or / Ί12 effective, with the last digit 1 or 2 indicates which switch position of the flip-flop the control line in question can be effective.

To make the circuit diagram easier to understand, certain parts of the circuits are included shown in full, namely in FIGS. 12 to 14. These will be described after dealing with Figs. 1-8.

Before proceeding with the detailed description of FIGS A description of the general arrangement is also given with reference to FIG.

This shows three communication channels which contain the incoming connection lines Ti, T2, and T 3. These belong to the outgoing lines TOi, TO2 and TO3. A circuit arrangement belongs to each channel, namely the circuit arrangements CCi, CC2 and CC3 with regard to the presence of three communication channels.

An electronic scanning device SCB is assigned to the three connecting channels, which searches for the respective channel which requires pulse renewal. Such a scanning device can of course also scan more than three channels.

In the detailed description, one scanning device serves ten channels.

Furthermore, the magnetic drum MD is shown in FIG. Five of the closely spaced storage lanes of this drum are shown.

The first of these tracks MT is the marking track, which, as already described, picks up a marking at the beginning of each storage section of all tracks. The marking track MT is assigned a marking pick-up head WH which picks up the pulses and controls the counter EC via an amplifier MA , which is described in detail later.

The next path is the element or time path ET, which has a magnetic impression in every switch position (element). The element or time header EH and an amplifier EA are assigned to this path. The output of this amplifier runs on the one hand to an element or time pulse counter EC, which has a number of switching positions which is equal to the number of elements on each track section. On the other hand, the output from the amplifier EA runs to a pulse circuit PF, which generates the pulses ti , the width of which is a third of the pulses from EA . The second output from the pulse circuit PF is fed to a delay circuit D ι , which carries out a delay of a third of the pulses from EA and thus generates the pulses t2. The second output from the delay circuit D 1 leads to a further delay circuit D 2, which produces the pulses £ 3 in the same way. The individual outputs of the counter EC send pulses in the individual switch positions.

The output on the marking path is labeled TM and is used to bring the counter EC to its rest position.

The devices associated with a single lane will now be described. These include a storage head SH, a tap head RH and an auxiliary storage head ASH, the purpose of which will be described later. All of these heads are assigned amplifiers, which are not designated in detail. The memory path, which is now to be considered, is the middle one and is used for those communication channels which are reached via the scanning device SCB . This scanning device is connected to a device RSB which controls the tapping, storage, insertion and deletion of message contents.

There are also shown schematically other scanning and control devices, namely RSA, SCA, RSC and SCC , which are assigned to other memory lanes.

The devices below the drum MD in Fig. Ι do not require any further explanation, so that the description of the details can now be made.

If no channel requests storage, the devices F 13 and F 15 in Fig. 3 have switched their elements ι. At this point in time the gates Ggio and G-517 are blocked, since element 1 of the device F 1 (toggle circuit) in Fig. 4, which receives the outputs of the tapping device, is not switched during the switch positions 1 to 11, since no storage is desired. Gate 511 in FIG. 3 and the corresponding gates for the other communication channels are also blocked, since element 3 of device F 17 is normally connected via br 2 (FIG. 2) and therefore there is no potential on control line / Ί72.

When a track section begins to run past the tapping head, element 1 of the toggle switchi "i3 is actuated in switch position 1, so that potential is applied via the control line / Ί31 with the pulses TCC 2 to Ii, around gates G 501 to G510 one after the other to open so that the device .F14 operates its elements 1, 2, etc. one after the other. The device F 14 has so many switching

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Positions, how message channels are assigned to the storage path. As can be seen from Fig. 3, it is assumed that there are ten such channels. Thus, every free storage lends itself to every message channel. The outputs of the device .F14 are applied to the gates GMi to GM 5 of the corresponding communication channels in Fig. 2, but these gates remain closed because the control line / Ί32 is not conductive. There are also three exits to the gates, e.g. B. G512 and G52O in Figs. 7 and 8, which are assigned to the flip-flop circuit F 7 in Fig. 7. The flip-flop circuit F 7 with its element 2 is thus effective for the duration of the selection elements 2 to 11. The gate 512 and the corresponding gates for other channels are opened by the pulses TCC ; but the TorGsiq is blocked by the control line / Ί32. However, the gate G 520 and the corresponding gates for the other channels are opened and, accordingly, the gate G 521

ao through the control line / Ί31, so that gate G99 opens for each of the elements 2 to 11 at time ti and thus switches element 2 of the device Fy , so that "o" is stored for the selection elements. '

It is now assumed that the communication channel 4 is in operation and requires storage for the purpose of pulse renewal. Initially, the device F 17 in FIG. 2 is connected to its element 3; but when the loop is closed off, a positive signal to the gate GR 1 is placed, which in conjunction with the control line / Ί73 the opening of the gate Gi? 1 causes and thus the element 2 of the device F 17 switches. The potential applied to the control line / Ί72 in Fig. 3

causes the opening of the gate 511 in the time slot TCC 5, and since element 1 of the flip-flop F 15 is switched, the gates G5i5 and G5i3 are opened and thus cause the switching of the element 2 of the flip-flop .F13. The element 1 of the flip-flop F 13, which is not actuated, blocks the gates G501 to G510, so that the device F 14, which has switched its fourth element at this point in time, remains in the same position during this section storage. This prevents other communication channels from being switched on before the busy element is stored in the switch position ι. At the time £ 3, the gate GR 2 in Fig. 2 is opened via the control line TCC 5, so that the element 1 of the device Fi7 is switched. The signal is removed from the control line f 172 and thus prevents other storages for this message channel.

The potential at the control line / Ί32 in the switch position TCC 5 causes the opening of the gate G519 in Fig. 7 as well as the blocking of the gate 521 and as a result of the time slot TCC 5 and ti the opening of the gate G 98 and the actuation of the element ι the toggle switch F 7. This means that "1" is impressed on element 5 of the memory section.

Since the counter F 14 remains switched with its fourth element, the gate G522 and then the gates G523 and G99 are opened in the next time slot TCC 6. The element 2 of the flip-flop F 7 is thus switched. This means that "0" is saved for the remaining selection elements, ie 6 to 11. The storage which was carried out for these switching processes corresponds to the line PiVi in FIG. 9. It is understandable that gates are present, such as G512, G520 and G 522 for the individual selection elements. These are denoted by the indices η, η + ι, η + 2 for the timing controls of the three gates shown. It is noted that the timing for gate group G 522 is one time slot later than the corresponding gates G520. The other gates, which correspond to gates G 522, are controlled by TCC3 and f 141, TCC 4 and / Ί42 and by TCC 11 and / Ί49. This ensures that when "τ" is stored for one of the message channel elements 2 to 11, the following pulse switches the flip-flop F 7 and thus makes element 2 effective. For the case in which 11 is the element for receiving a "τ" , it is not necessary to switch over the flip-flop F 7 and make the element 2 effective.

It is assumed that a memory section must be switched as occupied in switch position 1; because otherwise this section, if it is interconnected with the circuit 4, could also be connected to section 1, 2 or 3. It is therefore necessary to change the electrical state of the element 1 after it has been guided past the heads (normal pick-up heads). For this purpose, an auxiliary storage device is arranged with respect to the normal storage device in such a way that the elemental is tapped when the element 1 passes the auxiliary storage device. The switch position 31 has been selected for this purpose for conventional reasons, but any other suitable switch position after the switch position 11 could also be used for this purpose. In switch position 31, potentials are applied to control lines / 32 and / Ί62, as will be described later, and the potential passes gate G 514 (FIG. 3) in order to store the character “z” in switch position 1. As a result of this measure, the memory section is switched as occupied before the section. is detected again by the tapping device. A special timing control for gate G 514 determines the switch position of the auxiliary storage device, where Γ31 represents a possible switch position. From the switching operations between the flip-flop switch F 16 and the TorG5i4 it is understandable why the switch position must be later than the twenty-fourth. The element 2 of the flip-flop F 16 is used for the following reason. When all message contents have been recorded and distributed, the section of memory should be freed. This state is determined by the fact that the elements 20 to 24, which form the group L , are all switched to "0" when the message content has been sent out. Until this occurs, element 1 of toggle switch F becomes effective for one or more of these switching positions, gate G 518 is opened and element 2 of toggle switch F 16 becomes effective. However, if the message content has been transmitted, the element is 1

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the toggle switch Fi is blocked in the switch positions 20 to 24, and thus element 1 of the toggle switch F16 also remains unactuated, and the gate G 514 is closed in the switch position 31. As will be shown later, such a measure allows the storage to be released. The magnetic state of the track elements 1 to 11 corresponds to the lines PN 2 to PN 35 in FIGS. 10 and 11 and is maintained until the passage according to line PiV 36 in FIG. 11 occurs.

At the end of this particular memory section, the pulse Γ 48 is applied to the flip-flops F 15 and F 16 and thus causes the actuation of the elements 1 for the test process to the next memory section. The pulse Ti of the next section reverses the flip-flop F 13 and makes the element 1 conductive.

When element 1 of the section under consideration is tapped again, since it is now magnetized to "τ" and element 1 of flip-flop F 1 is effective, gate G517 in FIG. 3 is opened by pulse Ti and element 2 of Toggle switch F 15 switched. Since the element 1 of the flip-flop .F15 not long is effective, the gate G is closed 515 so that these storage of the flip-flop F 13 can not spread to other message channels by operation of the element. 2 If, however, the pulse TCC 5, which corresponds to the switched-on channel no. 4, is applied to the gate G 516, the element 1 of the flip-flop F 1 and the element 2 of the flip-flop F 15 become effective, so that the gates G516 and G513 open and the element 2 of the flip-flop 513 becomes effective, so that the element 5 retains its memory marker.

Element 4 of counter F 14 also becomes effective, and since element 2 of flip-flop F 13 and element 4 of counter F 14 remain effective for the remainder of the section storage, gates GMi to GM 5 in FIG. 2 are prepared so that the storage of the message elements can take place, as will be described later. Elements 1 and 5 have of course been newly saved as "1" , as previously described, and are retained for the further cyclical switching processes.

Thus, in the next run, the switching state is that as shown in line PN 2 in Fig. 9.

^: posed. Element 2 of toggle switch F 15 switches via gate G517 in time slot Ti, since the occupied state is marked in element 1. It has already been emphasized that the element 2 of the flip-flop F 13 is actuated by TCC 5 and that the switching element 4 of the counter F 14 is also switched. As a result, potential on line STL causes gate GMi to open. Here, potential is applied via line LPi to gate G 4 (Fig. 4), which opens as soon as time slot Γ14 occurs. According to the same approach, three out of four control lines are effective for the GM 2 gates. Since gate GMi is open, potential is applied to element 1 of flip-flop F 2 via gates G4 and G 5. As a result, potential is applied to lines / "21, so that gate G 54 in FIG. 7 opens in the same time segment that gate G 98 follows in switch position t2 of Γ14. Element 1 of flip-flop circuit F 7 also responds, in order to give a positive sign to the drum in the switching position 14, as can be seen from the characteristic curves PN 2 in FIGS.

The flip-flop F1 in FIG. 4 follows the magnetic switching states on the drum track, namely element 1 for the positive state or "1" and element 2 for the negative state or "0". In the time segment T 14, the element 2 of the flip-flop circuit Fi was actuated, and as a result the gate G12 is also opened by the control lines fi2 and / "21. The gate Gn then closes, so that the element 2 of the flip-flop circuit F5 switches.

When the group of time slots TR (TR 15 to TRig) begins, gate G61 in FIG. 8 opens. This is followed by opening of gate G 99 at t2 of element 15, so that element 2 of flip-flop F 7 becomes effective again , whereby a distance for the first and all subsequent switch positions of the time slot R is stored. Thereafter, any positive storage that was in effect in section R is deleted when the storage in question becomes free, as described later.

The element 1 of the flip-flop F1 is actuated when the elements R 19 and L 20 are tapped, since these two elements are normally positive, go In the time segment TL20 , the gate Gii2 in FIG. 5 opens as a result of the potential on the control line fii, and the element 1 of counter C1 responds. While the counter Ci assumes the switch position 1 in the time segment TL 20, the gate G74 and then the gate G 73 open, since the device F10 in FIG. 6 normally assumes the switch position ι. The gate G98 therefore opens in the position tz of the time segment T20, and the element 1 of the device Fy responds in order to store positive or to identify the element 20.

At the beginning of the time segment TL21 , the switching state changes the path to distance, and therefore the element 2 of the flip-flop F1 responds, so that there is no longer potential on the common control line to the gates G112 ... which control the device C ι , so that it remains in the switch position ι. The gate G91 in Fig. 8 opens, and in connection with the time segment TL 21 opens the gate G 95, so that in the position t2 the gate G 99 opens and thus causes element 2 of the toggle circuit F 7 to respond and the storage head to respond Distance registered. No other switching functions occur until switch position F 48 is reached.

Returning to the communication channel in Fig. 2, as soon as the switch position Γ 48 is reached, and with regard to the toggle switch F 8 in Fig. 6, which normally occupies the switching position 2, the gate GL 2 and then GM 5 opens, so that the element 1 of the flip-flop FA opens, whereupon the relay AR responds. The contact απ thus closes the outgoing loop.

The relay BR was actuated in the time slot T 14, in which the gate GL1 with the element 1 of the toggle switch F 7 had opened. The closing of the contact br ι switches the repeater as busy.

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Also in the time slot Γ 48 and depending on the toggle switch F 8, which is in the switch position 2, and the counter F4. , Which is in the switch position 3, the gate G 87 in Fig. 7 opens, which the gate G 98 follows, so that the element 1 of the flip-flop F 7 becomes effective and thus a positive storage for the switch position 48 takes place. Up to the first selection pulse that was picked up by the repeater, successive passes of the section under consideration have passed the pick-up head, which causes the same sequence of switching functions as before, the only difference being that these passes are counted at section R. This • counting has no meaning at this moment, but it is used for timing purposes and takes place in the pauses between the pulses in order to sample the periods between the digits. Before the 'switching operations are described further, the time switch device will be dealt with first.

When PiV 3 is run, nothing happens in time slots T 12, but in Γ13. The element O of the counter C 1 in Fig. 5 is actuated. One can see from this that the journal Γ13 always wants to bring the numerator Ci into position O. The positive storage in element 14 is tapped and stored again. As before, element 1 of flip-flop F 2 in FIG. 4 becomes effective in time slot Γ14. This causes the opening of the gate G 9, since the element 1 of the flip-flop circuit F 1 is actuated, so that the gate G 8 opens and the element 1 of the flip-flop circuit F 5 becomes effective.

At the time slot Ti? 15 opens gate G14 in FIG. 4, and element 2, which switches toggle switch F 6, and in conjunction with element 2 of toggle switch F 1 opens gate G 57 in FIG. 7, since no marking is stored in switch position 15 would. At the same time, the gate G56 in Fig. 7 has opened under the control of the control line / "51 and TR , so that the gate Göo opens and in the time position TRx * and tz opens gate G 98 and element 1 of the flip-flop F 7 opens to store a marker in time slot 15.

In the section Ti? 15 and 1 3 and depending on that the elements 2 of the flip-flop F 1 and F have switched 6, the gate G15, the goal G joins 3, so that the element 1 of the flip-flop F 6 on again opens. In the time slot Ti? 16, the element 2 of the toggle switch F 2 is still actuated, so that the gate G 64 opens in FIG. 8, which is followed by the gate G63. In addition, the gate G99 has opened in i2, so that the element 2 of the toggle switch F 7 responds and stores a distance in the switch position 16. In the remaining switch positions R and depending on the element 2 of the toggle switch F 1, the gate G 64 opens in FIG. 8 and not the gate G 59 in FIG. 7, so that the element 2 of the toggle switch F 7 remains actuated and the distance storage over the whole section R is continued.

With each subsequent pass, the memories are changed in the switch positions R up to the first spacer element. This change adds a 1

: the binary character already stored in the R section. If one considers z. B. the case when the switching position 15 and no other contains a positive storage after the passage PN 3, as just described. As before, the element 2 of the flip-flop circuit F 6 responds via the gate G14 in the time segment TRi $ ; but since element 1 of flip-flop F ι is effective, gate G 62 opens in FIG. 8 in place of gate G57. The gate G62 can open because the element 3 of the device F 4 in FIG. 4 is not actuated. The gates G63 and G99 open, and the element 2 of the flip-flop F 7 switches through to store the distance for the time slot 15 in place of the marking that was previously stamped there. Since element 1 of toggle circuit Fi is actuated, gate G15 in FIG. 4 cannot open, and element 2 of toggle circuit F 6 remains actuated.

In the time slot TR 16, the element 2 of the flip-flop F ι is actuated, and with the switched element 2 of the flip-flop F 6 opens the gate G 57 in Fig. 7. The gate G 56 is also open, because of the element 1 of Toggle switch F 5 in FIG. 4, so that the gates G 60 and G 98 are open and the element ι of the toggle switch F 7 responds in order to store a marker in the 16 position. The element 2 in the flip-flop F 1 is open during the time segment TR16 , so that at t $ the gates G15 and G3 open in order to open the element 1 of the flip-flop F 6 in FIG. This leads to storage during the time period Ti? 17, which in this case means the switching condition for the distance, depending on the opening of gates G64, G63 and G99. It can be seen that the toggle switch F 6 scans the first distance between the switch positions in the R group. When the element 2 of the flip-flop circuit F 6 is actuated, the reverse of what was tapped is stored. When element 1 of flip-flop F 6 responds again, the switch positions are saved as they were tapped. This leads to the addition of ι to the binary character that was stored in the time slots R on each pass. The count of the free revolutions is shown in FIG. 10 by the lines PiV3 to PiV5. During the pass PiV3 contact ar-2 in Fig. 2 via the gate GM 2, the control line LP 2 to the gate G16 in Fig. 4, which therefore opens in the time slot TL 24 and thus the actuation of the element 1 of the flip-flop Fz caused. However, this measure has no immediate purpose.

When the first digit pulse has been received, which consists in opening the loop on wires a, b , this results in a change in the potential on line STL and thus closes gate GMi. As a result of this, the gate G 4 in FIG. 4 cannot open in the time slot Γ14 in the next run, and the element 2 of the toggle circuit F 2 remains actuated. It is necessary to delete the storage in the time slots R , from the period of occupancy to the first pulse. For this reason, the marking stored in element 14 must also be deleted.

As soon as the time segment T 14 is reached, the element ι of the flip-flop F 1 responds. This has no immediate effect; but the control line / Ίΐ

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in connection with the control line / "22 opens the gates Gio and G11 and also actuates the element 2 of the flip-flop circuit F 5. The control line /" 22 in connection with the time slot T14 opens the gate G55 in FIG. 8 and at t% the gateGa .9 to perform a distance storage for element 14.

At the beginning of the period Ti? 15, the gate G 61 in FIG. 8 opens the gate G 99 depending on the control line 52, so that the toggle switch F 7 continues the distance storage. The toggle switch F 7 remains in this position for the other elements R.

In the time slot TL 20, the element 1 of the flip-flop F1 in FIG. 4 responds. The counter C 1 in FIG. 5 is brought to the rest position in the time segment Γ13, as previously described. Gate G112 is now open and element 1 of counter Ci is switched through. The control lines C11 and TL 20 open the gate G 74 in Fig. 7. The element 1 of the toggle switch F 1 is actuated by the marker memory in the element 20. The control lines fii, TL20, / 103 open the gate 108, to the To actuate element 1 of the flip-flop circuit F 10 in FIG. As a result, the control line fioi opens the gate G73, since the gate G74 is open. In the time slot TL20 and i2 , the gate G 98 therefore opens, and the element 1 of the flip-flop F 7 responds in order to store a marking in the element 20.

Via the control line TL 21 in connection with the counter Ci in the switching position 1, the gate G 91 opens in FIG. 8 and with the control line TL gate G 95 opens in order to cause the opening of the gate G 99 and also the actuation of the element 2 the flip-flop Fy. The distance storage is continued via the time slots TL21 to TL 24, section S and time slot Γ31.

It is necessary to save a marker in the switch position 32 of the section ΰΐ in order to received pulse.

It can be seen from this that elements 1 and 2 of device F 4 in FIG. 4 are controlled by control lines fii, T14 and T13, respectively. This means that during the previous runs with a marking stored in element 14, the device F 4 switched from element 1 to element 2 and back during each run. In the control line of the present Γ14 the run the element 1 of the device has responded JP 4 again, as a marker has been tapped and the element 1 of the flip-flop F is connected. 1

In the previous runs with potential at LPi , element 1 of flip-flop F 2 is actuated during section Γ14, and gate G9 is opened in connection with element 1 of flip-flop -Fi. This period of time, but without potential at IPi due pulse interrupt to the loop from in Fig. 2, causes a permanent operation of the element 2 of the flip-flop F 2 and opens in conjunction with the control line fix the gate G10, followed by the gate G11 to the To operate element 2 of the flip-flop switch F 5. When TD 32 is reached and when the counter Ci assumes the switch position ι, the gate G18 opens and continues to open in connection with the control lines / "41 and /" 52, the gate G22, so that the gate G14 opens in the time slot Ti and that Element 2 of the trigger circuit F6 takes effect. The control lines fi2 and / "62 open the gate G 86 in FIG. 7, so that the gates G 85 (from TD 32 to TD 35, ie TD τ to TD 4) and G 98 open alternately. The element 1 of the flip-flop circuit Fy responds to store the marking in the element 32. The first element of the group D ι is used to store the first digit.

In the time interval Γ 32 and if 3 potential from element 2 of flip-flop F 6 opens gate G15 and then gate G3, so that element 1 of flip-flop F 6 is actuated. As a result, the remaining spacer elements 33 to 47 are tapped off and stored again via the control lines / "6i, fi2 and TorG82 in FIG. 8.

In the time slot Γ48 a marking is tapped, so that the element 1 of the flip-flop F 1 becomes effective. It is desirable to retain a memory marker in element 48 until it is necessary to retransmit the stored pulses. This is controlled by the flip-flop circuit F 8 in FIG. 6, which has actuated its element 2 at the moment. As a result, the gate G 87 opens, which is followed by the gate G 98, whereupon a positive storage in element 48 is carried out. go

The next function of the control circuit is to tap the end of the first dialing pulse, which is stored, and to measure the duration of the pulse. When the pulse is tapped, the flow counter for subsection R is brought to the rest position. On the next and subsequent iterations during which the pulse is present, "x" is added to the binary character stored in subsection R in the same way as described above for the post-seizure state before the first pulse was received. If the loop ab in FIG. 2 is interrupted until the last binary storage element Rig is marked, a forced triggering takes place in the next cycle by actuating the third element of the device F 4. This occurs because the second element of the flip-flop -Fi has responded in section Γ13, and the gate G 28 in FIG. 4 is actuated by the control line f62 during the time slot Ti? 19. Element 3 of device F 4 then takes effect. A check now takes place as to whether all flip-flops have returned to the rest position and whether the communication channel is enabled by actuation of element 3 of device F 4. These operations are not described in detail.

It is now assumed that the first selection pulse ends within a normal period, so that the potential at LPz reappears.

The runs PNy, PN8 and PNg mark the count of the runs for measuring the duration of the first pulse, while PN10 shows what occurs after the potential at LP1 reappears. In the time segment T14, the gates G 4 and G 5 in Fig. 4 open alternately to the element 1 of the

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To operate toggle switch F 2. The element 2 of the flip-flop circuit Fi is actuated during the time segment T 14, so that the gates G12 and G11 open alternately in order to open the element 2 of the flip-flop circuit F 5 . Gate G 54 in FIG. 7 also opens in time segment T14, followed by gate G 98 and element 1 of flip-flop circuit F 7, so that positive storage in element 14 is carried out. The elements R must be in the negative switching state

to be brought. This is determined by opening the gate G 61 in FIG. 8, depending on the actuation of the element 2 of the flip-flop circuit F 5. In the next pass PN 11, the counting in the subsection R starts again and continues in this way during the following passes long until the next impulse appears.

The storage of the second pulse takes place during pass PN 12, namely by means of a series of switching operations which are essentially the same as those used to store the first pulse during pass -PN 6. The only difference is that in subsection Di in Fig. 9 a "1" is added to a "1" ; instead of an "o".

It is assumed that the first digit is a 2 and that this digit has now been fully included. However, the device cannot know this, and it must therefore determine the switching state by determining the deviation time, since the last dial pulse was recorded by counting the passes and the last pulse was recorded and a marking was inserted in element L 21.

A pause between the digits is scanned if a marking was inserted in the element RiJ during the counting process. While in section TRij the flip-flop F 7 has been actuated after element 1, gate G 102 opens in time segment TRz ¹ J, which is followed by gate G 104, and element 1 of flip-flop F 9 switches. In order to receive the next digit, the counter Ci must be switched to the second step, and in order to prepare the counting of the first digit, the storage in section D 1 must be converted into the complement of the binary digit, which is achieved by converting each of the elements of the section D 1 takes place.

The element 1 of the flip-flop F 6 is operated and the following elements R are stored.

In the time period TL 20, the element 1 of the flip-flop circuit Fi switches so that the gate G 112 in FIG. 5 opens, which causes the actuation of the first element of the counter Ci. The gate G108 in Fig. 6 also opens, with regard to the control lines TL20, fii, / Ί03, so that the first element of the device F 10 is actuated. Then gate G74 opens in FIG. 7, which is followed by gates G 73 and G 98, so that the marking is stored in element 20.

Through the control lines TL20 and Iß, the device C 2 in FIG. 5 being at step 6, and with the actuated element 1 of the toggle switch F 7, the first switching position of the device C 2 becomes effective. The gate G137 in FIG. 5, which is followed by the gates G136 and Gi 10, opens through the control line TL21 and with regard to the actuated first switch position of the counter Ci. This causes the counter C1 to switch to the second step, and at the same time the gate G103 opens, which actuates the second element of the flip-flop circuit F 9, whereby the gate G110 is closed. The control lines TL21 and C12 open the gate G75 in FIG. 7, which together with the control line / 101 opens the gate G 73. .

The last-mentioned gate in connection with the control line 12 opens the gate G98 in order to actuate the element 1 of the toggle switch F 7 and thus to save a marking in the switch position L 21. Via the control lines TL 21 and ^ 3, the device C 2 switches to the element 5. This indicates that the first digit has been completely recorded and that the transmission of this digit can be carried out on the outgoing loop of the connection.

No switching operations take place up to the time segment TD 32. The complementary storage of the digits is controlled by gates G71, G86, G81, G83 and the associated auxiliary gates. It is noted that the gate G 86 which controls the first element of the flip-flop Fj is switched itself by the second element of the flip-flop Fi, whereas the gate G 83 which controls the actuation of the second element of the flip-flop Fj is switched itself by the first element of the flip-flop Fi is made effective. The storage in each element of the section Di is thus reversed. The sequence of the inversion of the digit is controlled by the auxiliary gates. The control lines TD determine which digit is reversed, while the counter Ci determines that only one digit in a time unit is converted in the correct sequence. Gate G 71 decides in which periods of the entire switching processes these conversions can take place, while gate G 86 controls the inversion of the elements. The first element of the flip-flop Fn in FIG. 6 was actuated by the control line TL 20 through the first element of the flip-flop F 9 via the gate G109.

It can be seen from this that, under the current switching circumstances, gates G 65, G 71 and G69, G81 remain open during the entire section Di, whereas gates G 86 and G 83 open alternately, taking into account the existing memories in the elements of section Di, in which distance and marking is embossed. This causes the reverse re-storage. In the following runs, a coincidence occurs between TDi (TD 32) and the second element of the counter Ci before the next digit is received. In this case, however, the first element of the flip-flop Fn is not actuated because the first element of the flip-flop F 9 did not switch in the time segment 77120 (see gate G109) because Ti? 15 ensures that the second element of the flip-flop F 9 switches. Gate G102 is through

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TR 17 is not open for most of the following runs because the second element of the flip-flop circuit F 6 is not actuated. During the remainder of the time counting through the section R , the switching state is obtained that the elements R 15 and R 16 both contain markings and the section R 17 represents a distance, but only if the sections R18 and Rig are included. If at the end of the complete count all elements R denote distances, then elements R15 and i? I6 denote markings and elements R 17, Ri8 and Rig denote distances.

In order to prevent the element Rig from being marked at the end of the count, it is

. waits until the next break in the voice line occurs.

The element 2? 18 or Rig opens gate G101 as a marker in order to actuate element 2 of toggle switch Fg and also to leave element 1 inactive, so that at a point in time TL 20 the gate

ao G109 does not open.

After the complete count in the section R , the elements Ä15 and i? I8 are negative in the next run, because the element 2 of the flip-flop F 6 in the time period Ti? 15 is not actuated. However, when the time segment TR 19 is reached, the gate G150 in FIG. 4 is opened in order to switch the element 1 of the flip-flop circuit F 6. As a result of this, the element 1 of the flip-flop Fy is actuated in order to store a marking again in the element Rig. If the speech loop is interrupted, the element 2 of the toggle circuit Fz in Fig. 4 remains actuated and since the element T 14 had marked the loop state, the gates G 10 and Gn open to operate the element 2 of the toggle circuit F 5 zn. As a result of this, gate G56 in FIG. 7 remains closed during time segment TR and gate G 61 in FIG. 8 opens in order to cause the storage of a distance in time segment TR.

From this it can be seen that when pulses are transmitted and by adding "1" to the binary characters in section Di, the first digit is completely transmitted for each transmitted pulse if all elements of section Di contain markings.

Each pulse is started during the last element position of a pass and is maintained for four passes, which are counted by the section S. As each digit is sent out, its storage in section L is removed.

The transmission of the first pulse is initiated by converting element 48 from a marker to a distance. As previously explained, the element S of the counter C 2 becomes active during the passage and, as a result, the gate G120 in FIG. 6 is opened in the time slots TS27 and ti , so that the element 1 of the toggle circuit F 8 is actuated. Thus, in the time segment Γ48, the gate G88 in FIG. 8 is opened by the control line f8i , as a result of which a distance is stored in the element 48. The same control combination T48, f 81 opens gate GL 3 in FIG. 2. As a result, potential is applied to gate GM 6. It will be recalled that the counter F 14 in FIG. 3 causes the identification of the message channel in FIG. 2 to be stored. At the moment the counter F 14 is in the switch position 4 and thus applies potential to the gate GM 6. Furthermore, the elements 2 of the flip-flop circuits F 13 and F 15 are still actuated, so that the gate GM 6 opens. This is followed by the gate GM 8 in order to actuate the element 2 of the toggle circuit FA , which switches off the relay AR in order to initiate a pulse transmission with contact on.

In the following runs, further digit pulses can be received and stored in the same way as previously described, with the difference that the next digit is stored in section D 2, etc. We will now turn our attention to the pulse transmission, which is initiated in the switching position 48, line PN 20 in FIG. The following runs are shown graphically in FIG. The counting processes, which in the lines PN 21 .... for section R are skipped so that the first switching we will consider is the counting of the first pass of section S. The waste from the relay AR opens the contact ar 2 and thus removes the negative potential from the line LP2 in Fig. 2. The element 1 of the flip-flop F 2 in FIG. 4 can be operated through line LPi in the switching position Γ14 over the gate G 4 , but in any case the element 2 of the flip-flop F 2 is actuated again during the time segment TR. By removing the potential from the line LP2 , the gate G16 does not open in the section TL 24, so that the element 2 of the flip-flop F 2 remains actuated and the gate G58 in FIG. 7 opens in the time period TS. The element 2 of the flip-flop F τ is conductive, since the group of element positions S is empty, that is to say that all elements are marked as distances. Gate G17 in FIG. 4 was also opened by potentials TS 25 and / "22 and gate G14 was opened with ti in order to actuate element 2 of toggle circuit F6 . As a result, gate G57 in FIG. 7, and with With the help of gate G 58, gate G 60 is also unlocked, so that element ι of flip-flop Fy becomes effective via time potentials tz and G 98 and a marking is thereby stored in element S 25. Opens with time potentials t% and fi2 the gate G15 in Fig. 4, so that the element 1 of the flip-flop circuit F 6 responds again and thus prevents the storage of the markings in the element positions 26 to 30. These time elements mark a distance so that the time potentials at fi2 and f6i the gates G. 64 and G 63 in Fig. 8. The element 2 of the flip-flop circuit Fy thus responds in order to re-register the distance storage for these elements.

It is necessary to store the fact that a pulse has been sent out so that after adding a pulse in section D1 during the current cycle, no further pulses will be added in section D1 until. the transmission of the first pulse is carried out completely and the transmission of the second pulse is started

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has. This storage is carried out in element 31 between sections 5 and D 1.

The time pulse combination TS and / "22 has activated the element 1 of the flip-flop circuit F 12 in Fig. 6 via the gate G125, so that the gate G89 open via the time potentials Γ31, fi2i and /" 22 and thus via t2, the gate G98 the Element 1 of the flip-flop F 7 is actuated in order to cause a marking to be stored in element 31. A pulse has now been added in section Di.

In the time slot TD 32 and in the switch position 1 of the counter, the gate G 23 opens in Fig. 4 and in connection with the time potential / Ί21 (Fig. 6) opens the gate G27, so that the gate G 14 opens with ti and TD32 and the second. Element of the trigger circuit F 6 is opened. It is now necessary to change every element of section D 1 including the first distance. When the element 32 has stored a distance, the element 2 of the toggle circuit Fi is actuated, and with the switched element 2 of the toggle circuit F 6 , the gate G 86, which is followed by the gates G 85 and G 98, opens the element 1 of the toggle circuit Press Fy to save a marking. The element 1 of the flip-flop circuit F 6 responds again through the time potentials TD 32 and i3, because the element 32 was tapped as a distance. This prevents any further change in the re-storage of the elements TDi . In a special case, which is shown in the line PN 21 in FIG. 11 ', the element' 32 contains a marking and was relocated to a distance by opening the gate G 83 in FIG. This was done through the potentials fii and f62, which acted on gates G98 and G99. The element 2 of the toggle switch F 6 remains actuated, so that the element 33, in which a distance is stored, is converted into a marking with the help of the gate G 86! was, as already described. The element 1 of the toggle circuit F6 is now actuated to prevent the reversal, so that the elements 34 and 35, in which markings have already been embossed, receive new memories through the gate G 84.

The remaining elements 36> to 48 are stored again as they were tapped off, with a view to the possibility of the digit storage being carried out further in section D 2.

In each of the next three ₍ passes, a pulse is added in the group of the element position S, but neither in element 31 nor in section D ι a change takes place because the transmission of the first pulse is still taking place.

On the line PN22 in FIG. 11, when the section 5 is reached, the element 1 of the flip-flop Fi responds, specifically in the time element 25. The element 2 of the flip-flop F 2 has it again when it was necessary in the time slot TR addressed, so that in the time slot TS 25 the gates G17 and G14 open and the element 2 of the flip-flop switch F 6 operate. Gate G62, followed by gate G 63, opens via control lines / "62 and fix , and element 2 of toggle switch F 7 responds to save a distance. Element 2 of toggle switch F 6 remains actuated, so that in time element 26 when element 2 of flip-flop F 1 is actuated, gate G57 in FIG. 7 opens and, in conjunction with gate G58, which was opened by control lines TS and f22 , gate G 60 opens to element 1 of the flip-flop F 7 to cause a marking storage. Element 1 of flip-flop circuit F 6 responds again via gates G15 and G 3 via t $ , and the remaining elements of section 5 are newly stored as they were tapped.

During the passage PN21 (Fig. 11), the element 1 of the flip-flop F 12 in Fig. 6 was actuated by the control potentials TS and / "22. The element 1 of the flip-flop F 12 remains addressed via the element 31, , which is referred to as element SCM , and beyond to section Di. During the passage according to line PN 22 , element 2 of flip-flop F 12 is actuated in time segment Γ31, since element 31 was tapped as a marker and the potential on the control line is fixed so that gate G126 opens.

Also in the time slot Γ31 the gate G89 in Fig. 7 has opened by the control potentials fixed and / "22, so that the element 31 is again stored as a marker. Since the element 2 of the toggle switch F 12 is actuated, the gate G 27 4 are not opened, and element 1 of flip-flop F6 remains actuated. As a result, gates G 84 and G 82 in section D χ store the elements as they were tapped.

In the line PiV "24 four pulses over a total, added so that the time element 27 receives a marker. Time potentials Γ 27 and ti in connection with the element of the counter C2, which is still operated, opens the gate G120 in Fig 6 to actuate element 1 of flip-flop F 8, as before, but as a result of time potentials TS 27 and i3, and with regard to element 1 of flip-flop Fy, which is actuated to store a marker, the gate opens G124, which is followed by gates G123 and G122, so that element 2 of flip-flop F 8. Element 2 of flip-flop F 6 in FIG 47 are stored again as they were tapped off. However, in the time slot T 48 and as a result of the actuated second element of the toggle circuit F 8, the gate G 87 opens and a marking is stored in the time slot element 48. The control potentials / ^ 82 and T 4th 8 also open the gate GL 2 in Fig. 2, so that the gate GMs opens to energize the flip-flop FA with its first element and the relay AR so that the contact ar 1 closes to determine the first pulse. In addition, the contact ar 2 is closed, which applies voltage to the line GM 2, which replaces the potential on the line LP2 . "

During the passage PN 25, the first element of the flip-flop F 2 is actuated in the time slot TL 24 , because the line LP2 the gatesGiö and G5

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opens. The gate G17 in Fig. 4 is therefore blocked in the time slot rS 25, and the element 1 of the flip-flop F6 remains actuated. It is now necessary to delete the marks stored in time slots 5 and Γ31. The first element S in the time slot 25 is a distance, since the number 4 is stored in the time slot 5, and consequently the gate G 64 in FIG. 8 is also opened by the control potentials f6i and / "12. Then the two gates come G 63

ίο and G99, and the second element of the toggle switch Fy is actuated in order to re-store the distance. Since the first element of the flip-flop F 2 is operative, the gates G57, G58 and G59 and G89, which control the element 1 of the flip-flop F 7 for the time slots S and Γ31, cannot operate the first element of the flip-flop Fj , and it will Therefore, a distance storage over the time slot 5 for the time slot 'Γ 31 is carried out. During the time slot TDi the first element of the flip-flop F 6 remains actuated because the element 2 of the flip-flop F 12 is still actuated and for this reason the gate G 27 in FIG. 4 cannot open. The gates G 84 and G 82 now control the re-storage of the elements of the section Di as they were tapped, since the control potential / \ ii opens the gate G84 to open the first element of the flip-flop F 7. The control potential fi2 opens the gate G82 in order to operate the second element of the flip-flop Fy. The time slot element 48 is stored again as a marker via the gate G 87, and the relay AR remains activated.

Track PN 26 is used to remove the second pulse by removing the stored marker in timing element 48, as was done previously with track PN20. In the time slots TS2y and 1 1, the element 1 of the flip-flop F 8 in FIG. 6 by respective control potentials actuated, as before, and it also remains actuated, as in the time slots TS and t $ 27, neither the control potentials fyi still / "n are effective so that the gates G124, G123, G122 remain locked. Upon reaching the timing element 48 8 opens the TorG88 in Fig. consequence of the control potentials f8i and Γ48, so that a distance storage is done with element 2 of the flip-flop Fy.

Furthermore, the control potentials f8i and Γ 48 open the gates GLs, GM6 and GM8 in order to operate element 2 of the trigger circuit FA and thus the relay ^ 42? throw off. This initiates the second impulse by opening the contact on. As usual, the pulse is retained over the next four runs, namely in tracks PN26 to PN29. The processes described for the first pulse occur here, with the only difference that section D 1 receives an additional pulse which completely fills the section, ie it leaves this section fully marked, whereby it is determined that the sent pulse is the last one for the digit. Accordingly, the timing elements 12 and 13 are converted into a marker. Section Di is completely filled in track PN2y. Consequently, at the timing TDi, although the gate G129 in Fig. 5 is in the track PiV 28 opened by the control potentials TDx and C31, the gate G128 is not opened because the control potential / "12 is not effective, so that the element 1 of the multivibrator Fg remains operated., the gate G127 in Fig in the timing Γ48. opened by control of the potential / "91 6 and the flip-flop circuit F operates the element 1 23. the auxiliary memory registers a marker in the timing element 12, as before for the element 1 described in the track PiVi. The flip-flop F 23 is reset to the element 2, which was actuated by the control potential £ 3.

During rotation PN 29, gate Gi in FIG. 4 is actuated by element 1 of flip-flop circuit F 1 in time slot T12 , which opens and element 1 of flip-flop circuit F 3 switches on. In the time slot or in the element Γ13, the gate G51 in FIG. 7 opens as a result of the control potentials / "31 and Γ13, whereby a marking is stored in the element 13. As before, the gate G127 opens in the time slot Γ48 when the control line fgx is active. This causes the auxiliary memory to insert a marker in the time element Γ12.

During the rotation PN 30, the tapping of the marking in the time element 12 causes the element 13 to pick up a marking again, and the auxiliary memory stamps a marking in the time element Γ12 at the required moment. In the meantime, the count S has stored the fourth run for the pulse 2, so that the element 27 is marked. As with the revolution PN 24, a marking has again been made in the element 48, so that the relay AR in FIG. 2 has picked up in order to terminate the regenerated second pulse and thus also the first digit. ·

It is now necessary to measure a pause between the digits passed through a group of Timing elements S is formed.

As it is apparent from Fig. 11, is the inclusion of the second digit of the message channel in Fig. 2 not yet been initiated, and the traces PN 21 to PN 30 show the timing element R, which for counting the runs until the reception of the second digit is used. Section R counts more than once when the second digit is delayed for inclusion. The reception of the second digit has been omitted in FIG. 9 in order not to make the diagram unnecessarily complicated. It is assumed, however, that the recording of the second digit is carried out with the similar switching functions as shown in tracks PN 6 to PN 20.

The smallest pause between two digits comprises thirty-six runs after the stored marking of the first digit in the element curve L is deleted, ie is newly stored as a permanent interval in order to enable the second digit to be retransmitted after reception. The storage in the time slot S is held so that the count of the pause is from 4 to 40. In the track PiV31 the first element of the flip-flop F 1 is actuated again, which is followed in the time slot T12 by the first element of the flip-flop F 3, so that in the time slot

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TS 25 the control voltage / "31 opens the gates G17 and G14 in order to operate element 2 of the flip-flop circuit Fb.

The control voltages TS and / "31 open the gate G58 in FIG. 7. Since the time element 25 is effective as a spacing, the control voltages f 62 and fi2 open the gate G57, so that the gate G60 is then opened and a marking is saved This adds a 1 to the storage in the time slot S. As before, the element 1 of the flip-flop circuit F 6 is actuated in the time slots TS 25 and t3 in order to enable a re-storage for the rest of the time slots S. Since the relay AR again has addressed potential to the line LP2 in Fig. 2 and 4 is placed, so that the first element of the multivibrator Fz is effective at the timing TL 24th 8, the gate G 90 in Fig in the timing Γ31. by the control voltage / 21 is opened and the element 31 is saved as the distance again, the remaining time elements are saved again as they were tapped.

There is no change on tracks PN 32 to PN 65 except for the addition of 1 in section S for each pass. Since the marking storage in the element 28 was carried out during the track PN φ , the control potentials or time slots open the gate G107 in FIG. 6, and the gate G106 actuates the element 2 of the flip-flop circuit Fio. Since the marking is stored in the time element 30, the control potentials / "71, TS 30 and / Ί02 open the gates Gin and G103 in order to actuate the second element of the flip-flop circuit F 9 in FIG.

As a result, no control potential occurs on line fgi in time slot 2 "48. The flip-flop F 23 with its element 2 therefore remains actuated. In time slots TS 28 and TS 30, gates G107 and Gin open by a distance into the time element 12. This is done by actuating the elements 2 of the flip-flops Fg and .F10 by means of markings in the time slot elements 28 and 30.

In the case of the PN 67 cycle, the time elements have 12

and 13 a distance is stored, the element 12 being tapped as the distance, but the element 13 being evaluated as a marker, since the control potentials 13 and the second element of the flip-flop Fi open the gate G 2 to operate the second element of the flip-flop F 3 . The control potential / "32 opens the gate G 52 in Fig. 8 in the time slot Γ13. Also in the time slot Γ13, the control potentials T13, / Ίΐ and /" 32 open the gates G105 and G106 to the time element 2 of the flip-flop circuit Fio in Fig 6. Satisfy. In the time slot TL20 , the gate G 95 in FIG. 8 is opened by the control voltages / Ί02 and TL20 in order to store a distance in place of an earlier marking. Gate G138 in Fig. 6 is opened by the control voltages / Ί02 and £ 3. The gate G108 is then opened by the control voltages TL20 and fii, so that the element ι of the flip-flop F 10 responds.

The gate G 75 in FIG. 7 is opened by the control voltages TL21 and ci2 and the gate G 73 is opened by the gate G75 and the control potential / "ιοί, so that a marking is stored in the time element 21. In the time slot TL22 the gate G92 is opened by the control potential c 12, which in turn opens the gate G 95 in order to store a distance. The remaining time elements of the section L are newly stored as they were tapped Clear.

In the time slot TL 24 and above LP 2 , the

Gates G16 and G 5 open to open element 1 of flip-flop F2 . In the time slot TS 25, the gate G 58, which is caused by the tensions / "22

i or / "31 is controlled, does not open, so that too Gate G60 remains blocked. In this way, the storage of a marker in the section S j prevented. A distance is therefore stored because the gate G 64 in FIG. 8 is controlled by the control voltage

/ "12 and /" 6i is open. Furthermore, element 2 of the toggle switch F η is actuated via the gate G 63, which remains actuated beyond the time segment S. ■ '.

It is now important to describe in detail the storage and transmission of the following digits; but first the successive switching functions controlled by the counters Ci, C2 and C3 are dealt with. The second digit is received with the counter Ci in the time slot 2, and at the end of the storage, the counter Ci is controlled by the gates G137, G133, G134 and G135, which successively in the individual counting positions cn to c 14 or in the time slots TL21 to TL 24 are open.

The counter C2 is used to determine whether another digit can be transmitted. The control gate G118 can be opened in each of the two successive time slots TL in which the marking by the control potential is stored in the switch positions 0 and 1 during a cycle of the counter C 2, so that the counter C 2 advances from the switch position Ό to 1 and from 1 to switching position 5, if the switching conditions require this. The counter C 2 in the switch position S allows the next digit to be transmitted. The counter C 2 is set to 0 in the time slot Γ12 for each cycle, namely by a potential which is applied directly to the element 0 of the counter C 2.

The counter C3 counts the transmission of the digits. The advancement of the counter C 3 to the next switch position in any time period depends on the presence of switching conditions, such as. B. are shown in the track PiV 67 in Fig. 11, in which the first time slot L represents a distance.

The counter C 3 successively counts the switch position from 20 to upwards and is reset in each subsequent switch position T 12. In such switch positions, the control line / "72 is effective. As already mentioned, the counter C 2 is in the rest position, so that in the time slots £ 3 of the successive switch positions ΓΖ, 20 to TL 24 when the control lines / ^ 72 come into effect, the counter C3 receives an impulse and advances it step by step, however, since switch position TL 20 is free in track PN 67 but switch position TL 21 is occupied

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in the switch position Ti 21 the control potential / "71 effective instead of the control potential /" 72, and the counter C 2 switches to position 1 so that the counter C 3 does not switch to the empty switch position L later due to the active control voltage / "72 can (e.g. £ 22 to L 24).

As before, the receipt of the second digit is stored. Since the counter Ci is now in the Switch position 2 is the gate G74 in FIG. 7

ίο not open in the time slot Ti 20 of the next run after receipt, nor is the gate G91 in Fig. 8 in the switch position TL 21, but the gate G 75 is opened in the time slot Ti 21 by the control voltage c 12 to to store a marker in the time slot Z 21.

While in the case of the first digit the counter Cx was in the time slot 1, so that in the time slot TD 32 the control voltage cn has opened the gate Gi8 in FIG. 4, in the case of the second digit the gate G18 is not open, but In the time slot TD 36 the control potential at ci2 opens the gate G19, and in this way the first pulse of the second digit is stored in the switch position 36 instead of in the switch position 32, and the number is registered as a whole in the time slot group D 2, which contains items 36-39.

At the end of the second digit, a marker is inserted in the time slot TL 22 after the counter Ci in its third. Switch position has been brought by opening the gates G 76, G 73 and G 98 in Fig. 7. The second digit is reversed and sent in the same way as the first digit, with the only difference that the time slots TD 36 to 39 can be used in place of the time slots TD 32 to 35. The remaining digits are stored in a similar way and sent out again.

At the end of the transfer, the marking in the switch position L 21 is removed. After receiving the third and fourth digits, markers are inserted into time slots i23 and i24, while am. At the end of the transmission of the third and fourth digits, the markings in time slots i22 and £ 23 will be removed.

When all message contents have been received and sent, storage is no longer necessary and must therefore for the assignment to another message channel, which is a storage wishes, free, to be made. The switching processes required for this are carried out as follows.

. It can be seen later that elements 20 to 23 of section £ are in the "0" state. As a result is effective when these elements through the switching element 2 of the flip-flop F 1, at this time. Consequently, the gate G518 in FIG. 3 is not opened in the time segments TL 20 to 23, so that the element 1 of the flip-flop circuit 16 is left effective and the gate G514 remains closed in the time slot T31. Here, "o" (distance) is saved in element position 1, which indicates that the memory device is now free. It is now necessary to delete the storage in time slot TCC 5. This is done during the next cycle, whether a calling channel 1, 2 or 3 is switched on in the meantime or not. The next time element 1 of the flip-flop Fx is tapped, so that the second element of this flip-flop becomes effective. The gate G517 is not opened, so that the element 1 of the toggle switch F 15 in FIG. 3 remains actuated. If nothing else occurs before the switch position TCC 5 is reached, the gate G 516 remains closed and the element 1 of the toggle switch F 13 remains effective, although the element 1 of the toggle switch F τ wants to operate the element 2. Thus, the gates G520 and G521 in FIG. 8 are opened, since the device • F 14 is still in the switch position 4 and the element 2 of the toggle switch F η is actuated, so that the storage "0" occurs in the time slot 5. The storage is now free for other news channels. '

If the channel 1, 2 or 3 has occupied the common device, the switching element 1, 2 or 3 of the device F 14 would be actuated, which is followed by the second element of the toggle switch F 13, namely by opening a gate, which the gate G511 is equivalent to. The gate G522 is opened for the switch positions i, 2 or 3 of the device .F14 in the time slots 3, 4 or 5. "0" is saved for time elements 5 to Ii.

If the message channel is disconnected from the memory device after all memory contents have been transferred, the relays BR and AR remain in the actuated state, so that the elements 1 of the flip-flop circuit FB and FA are conductive at this point in time.

If the connection is triggered under certain circumstances, the drop of the relay RR actuated in Figure 2 rri by closing the contacts and RCC, which open the gates GM 7 and GM 8 and hence the elements 2 of ^the:. Actuate trigger circuit FB and FA, releasing the elements ι of the flip-flops FB and FA. The relays AR and BR are therefore released and the contact br χ opens to remove the busy earth from the c-wire of the incoming connection line.

Three parts of the circuit arrangement have been selected for the description, since these parts are characteristic of the rest of the circuit arrangement. These are gates G62; G63 and G64 in FIG. 8, which are shown in detail in FIG. 12, and the flip-flop circuit F 8 with the associated circuits of FIG. 6, which are shown in detail in FIG. Furthermore, the counter C 2 from FIG. 5 is shown in detail in FIG.

The three gates in FIG. 8, which for the purposes of description form part of an extremely complicated gate network, are interconnected with the flip-flop circuit Fy which controls the storage. In their basic arrangement, the gate circuits used are simple rectifier coincidence gates. In such gate circuits a common point, which is generally the starting point of the circuits, is connected to a number of control points and to a source which provides a positive bias potential. The connection to the bias source contains a resistor and a voltage

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binding to the tax authorities, each of which contains a rectifier.

. The potential of a; control point can be two different Assume values, one of which prevents the activation of the gate circuit because it is at or close to earth potential, and the other

". Value, which, make the gate circuit effective can because it represents a positive potential. If in the cases in which many gates are used the control point is at the cathode of a cold cathode tube, the control potential is on the ineffective. Value when the tube is not ignited and at an effective value when discharged the tube.

The rectifiers are connected to in the Forward direction of. .the bias source via the

... s lead rectifiers to the control points. Therewith the effect of the rectifiers is to keep the common point at a potential, which is positive relative to the control points. The arrangement is made so that if the same positive or effective potentials are simultaneously at all control points of a gate circuit, the Potential at the common point is substantially equal to the potential of the control points. Thus can it can be seen that the common point, i.e. H. the starting point of the gate circuit, only a positive potential assumes if positive potentials are present at all control points at the same time. As it was found is this potential at the common point is equal to the positive potential of the control points.

The connection from the common point of a gate to the next stage of the arrangement sometimes includes a rectifier with the forward direction from one common point to the next Stage of the circuit arrangement. Such rectifiers serve as decouplers and are required where the same point in the circuit is controlled via any of several independent gates can. They are used to ensure that a gate does not have a number of other gates connected to that point can render ineffective.

Returning to FIG. 12, it can be seen that the gate G 64 is a simple gate of this type, with two control lines, one from the point fixed and the other from the point f 61. These two points lead to tubes Fu, not shown and F6.1. When both of these tubes discharge, their cathode potentials will be biased positive and rectifiers MRx and _{MRq 1 will} be biased positive. This means that the common point assumes a positive potential, which is via the decoupling rectifier. Wed? 3 is applied to the grid of the cathode amplifier tube CFA. The grid of this tube is connected to a negative potential via a resistor Ri , so that the tube CFA nor-. sometimes ^ does not lead:

If the gate circuits G 64 or G 62 provide an output voltage ■ ·. discharged, the tube CFA becomes conductive, so that a positive ■ potential appears at its cathode. ;; ₇ -

; Now that will; second gate G62, which controls the tube CFA , .-, consider .. The. Fig. 8 shows that there are three control inputs, and indeed fx.x, f6.2 and / "4.3, the last of which is a braking input, ie if the input /" 4.3 discharges, the gate is independent of that State of the other inputs ineffective. To achieve this, the input voltage /^4.3 is reversed and used for control. The reverse circuit uses a single triode V, the anode of which is connected to ground potential via a rectifier MR 4 and to a positive potential of about 60 volts via a resistor R2. The cathode of the tube V is connected to a resistor branch R 3, i? 4, which. lies between a negative supply potential and earth. The control grid is connected to a point of the resistor branch R 5 ,: R6 , which lies between a negative supply potential and the control point / "4.3, ie at the cathode of a tube -F4.3, not shown.

The circuit elements are dimensioned so that, when the tube F 4.3 has not ignited, its cathode voltage is at or near the earth potential, so that the tube V is switched off. This means that the anode voltage is determined by the positive source which is fed in via the resistor Rz. In these switching states, the coincidence of control lines fxx and f6z causes gate G62 to release an output pulse. When the tube .F4.3 discharges, its cathode voltage becomes positive, so that the tube V conducts. The rectifier MR4 then holds the anode potential to earth, which brakes the gate, regardless of the control lines fx.x and / "6.2.

The resistor R2 and the rectifier MR $ can be omitted without the circuit operating incorrectly. But the arrangement shown results with the resistor R 2 and the rectifier MT? 5 better results. .

The relatively simple embodiment, which was extracted from FIGS. 7 and 8, gives a picture of how this goal network is actually constructed. The cathode amplifier tubes are similar to the CFA tube and are used at various circuit points in order to achieve the necessary relationships. However, with regard to FIG. 12, it is not a great difficulty to fully develop the network of FIGS. 7 and 8.

The circuit in Fig. 13 will now be described. The flip-flop, which has two gas-filled cold cathode tubes, is coupled to the capacitor C 1 at the anode. The control electrodes are connected via resistors to a source of the bias voltage B , the value of which is smaller than the normal supply voltage, e.g. B. 170 volts with a supply voltage of 350 volts. The bias cannot ignite a tube. When a positive pulse is applied to the control electrode of a non-ignited tube, that tube will discharge. The anode circuit causes a sudden voltage drop at the anode of a freshly ignited tube, which is applied to the anode of the other tube via the coupling capacitor Ci and extinguishes the previously ignited tube.

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The TorGi2O, which is connected to the F8.χ tube, is a simple three-gate. The tube F8.2 is controlled by the gate G122, which contains two rectifiers, which together form a mixer 5 or one-gate. One input, which can switch the tube F 8.2, comes from TL24, while the other input comes from gate G123. The rectifier MR6 , as shown, functions as part of the gate G 122 as a decoupler for the gate G123.

The gate G 123 is a three-gate, one entrance of which is denoted by ^. The inputs TS 27 to TS 30 are switched during one of these four time slots so that the element pulses are applied to the four rectifiers, which together form a mixing port. A positive potential across any of these inputs biases the rectifier MRy so that the gate can operate. The other input circuit belongs to gate G 124, which is a simple single or mixed gate with two entrances.

. The last circuit to be described relates to the counter C2, which uses the same tubes as the tube F8. It is assumed that the pulse T12 has brought the counter C2 into the switching state in which the tube

25- C2.0 discharged. The common feed line to the other tubes runs from the cathode of tube CFB, which will be described later. A coincidence gate of simple construction is located between the successive pairs of tubes. As soon as a positive feed pulse occurs, the rectifiers MRxo and MR 11 are positively biased. However, at this moment the rectifier MR 12 is positively biased because the counter stage C2.0 is conducting. For this reason, the gate MR 12- MR 10 gives an output pulse via the capacitor shown, so that the counting stage C2.ι ignites. The increased current which runs in the common line across the load resistor i? 5 causes an increased voltage drop, which causes the counter stage C2.0 to be cleared. Counting stage C2.1 is now conductive.

Before the counting stage C2.1 fired, it was yours Cathode potential at or near earth, so that capacitor C 5 has been discharged. When the counting level C2.1 ignites, does its cathode potential become positive and thus tension the rectifier Mi? 14 before. As a result, the capacitor C 5 is charged by a positive potential. This so-called slow working output acts like a delayed output from counting stage C.2.1.

With the next pulse on the common feed line, both rectifiers MR 13 and MRn are positively biased, whereby the switching stage C2S ignites and the switching stage C2.1 goes out. This switching state lasts until the next pulse T 12 occurs, which brings the counter to its rest position. The cathode follower tube CFB emits a positive output pulse when its control gate G118 sends a positive pulse onto the grid. This gate has two simple control lines 1 3 and fjx and two mixed control gates.

: The circuit examples shown give a sufficient idea of the real circuits if one adds the pulse diagrams also shown. However, a few additional remarks are necessary. There are three circuit arrangements). consisting of three elements, namely Fx ¹ J, F 4 and Fxo in Figures 2, 4 and 6, which must be viewed as if they were flip-flops. These circuit arrangements, which represent simple multi-stable registers, could consist of three tubes, the anodes of which are connected by rectifiers, ie a three-tube design similar to the arrangement F 8. The multi-stable register F 14 could be a conventional circuit, such as, for. B. the counter in Fig. 14, but with more complicated gates between the tubes.

The five-stage counter C 3 could consist of gas-filled multi-cathode tubes. This would. would result in a useful arrangement since such a tube can be considered economical.

All of those arrangements which have yet to be described are particular embodiments of memory or storage devices, which are shown schematically in Figs. This are matrix devices arranged according to coordinates.

Such a matrix arrangement contains a number of cores of magnetic material, each of which can be brought into one of two stable states, usually referred to as positive or negative magnetizations. A core is required for each element. In the present case, ten memories must be provided, each of which consists of forty-eight elements. That would make a total of 480 cores. As shown, the cores are arranged in η rows, each row containing m cores so that one has m · η cores arranged such that the cores form m columns and η rows.

Each core carries three windings, namely two steering windings and one tap winding. It can be seen from FIGS. 15 and 16 that the uppermost windings of all cores are connected to a line which forms a common output connection. These windings are the tap windings and the common line is considered the output line. The other windings, as ^from: apparent the figures, coordinates are connected to each other.

To select a particular core, e.g. B. the core m + 2, the 'correct vertical line V and the corresponding horizontal line H must be detected. Each of the two coordinates absorbs half the current that is necessary to change the magnetic state of the core. In the example chosen, the direction of the current is chosen so that the core is positively magnetized. Thus only the core m - \ - 2 can be influenced, and it can obviously only be changed if it was already negatively magnetized. . The magnetic change so produced causes a large change in the magnetic flux across the tap winding of the corresponding core, releasing an output pulse. The storage for this is described later. . . ./ .. '.

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The three control pulses ti, t2 and t ^, which have already been mentioned, are used for control processes. It is now considered how and when the pulses t2 are generated. The counter C 5 has η switch positions, specifically corresponding to the number of cores per column. The counter C5 is switched with each cycle by the control lines C $ m and £ 3 via gate G401. In the present case, m = 48 is assumed, ie the number of element positions per storage. In this case the outputs from the counter C5 can be used to produce timing pulses which are used for control purposes. Likewise, η is equal to the number 10, ie the number of memories. It is clear that any other value for m and η can be assumed. An alternative is e.g. In 24x20 if two rows were necessary for each storage.

The outputs from the counter C 5 are sent to the

Gates were put in place to control the currents that flow in the column windings. The outputs of the counter Cδ are applied to those gates which control the series windings. Looking at a ferromagnetic core, the amplitude of the two currents, which act in an additive direction, is large enough to generate a force large enough to influence a core beyond the bend of the hysteresis loop. However, one of these currents alone is incapable of producing this force. The tapping process consists in magnetizing the selected core in a positive direction, regardless of its previous state. Thus, if the previous state was a positive magnetization, no output pulse takes place; but if the previous condition was negative, an output pulse is sent from the tap winding. It is further noted that the pick-off windings are arranged in such a way that, in other cases, impulses from others; Polarity, which are able to overcome accumulated demagnetizing forces.

It is assumed that the distributor formed by the counters C 5 and Cb energizes the units m and η. The pulse <3 of this element position switches the counter C 5 to the switching step i, and at the same time the gate G 401 opens, so that the counter C 6 comes to the switching step 1 '. At time tx , gates G402, G403, G404 and G405 are open so that the first column of windings and the first row of windings each receive a current pulse. As already described, only the core 1 can be made effective, and since the direction of the pulse is intended for a positive magnetization, no output impulse occurs if this core was already positively magnetized. However, if this core was already negatively magnetized, an output pulse is emitted.

Although the connection in which this circuit effect is achieved is not shown, the output pulse produced in this way is applied to both the control circuit and the input circuit of FIG. The input circuit is such that the core is positively magnetized if it is to be left in the interrogated state. No output pulse is sent. If, on the other hand, the core is to be left negative, a negative pulse - tz is generated. In the latter case, gates G407 and G405 as well as G406 and G403 are open. Therefore, the pulses run through the same windings in the opposite direction to the original tapping direction. As before, only core 1 can be influenced, and this core is brought into state N because of the direction of the pulse.

. The next pulse £ 3 switches the counter C 5 to its second switch position and thus the gates in the second column and the first row with the next pulse 1 1. Since the core 2 is magnetized positively or left positive, an output pulse is produced or not, depending on how the magnetic state of the core was previously. The switching functions continue to develop as described, one after the other for each core, as shown in FIG. The counter C 5 selects the column and the counter C 6 the rows. For the circuit arrangement in FIG. 15 it was assumed that m = 48, the core m + ι is the first core of the second storage.

16 shows schematically the function of the auxiliary head. It will be recalled that the auxiliary head is used to apply an occupied memory to the first element of an occupied memory lane. This takes place in a suitable time slot within the storage cycle. An additional receiving gate G449 is used in the matrix arrangement, which is controlled by the pulse - -t2 and corresponds to the receiving gate G406 for the normal column, but receives an additional control pulse via ARD .

If it is necessary to use a restoration, the control line A RD takes effect. This control line is controlled by the gate G514 in Fig. 3 or by the flip-flop .F23 in Fig. 6, if necessary. The only difference between this mode of operation and that which uses a drum for storage is essentially to ensure that the time slot used to switch the control line ARD is not also used to switch via the normal memory port. If these measures were not taken, incorrect storage of an undesired tap could occur if three or even four lines are excited at the same time.

In Fig. 16, two cores of the second row and two of the last row are shown. The gates G 450 and G 451 are the row gates for restoring, while the other gates are the normal ones as in Fig. 15 1: 5 are. .

From Figs. 15 and 16 it can be seen that the The symbols shown for the voltage gates are shown in the interest of a simple scheme. However is the. The current control used for the matrix is carried out, for example, with the help of "hard" tubes.

A coordinate matrix is schematically shown in FIG which is essentially the same as the arrangements shown in Figs. 15 and 16, but with the difference that so-called ferroelectric

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Elements are used. Ferroelectric materials are dielectrics in which electrical dipoles occur and adapt themselves through interrelationships. The dielectric induction curves versus the electric field show a hysteresis loop similar to that created by the S-iJ curves shown for ferromagnetic materials will. Barium titanate (Ba Ti 03) is now the most common ferroelectric material.

The function is the same in many respects for ferromagnetic matrices. It should be said that the application of a memory pulse to an element this put in a stable electrical state and a tapping pulse an element in which a Impulse is stored, brings it into the other stable state and thus a strong output impulse drops off. When using barium titanates, you get an output pulse of 25 volts for a memory state or flag when the input pulse is 30 volts for 5 ms Compared to 0.6 volts for no saved switching status or a distance. In the present case shorter pulses can be used, which leads to correspondingly lower voltages.

The matrix of FIG. 17 contains a number m · η of ferroelectric elements which are arranged in rows and columns. According to the usual arrangement, m could be 48, η = ίο or m = 24 and η = 20 and the same counter device can be used as in FIG. 15.

To select a particular element for storage or tapping, half the required voltage is applied to the row line and the other half to the column line, making one element effective. As in the previous arrangements, storage is initiated with pulses t2 and tapping is initiated with pulses ti.

The individual elements each have a capacitor and a rectifier connected in parallel Connected in series. In FIG. 17, these switching elements are each common for one column. The output lines are removed from the columns and led to an exit gate G444. Furthermore, as in 15 arrangements are provided for tapping a pulse.

A preferred embodiment of the matrix contains a single large crystal of barium titanate 0.1-0.2 mm thick with conductive strips attached to each side, two sets this strip in an orthogonal arrangement. Each crossing point represents a single storage element.

Claims (18)

PATENT CLAIMS: i. Circuit arrangement for a pulse repeater in telecommunications, in particular telephone systems, which stores and emits dialing pulses in binary form, characterized in that when a connecting line (CCi in Fig. 1 and 2) which emits dialing current is switched on, to the pulse repeater (MD in Fig. 1) After checking a part of this pulse repeater, which stores the current surges sent by the connected connection line for pulse repetition, a switching criterion characterizing the dialing connection line (CC 2 in Fig. 9) is impressed in this part, which after storage of the dialing current impulses the transfer of the same to the outgoing End of the connected connection line and then the triggering of the pulse repeater. 2. Circuit arrangement according to claim 1, characterized in that for receiving and for Pick-up of magnetic drums with one or more magnetizable tracks as well as recording and tapping heads are used and that the dialing pulses in binary form on individual element sections of the courses are saved. 3. Circuit arrangement according to claim 2, characterized in that when connected a connecting line that emits elective surges to a magnetic drum is a free one Storage lane is occupied. 4. Circuit arrangement according to claim 2 and 3, characterized in that the magnetic storage and tapping device is assigned an electronic control device (z. B. SCB and RSB in Fig. 1, 3 to 8). 5. Circuit arrangement according to claim 1 and 2, characterized in that switching means (register EC in Fig. 1) are available for the optional assignment of a pulse repeater to the individual connection sets. 6. Circuit arrangement according to claim 5, characterized in that the dial pulses that can be taken from the connection sets connected to the pulse repeater, in binary Shape to be saved. 7. Circuit arrangement according to claim 3, characterized in that the individual magnetizable tracks of the magnetic drums are divided into sections (z. B. CC, R, L, S in Fig. 9). 8. Circuit arrangement according to claim 7, characterized in that the individual sections the paths of the magnetic drums in time slot segments (e.g. CC2 to CCn, Ä15 to Ä19 etc. in Fig. 9) are divided with a repeatable cycle. 9. Circuit arrangement according to claim 4 and 8, characterized in that in the control device Switching means are available which take up the connection criterion of a connection set. 10. Circuit arrangement according to claim 8, characterized in that on the tracks of the magnetic drums the individual binary memory tags on the element sections can be impressed by current pulses in different directions. 11. Circuit arrangement according to claim 8, characterized in that switching means (RH in Fig. 1) are present in the control device to 609 547/20O I 8411 VIII a / 21a ³ send the renewed output pulses to the outgoing connection set. 12. Circuit arrangement according to claim 4, 8 and 9, characterized in that in the control device Switching means are present which, after the renewed pulses have been sent to the outgoing connection line release the pulse repeater for other connection sets. 13. Circuit arrangement according to claim 1 to 12, characterized in that switching means are present in the repeater device, which switch off the storage of dialing pulses after a pulse pause of a certain length. 14. Circuit arrangement according to claim 7, characterized characterized in that the individual dialing pulses each in a digit of the call number a section of a path can be stored. 15. Circuit arrangement according to claim 14, characterized in that when the stored series of dialing pulses are sent in the control device Switching means are available, which the pauses between the individual power surges and determine the individual series of impulses. 16. Pulse repeater according to claim 1, characterized characterized in that ferromagnetic elements are used for storing the series of dialing pulses (Fig. 16) can be used. 17. Pulse repeater according to claim 1, characterized characterized in that ferroelectric elements are used for the storage of series of dialing pulses (Fig. 17) can be used. 18. Circuit arrangement according to claim 16 and 17, characterized in that the ferromagnetic and ferroelectric memory elements are interconnected like coordinates. Considered publications:
British Patent No. 684 079. In addition 6 sheets of drawings © 609 547/200 6. 56