DE69934517D1 - Mittels redundanter eingabedaten inhaltsadressierbarer speicher - Google Patents
Mittels redundanter eingabedaten inhaltsadressierbarer speicherInfo
- Publication number
- DE69934517D1 DE69934517D1 DE69934517T DE69934517T DE69934517D1 DE 69934517 D1 DE69934517 D1 DE 69934517D1 DE 69934517 T DE69934517 T DE 69934517T DE 69934517 T DE69934517 T DE 69934517T DE 69934517 D1 DE69934517 D1 DE 69934517D1
- Authority
- DE
- Germany
- Prior art keywords
- contentable
- memory
- input data
- redundant input
- medium redundant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/133,602 US6341327B1 (en) | 1998-08-13 | 1998-08-13 | Content addressable memory addressable by redundant form input |
US133602 | 1998-08-13 | ||
PCT/US1999/017631 WO2000010089A1 (en) | 1998-08-13 | 1999-08-03 | Content addressable memory addressable by redundant form input data |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69934517D1 true DE69934517D1 (de) | 2007-02-01 |
DE69934517T2 DE69934517T2 (de) | 2007-11-15 |
Family
ID=22459421
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69934517T Expired - Lifetime DE69934517T2 (de) | 1998-08-13 | 1999-08-03 | Mittels redundanter eingabedaten inhaltsadressierbarer speicher |
Country Status (7)
Country | Link |
---|---|
US (1) | US6341327B1 (de) |
EP (1) | EP1151383B1 (de) |
CN (1) | CN1160630C (de) |
DE (1) | DE69934517T2 (de) |
HK (1) | HK1046172B (de) |
TW (1) | TW442725B (de) |
WO (1) | WO2000010089A1 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6172933B1 (en) * | 1998-09-04 | 2001-01-09 | Intel Corporation | Redundant form address decoder for memory system |
US7089360B1 (en) | 2000-03-22 | 2006-08-08 | Intel Corporation | Shared cache wordline decoder for redundant and regular addresses |
US6507531B1 (en) | 2000-03-29 | 2003-01-14 | Intel Corporation | Cache column multiplexing using redundant form addresses |
US6707752B2 (en) * | 2001-06-22 | 2004-03-16 | Intel Corporation | Tag design for cache access with redundant-form address |
US8004610B2 (en) * | 2006-12-19 | 2011-08-23 | Intel Corporation | Techniques to enable digital television and GPS coexistence |
US8250440B2 (en) * | 2008-02-25 | 2012-08-21 | International Business Machines Corporation | Address generation checking |
US8984217B2 (en) * | 2010-08-24 | 2015-03-17 | Qualcomm Incorporated | System and method of reducing power usage of a content addressable memory |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3527930A (en) | 1967-07-19 | 1970-09-08 | Ibm | High speed division system |
US3917935A (en) | 1974-12-23 | 1975-11-04 | United Technologies Corp | Reduction of look-up table capacity |
JPS55103642A (en) | 1979-02-01 | 1980-08-08 | Tetsunori Nishimoto | Division unit |
US4572656A (en) | 1979-10-30 | 1986-02-25 | Xerox Corporation | Message que interactive control console |
US4327994A (en) | 1980-05-27 | 1982-05-04 | Xerox Corporation | Progressive disclosure copying machine console using common keys for copy number and function select operations |
JPS57155667A (en) | 1981-03-23 | 1982-09-25 | Sony Corp | Arithmetic circuit of galois matter |
JPS58140846A (ja) | 1982-02-16 | 1983-08-20 | Hitachi Ltd | 2進化10進数除算装置 |
US4636973A (en) | 1982-07-21 | 1987-01-13 | Raytheon Company | Vernier addressing apparatus |
US4507748A (en) * | 1982-08-02 | 1985-03-26 | International Telephone And Telegraph Corporation | Associative processor with variable length fast multiply capability |
US4534029A (en) | 1983-03-24 | 1985-08-06 | International Business Machines Corporation | Fault alignment control system and circuits |
JP2513603B2 (ja) | 1985-06-28 | 1996-07-03 | 株式会社東芝 | 画像形成装置 |
US4952823A (en) | 1989-05-03 | 1990-08-28 | Advanced Micro Devices, Inc. | Bicmos decoder |
US5184318A (en) | 1989-09-05 | 1993-02-02 | Cyrix Corporation | Rectangular array signed digit multiplier |
GB9007796D0 (en) | 1990-04-06 | 1990-06-06 | Foss Richard C | Dynamic memory row/column redundancy scheme |
GB2246001B (en) * | 1990-04-11 | 1994-06-15 | Digital Equipment Corp | Array architecture for high speed cache memory |
JP3159349B2 (ja) | 1993-12-28 | 2001-04-23 | 日本電気株式会社 | 加算デコード装置 |
US5568416A (en) * | 1994-03-24 | 1996-10-22 | Kawasaki Steel Corporation | Associative memory |
US5754819A (en) * | 1994-07-28 | 1998-05-19 | Sun Microsystems, Inc. | Low-latency memory indexing method and structure |
US5583806A (en) | 1994-10-17 | 1996-12-10 | Advanced Micro Devices, Inc. | Optimized binary adder for concurrently generating effective and intermediate addresses |
US5625582A (en) | 1995-03-23 | 1997-04-29 | Intel Corporation | Apparatus and method for optimizing address calculations |
JP2738363B2 (ja) | 1995-09-07 | 1998-04-08 | 日本電気株式会社 | 連想記憶装置 |
US5815420A (en) | 1996-07-31 | 1998-09-29 | Texas Instruments Incorporated | Microprocessor arithmetic logic unit using multiple number representations |
US5953745A (en) | 1996-11-27 | 1999-09-14 | International Business Machines Corporation | Redundant memory array |
US5893137A (en) | 1996-11-29 | 1999-04-06 | Motorola, Inc. | Apparatus and method for implementing a content addressable memory circuit with two stage matching |
US6172933B1 (en) * | 1998-09-04 | 2001-01-09 | Intel Corporation | Redundant form address decoder for memory system |
-
1998
- 1998-08-13 US US09/133,602 patent/US6341327B1/en not_active Expired - Lifetime
-
1999
- 1999-07-29 TW TW088112889A patent/TW442725B/zh not_active IP Right Cessation
- 1999-08-03 WO PCT/US1999/017631 patent/WO2000010089A1/en active IP Right Grant
- 1999-08-03 EP EP99937784A patent/EP1151383B1/de not_active Expired - Lifetime
- 1999-08-03 CN CNB998137286A patent/CN1160630C/zh not_active Expired - Fee Related
- 1999-08-03 DE DE69934517T patent/DE69934517T2/de not_active Expired - Lifetime
-
2002
- 2002-10-10 HK HK02107413.2A patent/HK1046172B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
WO2000010089A1 (en) | 2000-02-24 |
EP1151383A4 (de) | 2004-06-16 |
EP1151383B1 (de) | 2006-12-20 |
CN1354855A (zh) | 2002-06-19 |
EP1151383A1 (de) | 2001-11-07 |
CN1160630C (zh) | 2004-08-04 |
US6341327B1 (en) | 2002-01-22 |
DE69934517T2 (de) | 2007-11-15 |
HK1046172B (zh) | 2005-04-29 |
HK1046172A1 (en) | 2002-12-27 |
TW442725B (en) | 2001-06-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |