DE69930790D1 - Synchrone Steuervorrichtung und Verfahren dafür - Google Patents

Synchrone Steuervorrichtung und Verfahren dafür

Info

Publication number
DE69930790D1
DE69930790D1 DE69930790T DE69930790T DE69930790D1 DE 69930790 D1 DE69930790 D1 DE 69930790D1 DE 69930790 T DE69930790 T DE 69930790T DE 69930790 T DE69930790 T DE 69930790T DE 69930790 D1 DE69930790 D1 DE 69930790D1
Authority
DE
Germany
Prior art keywords
control device
method therefor
synchronous control
synchronous
therefor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69930790T
Other languages
English (en)
Other versions
DE69930790T2 (de
Inventor
Kinya Inoue
Masafumi Toshitani
Hitoshi Koseki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaha Corp
Original Assignee
Yamaha Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaha Corp filed Critical Yamaha Corp
Publication of DE69930790D1 publication Critical patent/DE69930790D1/de
Application granted granted Critical
Publication of DE69930790T2 publication Critical patent/DE69930790T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
DE69930790T 1998-07-23 1999-07-23 Synchrone Steuervorrichtung und Verfahren dafür Expired - Lifetime DE69930790T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP20813998A JP3296297B2 (ja) 1998-07-23 1998-07-23 同期制御方式
JP20813998 1998-07-23

Publications (2)

Publication Number Publication Date
DE69930790D1 true DE69930790D1 (de) 2006-05-24
DE69930790T2 DE69930790T2 (de) 2007-04-12

Family

ID=16551292

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69930790T Expired - Lifetime DE69930790T2 (de) 1998-07-23 1999-07-23 Synchrone Steuervorrichtung und Verfahren dafür

Country Status (4)

Country Link
US (1) US6643345B1 (de)
EP (1) EP0975094B1 (de)
JP (1) JP3296297B2 (de)
DE (1) DE69930790T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100585112B1 (ko) * 2003-11-25 2006-05-30 삼성전자주식회사 Pll 회로의 주파수 분주기, 이를 포함하는 pll 회로, 및 pll 회로의 주파수 분주기의 레지스터 검사 방법
GB2409383B (en) * 2003-12-17 2006-06-21 Wolfson Ltd Clock synchroniser
GB2413043B (en) * 2004-04-06 2006-11-15 Wolfson Ltd Clock synchroniser and clock and data recovery apparatus and method
US7646836B1 (en) * 2005-03-01 2010-01-12 Network Equipment Technologies, Inc. Dynamic clock rate matching across an asynchronous network
JP4475273B2 (ja) * 2006-12-21 2010-06-09 ソニー株式会社 情報処理装置及び方法
TW200921325A (en) * 2007-11-05 2009-05-16 Holtek Semiconductor Inc Frequency synchronous apparatus and method
US10069503B2 (en) * 2016-05-30 2018-09-04 Microsemi Semiconductor Ulc Method of speeding up output alignment in a digital phase locked loop

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150386A (en) * 1987-05-19 1992-09-22 Crystal Semiconductor Corporation Clock multiplier/jitter attenuator
US4941156A (en) * 1987-05-19 1990-07-10 Crystal Semiconductor Linear jitter attenuator
JPH02105272A (ja) 1988-10-13 1990-04-17 Hitachi Eng Co Ltd 画像処理装置
JPH0410712A (ja) 1990-04-27 1992-01-14 Shin Kobe Electric Mach Co Ltd 位相同期制御回路
JPH04322532A (ja) 1991-04-22 1992-11-12 Matsushita Electric Ind Co Ltd クロック再生回路
US5390180A (en) * 1991-10-10 1995-02-14 Nec America, Inc. SONET DS-N desynchronizer
US5339338A (en) * 1992-10-06 1994-08-16 Dsc Communications Corporation Apparatus and method for data desynchronization
US5901149A (en) * 1994-11-09 1999-05-04 Sony Corporation Decode and encode system
DK150796A (da) * 1996-12-23 1998-06-24 Dsc Communications As Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronise
US6088413A (en) * 1997-05-09 2000-07-11 Alcatel Apparatus for reducing jitter in a desynchronizer
US6111878A (en) * 1997-11-04 2000-08-29 Alcatel Low jitter timing recovery technique and device for asynchronous transfer mode (ATM) constant bit rate (CBR) payloads

Also Published As

Publication number Publication date
JP2000040956A (ja) 2000-02-08
EP0975094A2 (de) 2000-01-26
US6643345B1 (en) 2003-11-04
EP0975094A3 (de) 2003-04-09
DE69930790T2 (de) 2007-04-12
EP0975094B1 (de) 2006-04-12
JP3296297B2 (ja) 2002-06-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition