DE69928428D1 - Multiplizier-akkumulator-konfiguration zur effizienten planung in einem digitalen signalverarbeitungsrechner - Google Patents

Multiplizier-akkumulator-konfiguration zur effizienten planung in einem digitalen signalverarbeitungsrechner

Info

Publication number
DE69928428D1
DE69928428D1 DE69928428T DE69928428T DE69928428D1 DE 69928428 D1 DE69928428 D1 DE 69928428D1 DE 69928428 T DE69928428 T DE 69928428T DE 69928428 T DE69928428 T DE 69928428T DE 69928428 D1 DE69928428 D1 DE 69928428D1
Authority
DE
Germany
Prior art keywords
digital signal
signal processor
multiplier accumulator
efficient planning
accumulator configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69928428T
Other languages
English (en)
Other versions
DE69928428T2 (de
Inventor
A Mohamed
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Callahan Cellular LLC
Original Assignee
Mindspeed Technologies LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mindspeed Technologies LLC filed Critical Mindspeed Technologies LLC
Publication of DE69928428D1 publication Critical patent/DE69928428D1/de
Application granted granted Critical
Publication of DE69928428T2 publication Critical patent/DE69928428T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Advance Control (AREA)
DE69928428T 1998-10-14 1999-08-24 Multiplizier-akkumulator-konfiguration zur effizienten planung in einem digitalen signalverarbeitungsrechner Expired - Lifetime DE69928428T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US172527 1998-10-14
US09/172,527 US6230180B1 (en) 1998-10-14 1998-10-14 Digital signal processor configuration including multiplying units coupled to plural accumlators for enhanced parallel mac processing
PCT/US1999/019594 WO2000022514A1 (en) 1998-10-14 1999-08-24 Multiplier-accumulator configuration for efficient scheduling in a digital signal processor

Publications (2)

Publication Number Publication Date
DE69928428D1 true DE69928428D1 (de) 2005-12-22
DE69928428T2 DE69928428T2 (de) 2006-08-03

Family

ID=22628085

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69928428T Expired - Lifetime DE69928428T2 (de) 1998-10-14 1999-08-24 Multiplizier-akkumulator-konfiguration zur effizienten planung in einem digitalen signalverarbeitungsrechner

Country Status (4)

Country Link
US (1) US6230180B1 (de)
EP (1) EP1121636B1 (de)
DE (1) DE69928428T2 (de)
WO (1) WO2000022514A1 (de)

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US7107302B1 (en) 1999-05-12 2006-09-12 Analog Devices, Inc. Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units
US6820189B1 (en) 1999-05-12 2004-11-16 Analog Devices, Inc. Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation
US7111155B1 (en) 1999-05-12 2006-09-19 Analog Devices, Inc. Digital signal processor computation core with input operand selection from operand bus for dual operations
US6859872B1 (en) 1999-05-12 2005-02-22 Analog Devices, Inc. Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operation
GB2352066B (en) * 1999-07-14 2003-11-05 Element 14 Ltd An instruction set for a computer
US6856945B2 (en) * 2000-12-04 2005-02-15 Tensorcomm, Inc. Method and apparatus for implementing projections in singal processing applications
US6711219B2 (en) 2000-12-04 2004-03-23 Tensorcomm, Incorporated Interference cancellation in a signal
US7158559B2 (en) 2002-01-15 2007-01-02 Tensor Comm, Inc. Serial cancellation receiver design for a coded signal processing engine
US8085889B1 (en) 2005-04-11 2011-12-27 Rambus Inc. Methods for managing alignment and latency in interference cancellation
EP1540860A2 (de) 2001-11-16 2005-06-15 Tensorcomm Incorporated Konstruktion einer störungsmatrix für eine verarbeitungsmaschine für kodierte signale
US7260506B2 (en) * 2001-11-19 2007-08-21 Tensorcomm, Inc. Orthogonalization and directional filtering
WO2005081438A1 (en) * 2001-11-19 2005-09-01 Tensorcomm, Incorporated Interference cancellation in a signal
US20050101277A1 (en) * 2001-11-19 2005-05-12 Narayan Anand P. Gain control for interference cancellation
US7120780B2 (en) * 2002-03-04 2006-10-10 International Business Machines Corporation Method of renaming registers in register file and microprocessor thereof
US20040208238A1 (en) * 2002-06-25 2004-10-21 Thomas John K. Systems and methods for location estimation in spread spectrum communication systems
EP1387257B1 (de) * 2002-07-31 2017-08-23 Texas Instruments Inc. System zur Zuweisung einer Vielzahl von Befehlen an verfügbare Hardwarebetriebsmittel
US7808937B2 (en) * 2005-04-07 2010-10-05 Rambus, Inc. Variable interference cancellation technology for CDMA systems
US8761321B2 (en) * 2005-04-07 2014-06-24 Iii Holdings 1, Llc Optimal feedback weighting for soft-decision cancellers
US7463609B2 (en) * 2005-07-29 2008-12-09 Tensorcomm, Inc Interference cancellation within wireless transceivers
US7577186B2 (en) * 2002-09-20 2009-08-18 Tensorcomm, Inc Interference matrix construction
US20050180364A1 (en) * 2002-09-20 2005-08-18 Vijay Nagarajan Construction of projection operators for interference cancellation
US7876810B2 (en) 2005-04-07 2011-01-25 Rambus Inc. Soft weighted interference cancellation for CDMA systems
US7787572B2 (en) * 2005-04-07 2010-08-31 Rambus Inc. Advanced signal processors for interference cancellation in baseband receivers
JP4444832B2 (ja) 2002-09-23 2010-03-31 テンソルコム インコーポレイテッド スペクトル拡散システムにおける干渉除去を選択的に利用するための方法及び装置
US20050123080A1 (en) * 2002-11-15 2005-06-09 Narayan Anand P. Systems and methods for serial cancellation
US8005128B1 (en) 2003-09-23 2011-08-23 Rambus Inc. Methods for estimation and interference cancellation for signal processing
US8179946B2 (en) 2003-09-23 2012-05-15 Rambus Inc. Systems and methods for control of advanced receivers
WO2004036811A2 (en) * 2002-10-15 2004-04-29 Tensorcomm Inc. Method and apparatus for interference suppression with efficient matrix inversion in a ds-cdma system
CN1723627A (zh) * 2002-10-15 2006-01-18 张量通讯公司 用于信道幅度估计和干扰矢量构造的方法和装置
AU2003290558A1 (en) * 2002-10-31 2004-06-07 Tensorcomm, Incorporated Systems and methods for reducing interference in cdma systems
WO2004073159A2 (en) * 2002-11-15 2004-08-26 Tensorcomm, Incorporated Systems and methods for parallel signal cancellation
US7043518B2 (en) * 2003-07-31 2006-05-09 Cradle Technologies, Inc. Method and system for performing parallel integer multiply accumulate operations on packed data
US20050169354A1 (en) * 2004-01-23 2005-08-04 Olson Eric S. Systems and methods for searching interference canceled data
US7477710B2 (en) * 2004-01-23 2009-01-13 Tensorcomm, Inc Systems and methods for analog to digital conversion with a signal cancellation system of a receiver
US20060125689A1 (en) * 2004-12-10 2006-06-15 Narayan Anand P Interference cancellation in a receive diversity system
US20060229051A1 (en) * 2005-04-07 2006-10-12 Narayan Anand P Interference selection and cancellation for CDMA communications
US7826516B2 (en) 2005-11-15 2010-11-02 Rambus Inc. Iterative interference canceller for wireless multiple-access systems with multiple receive antennas
US9600278B1 (en) * 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees

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EP0042452B1 (de) * 1980-06-24 1984-03-14 International Business Machines Corporation Signalprozessorrechneranordnung und Verfahren zum Betrieb der Anordnung
US4754421A (en) * 1985-09-06 1988-06-28 Texas Instruments Incorporated Multiple precision multiplication device
EP0466997A1 (de) * 1990-07-18 1992-01-22 International Business Machines Corporation Verbesserte digitale Signal-Verarbeitungsarchitektur
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US5434808A (en) * 1993-10-29 1995-07-18 Nec Electronics, Inc. Highly parallel discrete cosine transform engine
KR0150350B1 (ko) * 1994-05-10 1998-10-15 모리시다 요이치 직교변환 프로세서
US6167503A (en) 1995-10-06 2000-12-26 Compaq Computer Corporation Register and instruction controller for superscalar processor
US5784306A (en) 1996-06-28 1998-07-21 Cirrus Logic, Inc. Parallel multiply accumulate array circuit
US6530014B2 (en) 1997-09-08 2003-03-04 Agere Systems Inc. Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits

Also Published As

Publication number Publication date
WO2000022514A1 (en) 2000-04-20
US6230180B1 (en) 2001-05-08
EP1121636A1 (de) 2001-08-08
EP1121636B1 (de) 2005-11-16
DE69928428T2 (de) 2006-08-03

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Owner name: SCHULKORT TRIO LLC, DOVER, DEL., US