DE69733101D1 - Datenüberlaufverwaltung in einem Rechnersystem - Google Patents

Datenüberlaufverwaltung in einem Rechnersystem

Info

Publication number
DE69733101D1
DE69733101D1 DE69733101T DE69733101T DE69733101D1 DE 69733101 D1 DE69733101 D1 DE 69733101D1 DE 69733101 T DE69733101 T DE 69733101T DE 69733101 T DE69733101 T DE 69733101T DE 69733101 D1 DE69733101 D1 DE 69733101D1
Authority
DE
Germany
Prior art keywords
computer system
data overflow
overflow management
management
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69733101T
Other languages
English (en)
Other versions
DE69733101T2 (de
Inventor
Christopher J Pettey
John M Maclaren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Application granted granted Critical
Publication of DE69733101D1 publication Critical patent/DE69733101D1/de
Publication of DE69733101T2 publication Critical patent/DE69733101T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4045—Coupling between buses using bus bridges where the bus bridge performs an extender function

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69733101T 1996-06-05 1997-06-04 Datenüberlaufverwaltung in einem Rechnersystem Expired - Lifetime DE69733101T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US658533 1996-06-05
US08/658,533 US6055590A (en) 1996-06-05 1996-06-05 Bridge circuit comprising independent transaction buffers with control logic adapted to store overflow data in second buffer when transaction size exceeds the first buffer size

Publications (2)

Publication Number Publication Date
DE69733101D1 true DE69733101D1 (de) 2005-06-02
DE69733101T2 DE69733101T2 (de) 2005-09-29

Family

ID=24641639

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69733101T Expired - Lifetime DE69733101T2 (de) 1996-06-05 1997-06-04 Datenüberlaufverwaltung in einem Rechnersystem

Country Status (4)

Country Link
US (1) US6055590A (de)
EP (1) EP0811934B1 (de)
JP (1) JPH1063611A (de)
DE (1) DE69733101T2 (de)

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US10141930B2 (en) 2013-06-04 2018-11-27 Nvidia Corporation Three state latch
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Also Published As

Publication number Publication date
DE69733101T2 (de) 2005-09-29
EP0811934A3 (de) 1999-02-10
EP0811934A2 (de) 1997-12-10
EP0811934B1 (de) 2005-04-27
JPH1063611A (ja) 1998-03-06
US6055590A (en) 2000-04-25

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Legal Events

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8364 No opposition during term of opposition