DE69919584T2 - Betriebsmittelsteuerung in einer datenverarbeitungsanlage - Google Patents
Betriebsmittelsteuerung in einer datenverarbeitungsanlage Download PDFInfo
- Publication number
- DE69919584T2 DE69919584T2 DE69919584T DE69919584T DE69919584T2 DE 69919584 T2 DE69919584 T2 DE 69919584T2 DE 69919584 T DE69919584 T DE 69919584T DE 69919584 T DE69919584 T DE 69919584T DE 69919584 T2 DE69919584 T2 DE 69919584T2
- Authority
- DE
- Germany
- Prior art keywords
- bridge
- bus
- register
- processing
- processing set
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Hardware Redundancy (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/094,847 US6167477A (en) | 1998-06-15 | 1998-06-15 | Computer system bridge employing a resource control mechanism with programmable registers to control resource allocation |
| US94847 | 1998-06-15 | ||
| PCT/US1999/012605 WO1999066416A2 (en) | 1998-06-15 | 1999-06-04 | Resource control in a computer system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69919584D1 DE69919584D1 (de) | 2004-09-23 |
| DE69919584T2 true DE69919584T2 (de) | 2005-08-11 |
Family
ID=22247520
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69919584T Expired - Lifetime DE69919584T2 (de) | 1998-06-15 | 1999-06-04 | Betriebsmittelsteuerung in einer datenverarbeitungsanlage |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6167477A (enExample) |
| EP (1) | EP1145131B1 (enExample) |
| JP (1) | JP2002526818A (enExample) |
| DE (1) | DE69919584T2 (enExample) |
| WO (1) | WO1999066416A2 (enExample) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6587961B1 (en) * | 1998-06-15 | 2003-07-01 | Sun Microsystems, Inc. | Multi-processor system bridge with controlled access |
| US6647446B1 (en) * | 2000-03-18 | 2003-11-11 | Sony Corporation | Method and system for using a new bus identifier resulting from a bus topology change |
| GB2369690B (en) * | 2000-11-29 | 2002-10-16 | Sun Microsystems Inc | Enhanced protection for memory modification tracking |
| GB2369692B (en) | 2000-11-29 | 2002-10-16 | Sun Microsystems Inc | Processor state reintegration |
| US6918027B2 (en) * | 2001-07-30 | 2005-07-12 | Hewlett-Packard Development Company, L.P. | System and method for in-system programming through an on-system JTAG bridge of programmable logic devices on multiple circuit boards of a system |
| US6883109B2 (en) * | 2001-07-30 | 2005-04-19 | Hewlett-Packard Development Company, L.P. | Method for accessing scan chains and updating EEPROM-resident FPGA code through a system management processor and JTAG bus |
| US20040225783A1 (en) * | 2001-07-30 | 2004-11-11 | Erickson Michael John | Bus to multiple jtag bus bridge |
| US6954929B2 (en) * | 2001-07-30 | 2005-10-11 | Hewlett-Packard Development Company, L.P. | Method for just-in-time updating of programming parts |
| GB2391335B (en) * | 2002-03-19 | 2005-01-12 | Sun Microsystems Inc | Computer system |
| GB2399913B (en) * | 2002-03-19 | 2004-12-15 | Sun Microsystems Inc | Fault tolerant computer system |
| US7213094B2 (en) * | 2004-02-17 | 2007-05-01 | Intel Corporation | Method and apparatus for managing buffers in PCI bridges |
| US7917906B2 (en) * | 2004-07-02 | 2011-03-29 | Seagate Technology Llc | Resource allocation in a computer-based system |
| US7669073B2 (en) * | 2005-08-19 | 2010-02-23 | Stratus Technologies Bermuda Ltd. | Systems and methods for split mode operation of fault-tolerant computer systems |
| CN104615572B (zh) * | 2015-02-27 | 2018-05-01 | 苏州科达科技股份有限公司 | 热插拔处理系统及方法 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5669002A (en) * | 1990-06-28 | 1997-09-16 | Digital Equipment Corp. | Multi-processor resource locking mechanism with a lock register corresponding to each resource stored in common memory |
| US5574869A (en) * | 1992-03-30 | 1996-11-12 | Intel Corporation | Bus bridge circuit having configuration space enable register for controlling transition between various modes by writing the bridge identifier into CSE register |
| US5941964A (en) * | 1992-05-21 | 1999-08-24 | Intel Corporation | Bridge buffer management by bridge interception of synchronization events |
| GB2268817B (en) * | 1992-07-17 | 1996-05-01 | Integrated Micro Products Ltd | A fault-tolerant computer system |
| US5515510A (en) * | 1994-01-14 | 1996-05-07 | Consilium Overseas Limited | Communications internetwork system connecting a client node array to a resource array |
| US5835742A (en) * | 1994-06-14 | 1998-11-10 | Apple Computer, Inc. | System and method for executing indivisible memory operations in multiple processor computer systems with multiple busses |
| US5603051A (en) * | 1995-06-06 | 1997-02-11 | Hewlett-Packard Company | Input/output processor with a local memory providing shared resources for a plurality of input/output interfaces on an I/O bus |
| JPH0954746A (ja) * | 1995-08-11 | 1997-02-25 | Toshiba Corp | コンピュータシステム |
| US5790814A (en) * | 1996-01-23 | 1998-08-04 | Dell U.S.A., L.P. | Technique for supporting semi-compliant PCI devices behind a PCI-to-PCI bridge |
-
1998
- 1998-06-15 US US09/094,847 patent/US6167477A/en not_active Expired - Lifetime
-
1999
- 1999-06-04 WO PCT/US1999/012605 patent/WO1999066416A2/en not_active Ceased
- 1999-06-04 EP EP99928406A patent/EP1145131B1/en not_active Expired - Lifetime
- 1999-06-04 JP JP2000555173A patent/JP2002526818A/ja active Pending
- 1999-06-04 DE DE69919584T patent/DE69919584T2/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| WO1999066416A2 (en) | 1999-12-23 |
| EP1145131B1 (en) | 2004-08-18 |
| EP1145131A3 (en) | 2002-03-27 |
| WO1999066416A3 (en) | 2001-12-13 |
| EP1145131A2 (en) | 2001-10-17 |
| DE69919584D1 (de) | 2004-09-23 |
| JP2002526818A (ja) | 2002-08-20 |
| US6167477A (en) | 2000-12-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |