DE69915953D1 - Verfahren und Anordnung zum Synchronisieren eines Datenstroms - Google Patents

Verfahren und Anordnung zum Synchronisieren eines Datenstroms

Info

Publication number
DE69915953D1
DE69915953D1 DE69915953T DE69915953T DE69915953D1 DE 69915953 D1 DE69915953 D1 DE 69915953D1 DE 69915953 T DE69915953 T DE 69915953T DE 69915953 T DE69915953 T DE 69915953T DE 69915953 D1 DE69915953 D1 DE 69915953D1
Authority
DE
Germany
Prior art keywords
synchronizing
arrangement
data stream
stream
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69915953T
Other languages
English (en)
Other versions
DE69915953T2 (de
Inventor
Raimo Santahuhta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Technology GmbH
Original Assignee
Nokia Technology GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Technology GmbH filed Critical Nokia Technology GmbH
Publication of DE69915953D1 publication Critical patent/DE69915953D1/de
Application granted granted Critical
Publication of DE69915953T2 publication Critical patent/DE69915953T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE69915953T 1998-09-22 1999-09-17 Verfahren und Anordnung zum Synchronisieren eines Datenstroms Expired - Fee Related DE69915953T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI982040 1998-09-22
FI982040A FI982040A (fi) 1998-09-22 1998-09-22 Menetelmä ja laite datavirran synkronoimiseksi

Publications (2)

Publication Number Publication Date
DE69915953D1 true DE69915953D1 (de) 2004-05-06
DE69915953T2 DE69915953T2 (de) 2005-01-27

Family

ID=8552539

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69915953T Expired - Fee Related DE69915953T2 (de) 1998-09-22 1999-09-17 Verfahren und Anordnung zum Synchronisieren eines Datenstroms

Country Status (4)

Country Link
US (1) US6765932B1 (de)
EP (1) EP0989484B1 (de)
DE (1) DE69915953T2 (de)
FI (1) FI982040A (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6839856B1 (en) * 2000-07-20 2005-01-04 Silicon Graphics, Inc. Method and circuit for reliable data capture in the presence of bus-master changeovers
US7333516B1 (en) 2000-07-20 2008-02-19 Silicon Graphics, Inc. Interface for synchronous data transfer between domains clocked at different frequencies
JP3580242B2 (ja) * 2000-10-25 2004-10-20 セイコーエプソン株式会社 シリアル／パラレル変換回路、データ転送制御装置及び電子機器
JP2003157228A (ja) * 2001-11-20 2003-05-30 Fujitsu Ltd データ転送回路
US6910145B2 (en) * 2001-12-13 2005-06-21 Emc Corporation Data transmission across asynchronous clock domains
US20030172235A1 (en) * 2002-02-27 2003-09-11 Letey George Thomas Read data storage controller with bypass read data return path
US7249274B1 (en) * 2003-12-30 2007-07-24 Intel Corporation System and method for scalable clock gearing mechanism

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4692893A (en) * 1984-12-24 1987-09-08 International Business Machines Corp. Buffer system using parity checking of address counter bit for detection of read/write failures
US4873703A (en) * 1985-09-27 1989-10-10 Hewlett-Packard Company Synchronizing system
US5706299A (en) 1992-05-21 1998-01-06 Alcatel Network Systems, Inc. Sonet tributary ambiguity resolution for elastic store control
AU665072B2 (en) 1992-05-21 1995-12-14 Alcatel N.V. TDM synchronous state machine
US5388074A (en) * 1992-12-17 1995-02-07 Vlsi Technology, Inc. FIFO memory using single output register
US5422914A (en) * 1993-09-07 1995-06-06 Motorola, Inc. System and method for synchronizing data communications between two devices operating at different clock frequencies
FR2711435B1 (fr) * 1993-10-20 1995-12-29 Cit Alcatel Dispositif pour justifier à intervalles réguliers un train numérique.
US5487092A (en) * 1994-12-22 1996-01-23 International Business Machines Corporation System for high-speed synchronization across clock domains
JP3408652B2 (ja) * 1995-02-03 2003-05-19 沖電気工業株式会社 ビット位相同期回路
WO1997006491A1 (en) * 1995-08-10 1997-02-20 International Business Machines Corporation Synchronizing logic avoiding metastability
US5905766A (en) * 1996-03-29 1999-05-18 Fore Systems, Inc. Synchronizer, method and system for transferring data
US5909563A (en) * 1996-09-25 1999-06-01 Philips Electronics North America Corporation Computer system including an interface for transferring data between two clock domains
JPH10144071A (ja) * 1996-11-01 1998-05-29 Oki Electric Ind Co Ltd 半導体記憶装置
US5696768A (en) * 1996-12-10 1997-12-09 Intel Corporation Method and apparatus for data storage array tracking
US6269136B1 (en) * 1998-02-02 2001-07-31 Microunity Systems Engineering, Inc. Digital differential analyzer data synchronizer

Also Published As

Publication number Publication date
FI982040A0 (fi) 1998-09-22
EP0989484A3 (de) 2002-05-29
US6765932B1 (en) 2004-07-20
EP0989484B1 (de) 2004-03-31
DE69915953T2 (de) 2005-01-27
FI982040A (fi) 2000-03-23
EP0989484A2 (de) 2000-03-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee