DE69901708D1 - Gemischter vektor/skalar-registersatz - Google Patents

Gemischter vektor/skalar-registersatz

Info

Publication number
DE69901708D1
DE69901708D1 DE69901708T DE69901708T DE69901708D1 DE 69901708 D1 DE69901708 D1 DE 69901708D1 DE 69901708 T DE69901708 T DE 69901708T DE 69901708 T DE69901708 T DE 69901708T DE 69901708 D1 DE69901708 D1 DE 69901708D1
Authority
DE
Germany
Prior art keywords
register set
scalar register
mixed vector
vector
mixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69901708T
Other languages
English (en)
Other versions
DE69901708T2 (de
Inventor
Neal Hinds
Vivian Jaggar
Terrence Matheny
James Seal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Publication of DE69901708D1 publication Critical patent/DE69901708D1/de
Application granted granted Critical
Publication of DE69901708T2 publication Critical patent/DE69901708T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138—Extension of register space, e.g. register cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G06F9/3455—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results using stride
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49957—Implementation of IEEE-754 Standard

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
DE69901708T 1998-05-27 1999-03-09 Gemischter vektor/skalar-registersatz Expired - Lifetime DE69901708T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/084,304 US6282634B1 (en) 1998-05-27 1998-05-27 Apparatus and method for processing data having a mixed vector/scalar register file
PCT/GB1999/000701 WO1999061996A1 (en) 1998-05-27 1999-03-09 Mixed vector/scalar register file

Publications (2)

Publication Number Publication Date
DE69901708D1 true DE69901708D1 (de) 2002-07-11
DE69901708T2 DE69901708T2 (de) 2002-12-05

Family

ID=22184104

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69901708T Expired - Lifetime DE69901708T2 (de) 1998-05-27 1999-03-09 Gemischter vektor/skalar-registersatz

Country Status (11)

Country Link
US (3) US6282634B1 (de)
EP (1) EP1080420B1 (de)
JP (1) JP2002517037A (de)
KR (1) KR100563219B1 (de)
CN (1) CN1191535C (de)
DE (1) DE69901708T2 (de)
IL (1) IL139250A0 (de)
MY (1) MY125652A (de)
RU (1) RU2212049C2 (de)
TW (1) TW413766B (de)
WO (1) WO1999061996A1 (de)

Families Citing this family (150)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6282634B1 (en) * 1998-05-27 2001-08-28 Arm Limited Apparatus and method for processing data having a mixed vector/scalar register file
US6687722B1 (en) * 2000-03-16 2004-02-03 Agere Systems, Inc. High-speed/low power finite impulse response filter
US6857061B1 (en) * 2000-04-07 2005-02-15 Nintendo Co., Ltd. Method and apparatus for obtaining a scalar value directly from a vector register
US6675376B2 (en) * 2000-12-29 2004-01-06 Intel Corporation System and method for fusing instructions
WO2002084451A2 (en) * 2001-02-06 2002-10-24 Victor Demjanenko Vector processor architecture and methods performed therein
US6842849B2 (en) * 2001-05-21 2005-01-11 Arm Limited Locking source registers in a data processing apparatus
US7831652B2 (en) * 2001-05-25 2010-11-09 Oracle America, Inc. Floating point multiplier with embedded status information
US7430576B2 (en) * 2001-05-25 2008-09-30 Sun Microsystems, Inc. Floating point square root provider with embedded status information
US6961744B2 (en) * 2001-05-25 2005-11-01 Sun Microsystems, Inc. System and method for generating an integer part of a logarithm of a floating point operand
US7016928B2 (en) * 2001-05-25 2006-03-21 Sun Microsystems, Inc. Floating point status information testing circuit
US7366749B2 (en) * 2001-05-25 2008-04-29 Sun Microsystems, Inc. Floating point adder with embedded status information
US7444367B2 (en) * 2001-05-25 2008-10-28 Sun Microsystems, Inc. Floating point status information accumulation circuit
US6976050B2 (en) * 2001-05-25 2005-12-13 Sun Microsystems, Inc. System and method for extracting the high part of a floating point operand
US7395297B2 (en) 2001-05-25 2008-07-01 Sun Microsystems, Inc. Floating point system that represents status flag information within a floating point operand
US6993549B2 (en) * 2001-05-25 2006-01-31 Sun Microsystems, Inc. System and method for performing gloating point operations involving extended exponents
US7191202B2 (en) 2001-05-25 2007-03-13 Sun Microsystems, Inc. Comparator unit for comparing values of floating point operands
US7228324B2 (en) * 2001-05-25 2007-06-05 Sun Microsystems, Inc. Circuit for selectively providing maximum or minimum of a pair of floating point operands
US7363337B2 (en) * 2001-05-25 2008-04-22 Sun Microsystems, Inc. Floating point divider with embedded status information
US6970898B2 (en) * 2001-05-25 2005-11-29 Sun Microsystems, Inc. System and method for forcing floating point status information to selected values
US7069289B2 (en) * 2001-05-25 2006-06-27 Sun Microsystems, Inc. Floating point unit for detecting and representing inexact computations without flags or traps
US7133890B2 (en) 2001-05-25 2006-11-07 Sun Microsystems, Inc. Total order comparator unit for comparing values of two floating point operands
US7069288B2 (en) * 2001-05-25 2006-06-27 Sun Microsystems, Inc. Floating point system with improved support of interval arithmetic
US7003540B2 (en) * 2001-05-25 2006-02-21 Sun Microsystems, Inc. Floating point multiplier for delimited operands
US7613762B2 (en) * 2001-05-25 2009-11-03 Sun Microsystems, Inc. Floating point remainder with embedded status information
US6779013B2 (en) * 2001-06-04 2004-08-17 Intel Corporation Floating point overflow and sign detection
US7080111B2 (en) * 2001-06-04 2006-07-18 Intel Corporation Floating point multiply accumulator
GB2382674B (en) 2001-10-31 2005-11-16 Alphamosaic Ltd Data access in a processor
US7937559B1 (en) 2002-05-13 2011-05-03 Tensilica, Inc. System and method for generating a configurable processor supporting a user-defined plurality of instruction sizes
US7376812B1 (en) * 2002-05-13 2008-05-20 Tensilica, Inc. Vector co-processor for configurable and extensible processor architecture
US7392368B2 (en) * 2002-08-09 2008-06-24 Marvell International Ltd. Cross multiply and add instruction and multiply and subtract instruction SIMD execution on real and imaginary components of a plurality of complex data elements
AU2003256870A1 (en) * 2002-08-09 2004-02-25 Intel Corporation Multimedia coprocessor control mechanism including alignment or broadcast instructions
US6986023B2 (en) * 2002-08-09 2006-01-10 Intel Corporation Conditional execution of coprocessor instruction based on main processor arithmetic flags
GB2424503B (en) * 2002-09-17 2007-06-20 Micron Technology Inc An active memory device
WO2004030224A1 (en) * 2002-09-27 2004-04-08 Ibiquity Digital Corporation Method and apparatus for interleaving signal bits in a digital audio broadcasting system
US6944747B2 (en) * 2002-12-09 2005-09-13 Gemtech Systems, Llc Apparatus and method for matrix data processing
US7219117B2 (en) * 2002-12-17 2007-05-15 Sun Microsystems, Inc. Methods and systems for computing floating-point intervals
US7236999B2 (en) * 2002-12-17 2007-06-26 Sun Microsystems, Inc. Methods and systems for computing the quotient of floating-point intervals
US20040193838A1 (en) * 2003-03-31 2004-09-30 Patrick Devaney Vector instructions composed from scalar instructions
US7024544B2 (en) * 2003-06-24 2006-04-04 Via-Cyrix, Inc. Apparatus and method for accessing registers in a processor
US7299170B2 (en) * 2003-06-28 2007-11-20 Transitive Limited Method and apparatus for the emulation of high precision floating point instructions
GB2409060B (en) * 2003-12-09 2006-08-09 Advanced Risc Mach Ltd Moving data between registers of different register data stores
GB2409068A (en) * 2003-12-09 2005-06-15 Advanced Risc Mach Ltd Data element size control within parallel lanes of processing
CN1306395C (zh) * 2004-02-13 2007-03-21 中国科学院计算技术研究所 Mips指令集的处理器扩展指令及其编码方法和部件
US8427490B1 (en) 2004-05-14 2013-04-23 Nvidia Corporation Validating a graphics pipeline using pre-determined schedules
US7395410B2 (en) * 2004-07-06 2008-07-01 Matsushita Electric Industrial Co., Ltd. Processor system with an improved instruction decode control unit that controls data transfer between processor and coprocessor
US8624906B2 (en) 2004-09-29 2014-01-07 Nvidia Corporation Method and system for non stalling pipeline instruction fetching from memory
US8424012B1 (en) 2004-11-15 2013-04-16 Nvidia Corporation Context switching on a video processor having a scalar execution unit and a vector execution unit
US20060179096A1 (en) * 2005-02-10 2006-08-10 International Business Machines Corporation System and method for a fused multiply-add dataflow with early feedback prior to rounding
US8250348B2 (en) * 2005-05-19 2012-08-21 International Business Machines Corporation Methods and apparatus for dynamically switching processor mode
US20060265555A1 (en) * 2005-05-19 2006-11-23 International Business Machines Corporation Methods and apparatus for sharing processor resources
US9092170B1 (en) 2005-10-18 2015-07-28 Nvidia Corporation Method and system for implementing fragment operation processing across a graphics bus interconnect
WO2007060932A1 (ja) * 2005-11-25 2007-05-31 Matsushita Electric Industrial Co., Ltd. 動的再構成論理回路を有するマルチスレッドプロセッサ
US20070186210A1 (en) * 2006-02-06 2007-08-09 Via Technologies, Inc. Instruction set encoding in a dual-mode computer processing environment
JP4934356B2 (ja) * 2006-06-20 2012-05-16 株式会社日立製作所 映像処理エンジンおよびそれを含む映像処理システム
US7865882B2 (en) * 2006-08-18 2011-01-04 International Business Machines Corporation Fast correctly rounding floating point conversion and identifying exceptional conversion
US9223751B2 (en) 2006-09-22 2015-12-29 Intel Corporation Performing rounding operations responsive to an instruction
US20080079713A1 (en) * 2006-09-28 2008-04-03 Eric Oliver Mejdrich Area Optimized Full Vector Width Vector Cross Product
US20080079712A1 (en) * 2006-09-28 2008-04-03 Eric Oliver Mejdrich Dual Independent and Shared Resource Vector Execution Units With Shared Register File
US7694193B2 (en) * 2007-03-13 2010-04-06 Hewlett-Packard Development Company, L.P. Systems and methods for implementing a stride value for accessing memory
US9024957B1 (en) 2007-08-15 2015-05-05 Nvidia Corporation Address independent shader program loading
US8411096B1 (en) 2007-08-15 2013-04-02 Nvidia Corporation Shader program instruction fetch
US8698819B1 (en) 2007-08-15 2014-04-15 Nvidia Corporation Software assisted shader merging
US8659601B1 (en) 2007-08-15 2014-02-25 Nvidia Corporation Program sequencer for generating indeterminant length shader programs for a graphics processor
CN101216756B (zh) * 2007-12-28 2011-03-23 中国科学院计算技术研究所 一种risc处理器装置及其模拟浮点栈操作的方法
US8681861B2 (en) 2008-05-01 2014-03-25 Nvidia Corporation Multistandard hardware video encoder
US8923385B2 (en) 2008-05-01 2014-12-30 Nvidia Corporation Rewind-enabled hardware encoder
US9690591B2 (en) * 2008-10-30 2017-06-27 Intel Corporation System and method for fusing instructions queued during a time window defined by a delay counter
US8489851B2 (en) 2008-12-11 2013-07-16 Nvidia Corporation Processing of read requests in a memory controller using pre-fetch mechanism
CN101819518B (zh) * 2009-02-26 2013-09-11 国际商业机器公司 在事务内存中快速保存上下文的方法和装置
US8341119B1 (en) * 2009-09-14 2012-12-25 Netapp, Inc. Flexible copies having different sub-types
CN101819516B (zh) * 2010-01-22 2014-04-16 龙芯中科技术有限公司 能够复用浮点操作用构件和向量操作用构件的处理器
US8606840B2 (en) * 2010-03-17 2013-12-10 Oracle International Corporation Apparatus and method for floating-point fused multiply add
US8495124B2 (en) * 2010-06-23 2013-07-23 International Business Machines Corporation Decimal floating point mechanism and process of multiplication without resultant leading zero detection
US8914430B2 (en) * 2010-09-24 2014-12-16 Intel Corporation Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions
US20120185670A1 (en) * 2011-01-14 2012-07-19 Toll Bret L Scalar integer instructions capable of execution with three registers
US20120216015A1 (en) * 2011-02-22 2012-08-23 Mitra Sumanranjan S System and method to concurrently execute a plurality of object oriented platform independent programs by utilizing memory accessible by both a processor and a co-processor
CN102200964B (zh) * 2011-06-17 2013-05-15 孙瑞琛 基于并行处理的fft装置及其方法
US9411585B2 (en) * 2011-09-16 2016-08-09 International Business Machines Corporation Multi-addressable register files and format conversions associated therewith
US9727336B2 (en) 2011-09-16 2017-08-08 International Business Machines Corporation Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers
US9946540B2 (en) 2011-12-23 2018-04-17 Intel Corporation Apparatus and method of improved permute instructions with multiple granularities
CN111831335A (zh) * 2011-12-23 2020-10-27 英特尔公司 经改进的插入指令的装置和方法
CN104011616B (zh) * 2011-12-23 2017-08-29 英特尔公司 改进置换指令的装置和方法
CN104126171B (zh) * 2011-12-27 2018-08-07 英特尔公司 用于基于两个源写掩码寄存器生成依赖向量的系统、装置和方法
US9632777B2 (en) 2012-08-03 2017-04-25 International Business Machines Corporation Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry
US9569211B2 (en) 2012-08-03 2017-02-14 International Business Machines Corporation Predication in a vector processor
US9575755B2 (en) 2012-08-03 2017-02-21 International Business Machines Corporation Vector processing in an active memory device
US9594724B2 (en) * 2012-08-09 2017-03-14 International Business Machines Corporation Vector register file
CN103281365B (zh) * 2013-05-20 2016-12-28 深圳市京华科讯科技有限公司 分布式虚拟化架构
US8626813B1 (en) * 2013-08-12 2014-01-07 Board Of Regents, The University Of Texas System Dual-path fused floating-point two-term dot product unit
US20150293767A1 (en) * 2014-04-11 2015-10-15 Fujitsu Limited Rotating register file with bit expansion support
GB2540943B (en) * 2015-07-31 2018-04-11 Advanced Risc Mach Ltd Vector arithmetic instruction
US10762164B2 (en) 2016-01-20 2020-09-01 Cambricon Technologies Corporation Limited Vector and matrix computing device
CN107704433A (zh) * 2016-01-20 2018-02-16 南京艾溪信息科技有限公司 一种矩阵运算指令及其方法
US10331449B2 (en) * 2016-01-22 2019-06-25 Arm Limited Encoding instructions identifying first and second architectural register numbers
CN111651201B (zh) * 2016-04-26 2023-06-13 中科寒武纪科技股份有限公司 一种用于执行向量合并运算的装置和方法
CN107315717B (zh) 2016-04-26 2020-11-03 中科寒武纪科技股份有限公司 一种用于执行向量四则运算的装置和方法
US10275243B2 (en) 2016-07-02 2019-04-30 Intel Corporation Interruptible and restartable matrix multiplication instructions, processors, methods, and systems
WO2018174931A1 (en) 2017-03-20 2018-09-27 Intel Corporation Systems, methods, and appartus for tile configuration
WO2019009870A1 (en) 2017-07-01 2019-01-10 Intel Corporation SAVE BACKGROUND TO VARIABLE BACKUP STATUS SIZE
US10474464B2 (en) * 2017-07-05 2019-11-12 Deep Vision, Inc. Deep vision processor
US10175912B1 (en) * 2017-07-05 2019-01-08 Google Llc Hardware double buffering using a special purpose computational unit
US11809869B2 (en) 2017-12-29 2023-11-07 Intel Corporation Systems and methods to store a tile register pair to memory
US11023235B2 (en) 2017-12-29 2021-06-01 Intel Corporation Systems and methods to zero a tile register pair
US11789729B2 (en) 2017-12-29 2023-10-17 Intel Corporation Systems and methods for computing dot products of nibbles in two tile operands
US11816483B2 (en) 2017-12-29 2023-11-14 Intel Corporation Systems, methods, and apparatuses for matrix operations
US11093247B2 (en) 2017-12-29 2021-08-17 Intel Corporation Systems and methods to load a tile register pair
US11669326B2 (en) 2017-12-29 2023-06-06 Intel Corporation Systems, methods, and apparatuses for dot product operations
US10664287B2 (en) 2018-03-30 2020-05-26 Intel Corporation Systems and methods for implementing chained tile operations
US11093579B2 (en) 2018-09-05 2021-08-17 Intel Corporation FP16-S7E8 mixed precision for deep learning and other algorithms
US10970076B2 (en) 2018-09-14 2021-04-06 Intel Corporation Systems and methods for performing instructions specifying ternary tile logic operations
US11579883B2 (en) 2018-09-14 2023-02-14 Intel Corporation Systems and methods for performing horizontal tile operations
US10866786B2 (en) 2018-09-27 2020-12-15 Intel Corporation Systems and methods for performing instructions to transpose rectangular tiles
US10719323B2 (en) 2018-09-27 2020-07-21 Intel Corporation Systems and methods for performing matrix compress and decompress instructions
EP3857353B1 (de) * 2018-09-27 2023-09-20 Intel Corporation Vorrichtungen und verfahren zur beschleunigung der matrixmultiplikation
US10990396B2 (en) 2018-09-27 2021-04-27 Intel Corporation Systems for performing instructions to quickly convert and use tiles as 1D vectors
US10896043B2 (en) 2018-09-28 2021-01-19 Intel Corporation Systems for performing instructions for fast element unpacking into 2-dimensional registers
US10963256B2 (en) 2018-09-28 2021-03-30 Intel Corporation Systems and methods for performing instructions to transform matrices into row-interleaved format
US10929143B2 (en) 2018-09-28 2021-02-23 Intel Corporation Method and apparatus for efficient matrix alignment in a systolic array
US10963246B2 (en) 2018-11-09 2021-03-30 Intel Corporation Systems and methods for performing 16-bit floating-point matrix dot product instructions
US10929503B2 (en) 2018-12-21 2021-02-23 Intel Corporation Apparatus and method for a masked multiply instruction to support neural network pruning operations
US11886875B2 (en) 2018-12-26 2024-01-30 Intel Corporation Systems and methods for performing nibble-sized operations on matrix elements
US11294671B2 (en) 2018-12-26 2022-04-05 Intel Corporation Systems and methods for performing duplicate detection instructions on 2D data
US20200210517A1 (en) 2018-12-27 2020-07-02 Intel Corporation Systems and methods to accelerate multiplication of sparse matrices
US10942985B2 (en) 2018-12-29 2021-03-09 Intel Corporation Apparatuses, methods, and systems for fast fourier transform configuration and computation instructions
US10922077B2 (en) 2018-12-29 2021-02-16 Intel Corporation Apparatuses, methods, and systems for stencil configuration and computation instructions
US11269630B2 (en) 2019-03-29 2022-03-08 Intel Corporation Interleaved pipeline of floating-point adders
US11016731B2 (en) 2019-03-29 2021-05-25 Intel Corporation Using Fuzzy-Jbit location of floating-point multiply-accumulate results
US11175891B2 (en) 2019-03-30 2021-11-16 Intel Corporation Systems and methods to perform floating-point addition with selected rounding
US10990397B2 (en) 2019-03-30 2021-04-27 Intel Corporation Apparatuses, methods, and systems for transpose instructions of a matrix operations accelerator
US11403097B2 (en) 2019-06-26 2022-08-02 Intel Corporation Systems and methods to skip inconsequential matrix operations
US11334647B2 (en) 2019-06-29 2022-05-17 Intel Corporation Apparatuses, methods, and systems for enhanced matrix multiplier architecture
CN110928577B (zh) * 2019-11-14 2021-11-05 中国人民解放军国防科技大学 一种带异常返回的向量存储指令的执行方法
US11714875B2 (en) 2019-12-28 2023-08-01 Intel Corporation Apparatuses, methods, and systems for instructions of a matrix operations accelerator
US20200218508A1 (en) * 2020-03-13 2020-07-09 Intel Corporation Floating-point decomposition circuitry with dynamic precision
US11513847B2 (en) 2020-03-24 2022-11-29 Deep Vision Inc. System and method for queuing commands in a deep learning processor
CN111459546B (zh) * 2020-03-30 2023-04-18 芯来智融半导体科技(上海)有限公司 一种实现操作数位宽可变的装置及方法
US12112167B2 (en) 2020-06-27 2024-10-08 Intel Corporation Matrix data scatter and gather between rows and irregularly spaced memory locations
US11972230B2 (en) 2020-06-27 2024-04-30 Intel Corporation Matrix transpose and multiply
US11941395B2 (en) 2020-09-26 2024-03-26 Intel Corporation Apparatuses, methods, and systems for instructions for 16-bit floating-point matrix dot product instructions
US12001887B2 (en) 2020-12-24 2024-06-04 Intel Corporation Apparatuses, methods, and systems for instructions for aligning tiles of a matrix operations accelerator
US12001385B2 (en) 2020-12-24 2024-06-04 Intel Corporation Apparatuses, methods, and systems for instructions for loading a tile of a matrix operations accelerator
CN112988236B (zh) * 2021-04-20 2023-04-14 浙江华忆芯科技有限公司 数据存储方法及装置、存储介质、电子装置
GB202112803D0 (en) 2021-09-08 2021-10-20 Graphcore Ltd Processing device using variable stride pattern
US11900116B1 (en) 2021-09-29 2024-02-13 International Business Machines Corporation Loosely-coupled slice target file data
US12001848B2 (en) * 2022-01-30 2024-06-04 Simplex Micro, Inc. Microprocessor with time counter for statically dispatching instructions with phantom registers
US11954491B2 (en) 2022-01-30 2024-04-09 Simplex Micro, Inc. Multi-threading microprocessor with a time counter for statically dispatching instructions
CN114816532B (zh) * 2022-04-20 2023-04-04 湖南卡姆派乐信息科技有限公司 一种提高risc-v二进制代码密度的寄存器分配方法
US12106114B2 (en) 2022-04-29 2024-10-01 Simplex Micro, Inc. Microprocessor with shared read and write buses and instruction issuance to multiple register sets in accordance with a time counter
US12112172B2 (en) 2022-06-01 2024-10-08 Simplex Micro, Inc. Vector coprocessor with time counter for statically dispatching instructions
CN115951936B (zh) * 2023-01-17 2023-05-26 上海燧原科技有限公司 向量化编译程序的芯片适配方法、装置、设备及介质

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3535694A (en) 1968-01-15 1970-10-20 Ibm Information transposing system
JPS5725069A (en) 1980-07-21 1982-02-09 Hitachi Ltd Vector data processing equipment
JPS61173345A (ja) 1985-01-29 1986-08-05 Hitachi Ltd 計算機システム
US4888679A (en) * 1988-01-11 1989-12-19 Digital Equipment Corporation Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements
US5261113A (en) * 1988-01-25 1993-11-09 Digital Equipment Corporation Apparatus and method for single operand register array for vector and scalar data processing operations
US5187796A (en) * 1988-03-29 1993-02-16 Computer Motion, Inc. Three-dimensional vector co-processor having I, J, and K register files and I, J, and K execution units
US5043886A (en) * 1988-09-16 1991-08-27 Digital Equipment Corporation Load/store with write-intent for write-back caches
US4969118A (en) * 1989-01-13 1990-11-06 International Business Machines Corporation Floating point unit for calculating A=XY+Z having simultaneous multiply and add
US5544337A (en) * 1989-12-29 1996-08-06 Cray Research, Inc. Vector processor having registers for control by vector resisters
US5197130A (en) * 1989-12-29 1993-03-23 Supercomputer Systems Limited Partnership Cluster architecture for a highly parallel scalar/vector multiprocessor system
DE69133072T2 (de) * 1990-08-24 2003-03-20 Matsushita Electric Industrial Co., Ltd. Verfahren und Gerät zur Berechnung von Gleitkommadaten
JP2718254B2 (ja) * 1990-10-02 1998-02-25 日本電気株式会社 ベクトル処理装置
US5437043A (en) 1991-11-20 1995-07-25 Hitachi, Ltd. Information processing apparatus having a register file used interchangeably both as scalar registers of register windows and as vector registers
US5717947A (en) * 1993-03-31 1998-02-10 Motorola, Inc. Data processing system and method thereof
US5669013A (en) 1993-10-05 1997-09-16 Fujitsu Limited System for transferring M elements X times and transferring N elements one time for an array that is X*M+N long responsive to vector type instructions
US5632023A (en) * 1994-06-01 1997-05-20 Advanced Micro Devices, Inc. Superscalar microprocessor including flag operand renaming and forwarding apparatus
GB2291515B (en) 1994-07-14 1998-11-18 Advanced Risc Mach Ltd Data processing using multiply-accumulate instructions
US5513366A (en) * 1994-09-28 1996-04-30 International Business Machines Corporation Method and system for dynamically reconfiguring a register file in a vector processor
US5548544A (en) * 1994-10-14 1996-08-20 Ibm Corporation Method and apparatus for rounding the result of an arithmetic operation
US5550767A (en) * 1994-10-14 1996-08-27 Ibm Corporation Method and apparatus for detecting underflow and overflow
US5537606A (en) 1995-01-31 1996-07-16 International Business Machines Corporation Scalar pipeline replication for parallel vector element processing
US5867413A (en) * 1995-10-17 1999-02-02 Hitachi Micro Systems, Inc. Fast method of floating-point multiplication and accumulation
US5822606A (en) * 1996-01-11 1998-10-13 Morton; Steven G. DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word
US5892698A (en) * 1996-04-04 1999-04-06 Hewlett-Packard Company 2's complement floating-point multiply accumulate unit
US5838984A (en) * 1996-08-19 1998-11-17 Samsung Electronics Co., Ltd. Single-instruction-multiple-data processing using multiple banks of vector registers
US5917741A (en) * 1996-08-29 1999-06-29 Intel Corporation Method and apparatus for performing floating-point rounding operations for multiple precisions using incrementers
US5805875A (en) * 1996-09-13 1998-09-08 International Computer Science Institute Vector processing system with multi-operation, run-time configurable pipelines
US6006315A (en) * 1996-10-18 1999-12-21 Samsung Electronics Co., Ltd. Computer methods for writing a scalar value to a vector
US5991531A (en) * 1997-02-24 1999-11-23 Samsung Electronics Co., Ltd. Scalable width vector processor architecture for efficient emulation
US6282634B1 (en) * 1998-05-27 2001-08-28 Arm Limited Apparatus and method for processing data having a mixed vector/scalar register file
US6115729A (en) * 1998-08-20 2000-09-05 Arm Limited Floating point multiply-accumulate unit
US6148314A (en) * 1998-08-28 2000-11-14 Arm Limited Round increment in an adder circuit

Also Published As

Publication number Publication date
JP2002517037A (ja) 2002-06-11
CN1303501A (zh) 2001-07-11
IL139250A0 (en) 2001-11-25
WO1999061996A1 (en) 1999-12-02
CN1191535C (zh) 2005-03-02
KR20010043772A (ko) 2001-05-25
EP1080420B1 (de) 2002-06-05
RU2212049C2 (ru) 2003-09-10
US6360189B1 (en) 2002-03-19
EP1080420A1 (de) 2001-03-07
TW413766B (en) 2000-12-01
US6332186B1 (en) 2001-12-18
MY125652A (en) 2006-08-30
KR100563219B1 (ko) 2006-03-22
US6282634B1 (en) 2001-08-28
DE69901708T2 (de) 2002-12-05

Similar Documents

Publication Publication Date Title
DE69901708D1 (de) Gemischter vektor/skalar-registersatz
GB0009284D0 (en) Processor utilizing template field instruction encoding
DE59913438D1 (de) Pigmentmischung
DE59804033D1 (de) Halteband
DK0674888T3 (da) Blandeindretning
DE69711357D1 (de) Bodenbelüfter
FI974481A0 (fi) Antenn
KR100524623B1 (ko) 혼합 장치
NO20000857D0 (no) Mikseapparat
DE19881927T1 (de) Elektromagnetische Verschiebeeinrichtung
DE69926557D1 (de) Reduziertes Vektor Raster
GB0108870D0 (en) Vector
DE59900656D1 (de) Mischvorrichtung
ID28046A (id) Vektor propionibacterium
DE59803259D1 (de) Mischvorrichtung
GB9827963D0 (en) Instruction execution mechanism
ID26779A (id) Campuran-campuran kasturi makrosiklik
DE19983309T1 (de) Mischersystem
DE69938795D1 (de) Gurtschloss
FR2766896B1 (fr) Mitigeur mono-commande
ID25932A (id) Campuran-campuran kapet yang mengandung organosilanapolisulfana
GB9825303D0 (en) Vector
DK1004236T3 (da) Blandingsindretning
ATA211098A (de) Gasmischer
ATE230756T1 (de) B-ring estratriendiol-sulfate

Legal Events

Date Code Title Description
8364 No opposition during term of opposition