DE69901247T2 - Direktspeicherzugriff in einer brücke für ein mehrprozessorsystem - Google Patents

Direktspeicherzugriff in einer brücke für ein mehrprozessorsystem

Info

Publication number
DE69901247T2
DE69901247T2 DE69901247T DE69901247T DE69901247T2 DE 69901247 T2 DE69901247 T2 DE 69901247T2 DE 69901247 T DE69901247 T DE 69901247T DE 69901247 T DE69901247 T DE 69901247T DE 69901247 T2 DE69901247 T2 DE 69901247T2
Authority
DE
Germany
Prior art keywords
bus
bridge
processing set
address
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69901247T
Other languages
German (de)
English (en)
Other versions
DE69901247D1 (de
Inventor
J. Garnett
A. Oyelakin
Stephen Rowlinson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE69901247D1 publication Critical patent/DE69901247D1/de
Publication of DE69901247T2 publication Critical patent/DE69901247T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Bus Control (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
DE69901247T 1998-06-15 1999-06-14 Direktspeicherzugriff in einer brücke für ein mehrprozessorsystem Expired - Fee Related DE69901247T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/094,842 US6223230B1 (en) 1998-06-15 1998-06-15 Direct memory access in a bridge for a multi-processor system
PCT/US1999/013385 WO1999066410A1 (en) 1998-06-15 1999-06-14 Direct memory access in a bridge for a multi-processor system

Publications (2)

Publication Number Publication Date
DE69901247D1 DE69901247D1 (de) 2002-05-16
DE69901247T2 true DE69901247T2 (de) 2002-11-28

Family

ID=22247497

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69901247T Expired - Fee Related DE69901247T2 (de) 1998-06-15 1999-06-14 Direktspeicherzugriff in einer brücke für ein mehrprozessorsystem

Country Status (6)

Country Link
US (1) US6223230B1 (enExample)
EP (1) EP1086425B1 (enExample)
JP (1) JP2002518742A (enExample)
AT (1) ATE216099T1 (enExample)
DE (1) DE69901247T2 (enExample)
WO (1) WO1999066410A1 (enExample)

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US6484227B1 (en) * 1999-08-23 2002-11-19 Advanced Micro Devices, Inc. Method and apparatus for overlapping programmable address regions
US6738845B1 (en) * 1999-11-05 2004-05-18 Analog Devices, Inc. Bus architecture and shared bus arbitration method for a communication device
WO2001079962A2 (en) * 2000-04-13 2001-10-25 Stratus Technologies International, S.A.R.L. Fault-tolerant maintenance bus, protocol, and method for using the same
US7080183B1 (en) * 2000-08-16 2006-07-18 Koninklijke Philips Electronics N.V. Reprogrammable apparatus supporting the processing of a digital signal stream and method
GB2369692B (en) * 2000-11-29 2002-10-16 Sun Microsystems Inc Processor state reintegration
US6665759B2 (en) * 2001-03-01 2003-12-16 International Business Machines Corporation Method and apparatus to implement logical partitioning of PCI I/O slots
JP2003281071A (ja) * 2002-03-20 2003-10-03 Seiko Epson Corp データ転送制御装置、電子機器及びデータ転送制御方法
US6968415B2 (en) * 2002-03-29 2005-11-22 International Business Machines Corporation Opaque memory region for I/O adapter transparent bridge
US7103691B2 (en) * 2003-03-04 2006-09-05 Hewlett-Packard Development Company, L.P. Method, system and device for a processor to access devices of different speeds using a standard memory bus
US7194663B2 (en) * 2003-11-18 2007-03-20 Honeywell International, Inc. Protective bus interface and method
KR100606163B1 (ko) * 2004-07-10 2006-08-01 삼성전자주식회사 디렉트 메모리 엑세스 장치, 디렉트 메모리 엑세스 장치를통한 데이터를 송수신하는 시스템 및 방법
US7886086B2 (en) * 2005-02-03 2011-02-08 International Business Machines Corporation Method and apparatus for restricting input/output device peer-to-peer operations in a data processing system to improve reliability, availability, and serviceability
US8676923B2 (en) * 2005-03-08 2014-03-18 International Business Machines Corporation Use of discovery scanning and method of IP only communication to identify owners and administrators of network attached devices
US7669073B2 (en) * 2005-08-19 2010-02-23 Stratus Technologies Bermuda Ltd. Systems and methods for split mode operation of fault-tolerant computer systems
US8041851B2 (en) * 2005-11-30 2011-10-18 International Business Machines Corporation Generic DMA memory space mapping
US20080082715A1 (en) * 2006-09-29 2008-04-03 Honeywell International Inc. Data transfers over multiple data buses
US20100010992A1 (en) * 2008-07-10 2010-01-14 Morris Robert P Methods And Systems For Resolving A Location Information To A Network Identifier
US20100011048A1 (en) * 2008-07-10 2010-01-14 Morris Robert P Methods And Systems For Resolving A Geospatial Query Region To A Network Identifier
US20100010975A1 (en) * 2008-07-10 2010-01-14 Morris Robert P Methods And Systems For Resolving A Query Region To A Network Identifier
US20100145963A1 (en) * 2008-12-04 2010-06-10 Morris Robert P Methods, Systems, And Computer Program Products For Resolving A Network Identifier Based On A Geospatial Domain Space Harmonized With A Non-Geospatial Domain Space
US20100162129A1 (en) * 2008-12-19 2010-06-24 Morris Robert P Methods, Systems, And Computer Program Products For Synchronizing Second Level Resources With First Level Resources Of A Multi-Level Navigation History
US20100161732A1 (en) * 2008-12-19 2010-06-24 Morris Robert P Methods, Systems, And Computer Program Products For Maintaining Consistency Between Non-Geospatial And Geospatial Network Directory Systems
US7933272B2 (en) * 2009-03-11 2011-04-26 Deep River Systems, Llc Methods and systems for resolving a first node identifier in a first identifier domain space to a second node identifier in a second identifier domain space
US20100250777A1 (en) * 2009-03-30 2010-09-30 Morris Robert P Methods, Systems, And Computer Program Products For Resolving A First Source Node Identifier To A Second Source Node Identifier
EP2418580B1 (de) * 2010-08-10 2012-10-10 Siemens Aktiengesellschaft Verfahren zum Betreiben eines Netzwerkes und Netzwerk
US8797799B2 (en) * 2012-01-05 2014-08-05 Conversant Intellectual Property Management Inc. Device selection schemes in multi chip package NAND flash memory system

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US4627017A (en) * 1980-10-22 1986-12-02 International Business Machines Corporation Address range determination
US4926322A (en) * 1987-08-03 1990-05-15 Compag Computer Corporation Software emulation of bank-switched memory using a virtual DOS monitor and paged memory management
JP2910303B2 (ja) * 1990-06-04 1999-06-23 株式会社日立製作所 情報処理装置
EP0481735A3 (en) * 1990-10-19 1993-01-13 Array Technology Corporation Address protection circuit
GB2268817B (en) 1992-07-17 1996-05-01 Integrated Micro Products Ltd A fault-tolerant computer system
US5644709A (en) * 1994-04-21 1997-07-01 Wisconsin Alumni Research Foundation Method for detecting computer memory access errors
JP3454294B2 (ja) 1994-06-20 2003-10-06 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプル・バス情報処理システム及びブリッジ回路
US5586253A (en) * 1994-12-15 1996-12-17 Stratus Computer Method and apparatus for validating I/O addresses in a fault-tolerant computer system
US5628029A (en) * 1995-02-03 1997-05-06 Vlsi Technology, Inc. Apparatus for monitoring distributed I/O device by providing a monitor in each I/O device control for generating signals based upon the device status
US5682512A (en) * 1995-06-30 1997-10-28 Intel Corporation Use of deferred bus access for address translation in a shared memory clustered computer system
US5953538A (en) * 1996-11-12 1999-09-14 Digital Equipment Corporation Method and apparatus providing DMA transfers between devices coupled to different host bus bridges
US5991900A (en) * 1998-06-15 1999-11-23 Sun Microsystems, Inc. Bus controller

Also Published As

Publication number Publication date
WO1999066410A1 (en) 1999-12-23
ATE216099T1 (de) 2002-04-15
EP1086425B1 (en) 2002-04-10
DE69901247D1 (de) 2002-05-16
EP1086425A1 (en) 2001-03-28
JP2002518742A (ja) 2002-06-25
US6223230B1 (en) 2001-04-24

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee