DE69835100T2 - Prozessor konfiguriert um vorausschauende resultate von zusammengefassten übertragungs-, vergleichs- und einfachen arithmetischen befehlen zu produzieren - Google Patents

Prozessor konfiguriert um vorausschauende resultate von zusammengefassten übertragungs-, vergleichs- und einfachen arithmetischen befehlen zu produzieren Download PDF

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Publication number
DE69835100T2
DE69835100T2 DE69835100T DE69835100T DE69835100T2 DE 69835100 T2 DE69835100 T2 DE 69835100T2 DE 69835100 T DE69835100 T DE 69835100T DE 69835100 T DE69835100 T DE 69835100T DE 69835100 T2 DE69835100 T2 DE 69835100T2
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Prior art keywords
instruction
operand
unit
instructions
operands
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Expired - Lifetime
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DE69835100T
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German (de)
English (en)
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DE69835100D1 (de
Inventor
B. David Austin WITT
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GlobalFoundries Inc
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Advanced Micro Devices Inc
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Publication of DE69835100T2 publication Critical patent/DE69835100T2/de
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Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE69835100T 1997-11-17 1998-10-19 Prozessor konfiguriert um vorausschauende resultate von zusammengefassten übertragungs-, vergleichs- und einfachen arithmetischen befehlen zu produzieren Expired - Lifetime DE69835100T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US6587897P 1997-11-17 1997-11-17
US65878P 1997-11-17
US115123 1998-07-14
US09/115,123 US6112293A (en) 1997-11-17 1998-07-14 Processor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead result
PCT/US1998/022030 WO1999026132A2 (en) 1997-11-17 1998-10-19 Processor configured to generate lookahead results from collapsed moves, compares and simple arithmetic instructions

Publications (2)

Publication Number Publication Date
DE69835100D1 DE69835100D1 (de) 2006-08-10
DE69835100T2 true DE69835100T2 (de) 2007-02-01

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DE69835100T Expired - Lifetime DE69835100T2 (de) 1997-11-17 1998-10-19 Prozessor konfiguriert um vorausschauende resultate von zusammengefassten übertragungs-, vergleichs- und einfachen arithmetischen befehlen zu produzieren

Country Status (5)

Country Link
US (1) US6112293A (enExample)
EP (1) EP1031074B1 (enExample)
JP (1) JP3866918B2 (enExample)
DE (1) DE69835100T2 (enExample)
WO (1) WO1999026132A2 (enExample)

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US6952827B1 (en) * 1998-11-13 2005-10-04 Cray Inc. User program and operating system interface in a multithreaded environment
US6480818B1 (en) * 1998-11-13 2002-11-12 Cray Inc. Debugging techniques in a multithreaded environment
US6189091B1 (en) * 1998-12-02 2001-02-13 Ip First, L.L.C. Apparatus and method for speculatively updating global history and restoring same on branch misprediction detection
US6230313B1 (en) * 1998-12-23 2001-05-08 Cray Inc. Parallelism performance analysis based on execution trace information
US6665688B1 (en) 1998-12-23 2003-12-16 Cray Inc. Method and system for automatically regenerating data on-demand
US6353829B1 (en) 1998-12-23 2002-03-05 Cray Inc. Method and system for memory allocation in a multiprocessing environment
US6321379B1 (en) 1998-12-23 2001-11-20 Cray Inc. Method and system for target register allocation
US6430676B1 (en) * 1998-12-23 2002-08-06 Cray Inc. Method and system for calculating instruction lookahead
US6415433B1 (en) 1998-12-23 2002-07-02 Cray Inc. Method and system for identifying locations to move portions of the computer program
US6247097B1 (en) * 1999-01-22 2001-06-12 International Business Machines Corporation Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions
US6499101B1 (en) 1999-03-18 2002-12-24 I.P. First L.L.C. Static branch prediction mechanism for conditional branch instructions
US6343359B1 (en) * 1999-05-18 2002-01-29 Ip-First, L.L.C. Result forwarding cache
US6546481B1 (en) 1999-11-05 2003-04-08 Ip - First Llc Split history tables for branch prediction
US6629234B1 (en) * 2000-03-30 2003-09-30 Ip. First, L.L.C. Speculative generation at address generation stage of previous instruction result stored in forward cache for use by succeeding address dependent instruction
US6782469B1 (en) * 2000-09-29 2004-08-24 Intel Corporation Runtime critical load/data ordering
US7107438B2 (en) * 2003-02-04 2006-09-12 Via Technologies, Inc. Pipelined microprocessor, apparatus, and method for performing early correction of conditional branch instruction mispredictions
US7185182B2 (en) * 2003-02-04 2007-02-27 Via Technologies, Inc. Pipelined microprocessor, apparatus, and method for generating early instruction results
US7100024B2 (en) 2003-02-04 2006-08-29 Via Technologies, Inc. Pipelined microprocessor, apparatus, and method for generating early status flags
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US20050216713A1 (en) * 2004-03-25 2005-09-29 International Business Machines Corporation Instruction text controlled selectively stated branches for prediction via a branch target buffer
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US7243210B2 (en) * 2005-05-31 2007-07-10 Atmel Corporation Extracted-index addressing of byte-addressable memories
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US20090182984A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Execute Relative Long Facility and Instructions Therefore
US20090182985A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Move Facility and Instructions Therefore
US7739434B2 (en) 2008-01-11 2010-06-15 International Business Machines Corporation Performing a configuration virtual topology change and instruction therefore
US20090182992A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Load Relative and Store Relative Facility and Instructions Therefore
US7734900B2 (en) 2008-01-11 2010-06-08 International Business Machines Corporation Computer configuration virtual topology discovery and instruction therefore
US7895419B2 (en) 2008-01-11 2011-02-22 International Business Machines Corporation Rotate then operate on selected bits facility and instructions therefore
US9280480B2 (en) 2008-01-11 2016-03-08 International Business Machines Corporation Extract target cache attribute facility and instruction therefor
US20090182988A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Compare Relative Long Facility and Instructions Therefore
US9690591B2 (en) 2008-10-30 2017-06-27 Intel Corporation System and method for fusing instructions queued during a time window defined by a delay counter
US8966230B2 (en) * 2009-09-30 2015-02-24 Intel Corporation Dynamic selection of execution stage
JP2013131036A (ja) * 2011-12-21 2013-07-04 Fujitsu Ltd 演算処理装置及び演算処理装置の制御方法
CN103984637A (zh) * 2013-02-07 2014-08-13 上海芯豪微电子有限公司 一种指令处理系统及方法
GB2518613A (en) 2013-09-25 2015-04-01 Ibm Multiple core processing with high throughput atomic memory operations
CN106406820B (zh) * 2015-07-29 2019-01-15 深圳市中兴微电子技术有限公司 一种网络处理器微引擎的多发射指令并行处理方法及装置
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Also Published As

Publication number Publication date
JP3866918B2 (ja) 2007-01-10
EP1031074B1 (en) 2006-06-28
US6112293A (en) 2000-08-29
WO1999026132A2 (en) 1999-05-27
DE69835100D1 (de) 2006-08-10
JP2001523854A (ja) 2001-11-27
WO1999026132A3 (en) 1999-09-16
EP1031074A2 (en) 2000-08-30

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Legal Events

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8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY

8328 Change in the person/name/address of the agent

Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER,