DE69831370D1 - Verfahren und Vorrichtung zur Steuerung der Ausführung bedingter Verzweigungen in einem Datenprozessor - Google Patents

Verfahren und Vorrichtung zur Steuerung der Ausführung bedingter Verzweigungen in einem Datenprozessor

Info

Publication number
DE69831370D1
DE69831370D1 DE69831370T DE69831370T DE69831370D1 DE 69831370 D1 DE69831370 D1 DE 69831370D1 DE 69831370 T DE69831370 T DE 69831370T DE 69831370 T DE69831370 T DE 69831370T DE 69831370 D1 DE69831370 D1 DE 69831370D1
Authority
DE
Germany
Prior art keywords
execution
controlling
data processor
conditional branches
conditional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69831370T
Other languages
English (en)
Other versions
DE69831370T2 (de
Inventor
William C Moyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of DE69831370D1 publication Critical patent/DE69831370D1/de
Application granted granted Critical
Publication of DE69831370T2 publication Critical patent/DE69831370T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE69831370T 1997-07-25 1998-06-02 Verfahren und Vorrichtung zur Steuerung der Ausführung bedingter Verzweigungen in einem Datenprozessor Expired - Fee Related DE69831370T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/900,796 US5951678A (en) 1997-07-25 1997-07-25 Method and apparatus for controlling conditional branch execution in a data processor
US900796 1997-07-25

Publications (2)

Publication Number Publication Date
DE69831370D1 true DE69831370D1 (de) 2005-10-06
DE69831370T2 DE69831370T2 (de) 2006-03-09

Family

ID=25413089

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69831370T Expired - Fee Related DE69831370T2 (de) 1997-07-25 1998-06-02 Verfahren und Vorrichtung zur Steuerung der Ausführung bedingter Verzweigungen in einem Datenprozessor

Country Status (5)

Country Link
US (1) US5951678A (de)
EP (1) EP0893756B1 (de)
JP (1) JP3977931B2 (de)
KR (1) KR100570906B1 (de)
DE (1) DE69831370T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1645956A3 (de) * 1997-08-29 2008-02-13 Matsushita Electric Industrial Co., Ltd. Anordnung zur Befehlsumwandlung um der Anzahl von Befehlsarten zu reduzieren
US6353880B1 (en) * 1998-07-22 2002-03-05 Scenix Semiconductor, Inc. Four stage pipeline processing for a microcontroller
DE69923289D1 (de) * 1999-04-28 2005-02-24 St Microelectronics Srl Halbleitervorrichtung mit auswälbarer Anschlussfläche
US6859875B1 (en) 2000-06-12 2005-02-22 Freescale Semiconductor, Inc. Processor having selective branch prediction
US7168005B2 (en) * 2000-09-14 2007-01-23 Cadence Design Systems, Inc. Programable multi-port memory BIST with compact microcode
US6662294B1 (en) * 2000-09-28 2003-12-09 International Business Machines Corporation Converting short branches to predicated instructions
US6948054B2 (en) * 2000-11-29 2005-09-20 Lsi Logic Corporation Simple branch prediction and misprediction recovery method
TW477954B (en) * 2000-12-05 2002-03-01 Faraday Tech Corp Memory data accessing architecture and method for a processor
US6957306B2 (en) * 2002-09-09 2005-10-18 Broadcom Corporation System and method for controlling prefetching
US7103757B1 (en) * 2002-10-22 2006-09-05 Lsi Logic Corporation System, circuit, and method for adjusting the prefetch instruction rate of a prefetch unit
US7139902B2 (en) * 2002-10-29 2006-11-21 Broadcom Corporation Implementation of an efficient instruction fetch pipeline utilizing a trace cache
US7140003B2 (en) * 2003-02-14 2006-11-21 International Business Machines Corporation Method and system for specifying sets of instructions for selection by an instruction generator
US7013383B2 (en) * 2003-06-24 2006-03-14 Via-Cyrix, Inc. Apparatus and method for managing a processor pipeline in response to exceptions
KR100591769B1 (ko) 2004-07-16 2006-06-26 삼성전자주식회사 분기 예측 정보를 가지는 분기 타겟 버퍼
US7979675B2 (en) * 2009-02-12 2011-07-12 Via Technologies, Inc. Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution
US8131984B2 (en) * 2009-02-12 2012-03-06 Via Technologies, Inc. Pipelined microprocessor with fast conditional branch instructions based on static serializing instruction state

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4742451A (en) * 1984-05-21 1988-05-03 Digital Equipment Corporation Instruction prefetch system for conditional branch instruction for central processor unit
US5228131A (en) * 1988-02-24 1993-07-13 Mitsubishi Denki Kabushiki Kaisha Data processor with selectively enabled and disabled branch prediction operation
US4974155A (en) * 1988-08-15 1990-11-27 Evans & Sutherland Computer Corp. Variable delay branch system
CA2045791A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites Branch performance in high speed processor
US5261063A (en) * 1990-12-07 1993-11-09 Ibm Corp. Pipeline apparatus having pipeline mode eecuting instructions from plural programs and parallel mode executing instructions from one of the plural programs
US5623615A (en) * 1994-08-04 1997-04-22 International Business Machines Corporation Circuit and method for reducing prefetch cycles on microprocessors
JPH08106387A (ja) * 1994-10-06 1996-04-23 Oki Electric Ind Co Ltd 命令プリフェッチ回路及びキャッシュ装置
US5701448A (en) * 1995-12-15 1997-12-23 Cyrix Corporation Detecting segment limit violations for branch target when the branch unit does not supply the linear address
US5734881A (en) * 1995-12-15 1998-03-31 Cyrix Corporation Detecting short branches in a prefetch buffer using target location information in a branch target cache

Also Published As

Publication number Publication date
EP0893756A2 (de) 1999-01-27
EP0893756B1 (de) 2005-08-31
JPH1196004A (ja) 1999-04-09
JP3977931B2 (ja) 2007-09-19
KR19990014132A (ko) 1999-02-25
DE69831370T2 (de) 2006-03-09
KR100570906B1 (ko) 2006-10-24
EP0893756A3 (de) 2000-11-15
US5951678A (en) 1999-09-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: SCHUMACHER & WILLSAU PATENTANWALTSGESELLSCHAFT MBH

8339 Ceased/non-payment of the annual fee