DE69828813D1 - Mehrdimensionale struktur eines cachekohärenzverzeichnisses - Google Patents

Mehrdimensionale struktur eines cachekohärenzverzeichnisses

Info

Publication number
DE69828813D1
DE69828813D1 DE69828813T DE69828813T DE69828813D1 DE 69828813 D1 DE69828813 D1 DE 69828813D1 DE 69828813 T DE69828813 T DE 69828813T DE 69828813 T DE69828813 T DE 69828813T DE 69828813 D1 DE69828813 D1 DE 69828813D1
Authority
DE
Germany
Prior art keywords
cache coherence
coherence directory
multidimensional structure
multidimensional
directory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69828813T
Other languages
English (en)
Other versions
DE69828813T2 (de
Inventor
S Passint
L Scott
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Graphics Properties Holdings Inc
Original Assignee
Silicon Graphics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Graphics Inc filed Critical Silicon Graphics Inc
Application granted granted Critical
Publication of DE69828813D1 publication Critical patent/DE69828813D1/de
Publication of DE69828813T2 publication Critical patent/DE69828813T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0826—Limited pointers directories; State-only directories without pointers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69828813T 1997-11-17 1998-11-17 Mehrdimensionale struktur eines cachekohärenzverzeichnisses Expired - Lifetime DE69828813T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US971184 1997-11-17
US08/971,184 US6633958B1 (en) 1997-11-17 1997-11-17 Multiprocessor computer system and method for maintaining cache coherence utilizing a multi-dimensional cache coherence directory structure
PCT/US1998/024492 WO1999026144A1 (en) 1997-11-17 1998-11-17 Multi-dimensional cache coherence directory structure

Publications (2)

Publication Number Publication Date
DE69828813D1 true DE69828813D1 (de) 2005-03-03
DE69828813T2 DE69828813T2 (de) 2005-11-17

Family

ID=25518033

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69828813T Expired - Lifetime DE69828813T2 (de) 1997-11-17 1998-11-17 Mehrdimensionale struktur eines cachekohärenzverzeichnisses

Country Status (4)

Country Link
US (1) US6633958B1 (de)
EP (1) EP1031085B1 (de)
DE (1) DE69828813T2 (de)
WO (1) WO1999026144A1 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6295598B1 (en) * 1998-06-30 2001-09-25 Src Computers, Inc. Split directory-based cache coherency technique for a multi-processor computer system
US6751698B1 (en) * 1999-09-29 2004-06-15 Silicon Graphics, Inc. Multiprocessor node controller circuit and method
US6915388B1 (en) * 2000-07-20 2005-07-05 Silicon Graphics, Inc. Method and system for efficient use of a multi-dimensional sharing vector in a computer system
US6718442B1 (en) * 2000-07-20 2004-04-06 Silicon Graphics, Inc. Method and system for using high count invalidate acknowledgements in distributed shared memory systems
US6868481B1 (en) * 2000-10-31 2005-03-15 Hewlett-Packard Development Company, L.P. Cache coherence protocol for a multiple bus multiprocessor system
US7069545B2 (en) * 2000-12-29 2006-06-27 Intel Corporation Quantization and compression for computation reuse
US7836329B1 (en) 2000-12-29 2010-11-16 3Par, Inc. Communication link protocol optimized for storage architectures
US6973484B1 (en) * 2000-12-29 2005-12-06 3Pardata, Inc. Method of communicating data in an interconnect system
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7636815B1 (en) * 2003-04-09 2009-12-22 Klaiber Alexander C System and method for handling direct memory accesses
US8751753B1 (en) 2003-04-09 2014-06-10 Guillermo J. Rozas Coherence de-coupling buffer
US7971002B1 (en) 2005-04-07 2011-06-28 Guillermo Rozas Maintaining instruction coherency in a translation-based computer system architecture
US7624234B2 (en) 2006-08-31 2009-11-24 Hewlett-Packard Development Company, L.P. Directory caches, and methods for operation thereof
US7657710B2 (en) * 2006-11-17 2010-02-02 Sun Microsystems, Inc. Cache coherence protocol with write-only permission
US7827357B2 (en) 2007-07-31 2010-11-02 Intel Corporation Providing an inclusive shared cache among multiple core-cache clusters
US9411733B2 (en) * 2011-09-09 2016-08-09 University Of Rochester Sharing pattern-based directory coherence for multicore scalability (“SPACE”)
JP5573829B2 (ja) * 2011-12-20 2014-08-20 富士通株式会社 情報処理装置およびメモリアクセス方法
WO2014021853A1 (en) * 2012-07-31 2014-02-06 Empire Technology Development Llc Directory error correction in multi-core processor architectures
US20150067246A1 (en) * 2013-08-29 2015-03-05 Apple Inc Coherence processing employing black box duplicate tags
US9372800B2 (en) 2014-03-07 2016-06-21 Cavium, Inc. Inter-chip interconnect protocol for a multi-chip system
US20150254182A1 (en) * 2014-03-07 2015-09-10 Cavium, Inc. Multi-core network processor interconnect with multi-node connection
US9411644B2 (en) 2014-03-07 2016-08-09 Cavium, Inc. Method and system for work scheduling in a multi-chip system
US9529532B2 (en) 2014-03-07 2016-12-27 Cavium, Inc. Method and apparatus for memory allocation in a multi-node system
US10592459B2 (en) 2014-03-07 2020-03-17 Cavium, Llc Method and system for ordering I/O access in a multi-node environment
US9836277B2 (en) * 2014-10-01 2017-12-05 Samsung Electronics Co., Ltd. In-memory popcount support for real time analytics
US9424192B1 (en) 2015-04-02 2016-08-23 International Business Machines Corporation Private memory table for reduced memory coherence traffic
US9842050B2 (en) 2015-04-30 2017-12-12 International Business Machines Corporation Add-on memory coherence directory

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5265232A (en) * 1991-04-03 1993-11-23 International Business Machines Corporation Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data
US5680576A (en) 1995-05-05 1997-10-21 Silicon Graphics, Inc. Directory-based coherence protocol allowing efficient dropping of clean-exclusive data
US5634110A (en) 1995-05-05 1997-05-27 Silicon Graphics, Inc. Cache coherency using flexible directory bit vectors
US5778437A (en) * 1995-09-25 1998-07-07 International Business Machines Corporation Invalidation bus optimization for multiprocessors using directory-based cache coherence protocols in which an address of a line to be modified is placed on the invalidation bus simultaneously with sending a modify request to the directory
US5787477A (en) * 1996-06-18 1998-07-28 International Business Machines Corporation Multi-processor cache coherency protocol allowing asynchronous modification of cache data
US5752258A (en) * 1996-07-01 1998-05-12 Sun Microsystems, Inc. Encoding method for directory state in cache coherent distributed shared memory system
US5900015A (en) * 1996-08-09 1999-05-04 International Business Machines Corporation System and method for maintaining cache coherency using path directories

Also Published As

Publication number Publication date
DE69828813T2 (de) 2005-11-17
WO1999026144A1 (en) 1999-05-27
EP1031085B1 (de) 2005-01-26
US6633958B1 (en) 2003-10-14
EP1031085A1 (de) 2000-08-30

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